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Subversion Repositories scan_based_serial_communication

[/] [scan_based_serial_communication/] [trunk/] [scan.perl.v] - Blame information for rev 13

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////////////////////////////////////////////////////////////////////////////////
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module scan (
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              // Inputs & outputs to the chip
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             PERL begin
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             /*
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              DEPERLIFY_INCLUDE(scan_signal_list.pl);
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              for (my $i = 0; $i < scalar @signal_list; $i++) {
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                 print "              $signal_list[$i]{name},\n";
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              }
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              */
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             end
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              // To the pads
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              scan_phi,
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              scan_phi_bar,
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              scan_data_in,
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              scan_data_out,
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              scan_load_chip,
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              scan_load_chain
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              );
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   // /////////////////////////////////////////////////////////////////////
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   // Ports
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   // Scans
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   input   scan_phi;
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   input   scan_phi_bar;
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   input   scan_data_in;
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   output  scan_data_out;
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   input   scan_load_chain;
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   input   scan_load_chip;
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   PERL begin
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      /*
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       DEPERLIFY_INCLUDE(scan_signal_list.pl);
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       for (my $i = 0; $i < scalar @signal_list; $i++) {
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           if ($signal_list[$i]{writable} == 1) {
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                print "   output reg ";
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           } else {
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                print "   input      ";
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           }
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            print "[$signal_list[$i]{size}-1:0]  $signal_list[$i]{name};\n";
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       }
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       */
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   end
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   // /////////////////////////////////////////////////////////////////////
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   // Implementation
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   // The scan chain is comprised of two sets of latches: scan_master and scan_slave.
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   PERL begin
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      /*
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       ##############################################################
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       # Modify scan_signal_list.pl in order to change the signals. #
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       ##############################################################
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       DEPERLIFY_INCLUDE(scan_signal_list.pl);
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       # Print scan chain latches
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       print "   reg [$scan_chain_length-1:0] scan_master;\n";
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       print "   reg [$scan_chain_length-1:0] scan_slave;\n\n";
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       # Print scan_load and scan_next logic
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       print "   reg  [$scan_chain_length-1:0] scan_load;\n";
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       print "   wire [$scan_chain_length-1:0] scan_next;\n\n";
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       print "   always @ (*) begin\n";
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       for (my $i = 0; $i < scalar @signal_list; $i++) {
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          my $name      = $signal_list[$i]{name};
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          my $size      = $signal_list[$i]{size};
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          my $addr_bits = $signal_list[$i]{addr_bits};
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          my $data_bits = $signal_list[$i]{data_bits};
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          my $size_begin = $signal_list[$i]{start};
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          my $size_end   = $size_begin + $size - 1;
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          my $addr_begin = $signal_list[$i]{start};
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          my $addr_end   = $addr_begin + $addr_bits - 1;
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          my $data_begin = $addr_end + 1;
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          my $data_end   = $data_begin + $data_bits - 1;
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          if ($signal_list[$i]{addr_bits} == 0) {
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             print "      scan_load[$size_end:$size_begin] = ${name};\n";
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          } else {
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             print "      scan_load[$addr_end:$addr_begin] = scan_slave[$addr_end:$addr_begin];\n";
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             print "      case (scan_slave[$addr_end:$addr_begin])\n";
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             for (my $a = 0; ($a+1-1)*$data_bits < $size; $a++) {
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                print "         ${addr_bits}'d${a}: scan_load[$data_end:$data_begin] = ${name}[$a*$data_bits +: $data_bits];\n";
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             }
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             print "      endcase\n";
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          }
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       }
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       print "   end\n\n";
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       print "   assign scan_next = scan_load_chain ? scan_load : {scan_data_in, scan_slave[$'$scan_chain_length-1:1]};\n\n";
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       # Print latches
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       print "   //synopsys one_hot \"scan_phi, scan_phi_bar\"\n";
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       print "   always @ (*) begin\n";
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       print "       if (scan_phi)\n";
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       print "          scan_master = scan_next;\n";
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       print "       if (scan_phi_bar)\n";
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       print "          scan_slave  = scan_master;\n";
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       print "   end\n\n";
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       # Print input latches
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       print "   always @ (*) if (scan_load_chip) begin\n";
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       for (my $i = 0; $i < scalar @signal_list; $i++) {
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          if ($signal_list[$i]{writable} == 1) {
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             my $name      = $signal_list[$i]{name};
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             my $size      = $signal_list[$i]{size};
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             my $addr_bits = 0 + $signal_list[$i]{addr_bits};
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             my $data_bits = 0 + $signal_list[$i]{data_bits};
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             my $reset   = 0 + $signal_list[$i]{reset};
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             my $size_begin = $signal_list[$i]{start};
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             my $size_end   = $size_begin + $size - 1;
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             my $addr_begin = $signal_list[$i]{start};
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             my $addr_end   = $addr_begin + $addr_bits - 1;
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             my $data_begin = $addr_end + 1;
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             my $data_end   = $data_begin + $data_bits - 1;
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             if ($signal_list[$i]{addr_bits} == 0) {
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                 if ($signal_list[$i]{name} ne $scan_reset_name) {
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                    print "      $name = scan_slave[$scan_reset_bit] ? ${size}'d${reset} : scan_slave[$size_end:$size_begin];\n";
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                 } else {
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                    print "      $name = scan_slave[$scan_reset_bit];\n";
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                 }
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             } else {
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                if ($scan_reset_exists) {
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                   print "      if (scan_slave[$scan_reset_bit]) ${name} = ${size}'d${reset}; else\n";
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                }
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                print "      case (scan_slave[$addr_end:$addr_begin])\n";
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                for (my $a = 0; ($a+1-1)*$data_bits < $size; $a++) {
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                   print "         ${addr_bits}'d${a}: ${name}[$a*$data_bits +: $data_bits] = scan_slave[$data_end:$data_begin];\n";
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                }
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                print "      endcase\n";
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             }
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          }
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       }
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       print "   end\n\n";
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       # Print data_out
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       print "   assign scan_data_out = scan_slave[0];\n";
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       */
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   end
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   // /////////////////////////////////////////////////////////////////////
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endmodule

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