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[/] [scan_based_serial_communication/] [trunk/] [scan_testbench.perl.v] - Blame information for rev 11

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`define SCAN_DELAY #2
 
module tbench();
 
   // Scan
   reg       scan_phi, scan_phi_bar, scan_data_in, scan_load_chip, scan_load_chain;
   wire      scan_data_out;
 
   //-----------------------------------------
   //  Scan Chain Registers and Tasks
   //-----------------------------------------
 
   // Scan Registers and Initializations
 
   PERL begin
      /*
       DEPERLIFY_INCLUDE(scan_signal_list.pl);
 
       print "`define SCAN_CHAIN_LENGTH $scan_chain_length\n\n";
 
       for (my $i = 0; $i < scalar @signal_list; $i++) {
 
          my $name      = $signal_list[$i]{name};
          my $size      = $signal_list[$i]{size};
          my $addr_bits = $signal_list[$i]{addr_bits};
          my $data_bits = $signal_list[$i]{data_bits};
 
          if ($signal_list[$i]{addr_bits} == 0) {
             print "   reg [$size-1:0] ${name};\n";
             print "   reg [$size-1:0] ${name}_read;\n";
             print "   initial ${name}      = ${size}'d0;\n";
             print "   initial ${name}_read = ${size}'d0;\n";
          } else {
             print "   reg [$addr_bits-1:0] ${name}_addr;\n";
             print "   reg [$data_bits-1:0] ${name}_data;\n";
             print "   reg [$data_bits-1:0] ${name}_data_read;\n";
             print "   initial ${name}_addr      = ${addr_bits}'d0;\n";
             print "   initial ${name}_data      = ${data_bits}'d0;\n";
             print "   initial ${name}_data_read = ${data_bits}'d0;\n";
          }
 
       }
 
       */
   end
 
   // Scan chain tasks
 
   task load_chip;
      begin
         `SCAN_DELAY scan_load_chip = 1;
         `SCAN_DELAY scan_load_chip = 0;
      end
   endtask
 
   task load_chain;
      begin
         `SCAN_DELAY scan_load_chain = 1;
         `SCAN_DELAY scan_phi = 1;
         `SCAN_DELAY scan_phi = 0;
         `SCAN_DELAY scan_phi_bar = 1;
         `SCAN_DELAY scan_phi_bar = 0;
         `SCAN_DELAY scan_load_chain = 0;
      end
   endtask
 
   task rotate_chain;
 
      integer i;
 
      reg [`SCAN_CHAIN_LENGTH-1:0] data_in;
      reg [`SCAN_CHAIN_LENGTH-1:0] data_out;
 
      begin
         PERL begin
            /*
             DEPERLIFY_INCLUDE(scan_signal_list.pl);
 
             for (my $i = 0; $i < scalar @signal_list; $i++) {
 
                if ($signal_list[$i]{addr_bits} == 0) {
                   my $begin = $signal_list[$i]{start};
                   my $end   = $signal_list[$i]{start} + $signal_list[$i]{size} - 1;
 
                   print "         data_in[$end:$begin] = " . $signal_list[$i]{name} . ";\n";
                } else {
                   my $begin = $signal_list[$i]{start};
                   my $end   = $signal_list[$i]{start} + $signal_list[$i]{addr_bits} + $signal_list[$i]{data_bits} - 1;
 
                   print "         data_in[$end:$begin] = {" . $signal_list[$i]{name} . "_data, " . $signal_list[$i]{name} . "_addr};\n";
                }
             }
 
             */
         end
 
         for (i = 0; i < `SCAN_CHAIN_LENGTH; i=i+1) begin
            scan_data_in = data_in[0];
            data_out     = {scan_data_out, data_out[`SCAN_CHAIN_LENGTH-1:1]};
            `SCAN_DELAY scan_phi = 1;
            `SCAN_DELAY scan_phi = 0;
            `SCAN_DELAY scan_phi_bar = 1;
            `SCAN_DELAY scan_phi_bar = 0;
            `SCAN_DELAY data_in = data_in >> 1;
         end
 
         PERL begin
            /*
             DEPERLIFY_INCLUDE(scan_signal_list.pl);
 
             for (my $i = 0; $i < scalar @signal_list; $i++) {
 
                if ($signal_list[$i]{addr_bits} == 0) {
                   my $begin = $signal_list[$i]{start};
                   my $end   = $signal_list[$i]{start} + $signal_list[$i]{size} - 1;
 
                   print "         " . $signal_list[$i]{name} . "_read = data_out[$end:$begin];\n";
                } else {
                   my $begin = $signal_list[$i]{start} + $signal_list[$i]{addr_bits};
                   my $end   = $signal_list[$i]{start} + $signal_list[$i]{addr_bits} + $signal_list[$i]{data_bits} - 1;
 
                   print "         " . $signal_list[$i]{name} . "_data_read = data_out[$end:$begin];\n";
                }
             }
 
             */
         end
      end
 
   endtask
 
   //-----------------------------------------
   //  Scan chain DUT
   //-----------------------------------------
 
   // We're going to use the name chip_iternal_<NAME> for the signals that would
   // normally be inside the chip that we're interacting with. We'll generate them
   // here
 
   PERL begin
      /*
       DEPERLIFY_INCLUDE(scan_signal_list.pl);
 
       for (my $i = 0; $i < scalar @signal_list; $i++) {
           if ($signal_list[$i]{writable} == 1) {
                print "    wire ";
           } else {
                print "    reg  ";
           }
 
            print "[$signal_list[$i]{size}-1:0]  chip_internal_$signal_list[$i]{name};\n";
       }
 
       */
   end
 
   scan scan_dut ( // Inputs & outputs to the chip
             PERL begin
             /*
              DEPERLIFY_INCLUDE(scan_signal_list.pl);
 
              for (my $i = 0; $i < scalar @signal_list; $i++) {
                 print "              .$signal_list[$i]{name}(chip_internal_$signal_list[$i]{name}),\n";
              }
 
              */
             end
 
                   // To the pads
                   .scan_phi        (scan_phi),
                   .scan_phi_bar    (scan_phi_bar),
                   .scan_data_in    (scan_data_in),
                   .scan_data_out   (scan_data_out),
                   .scan_load_chip  (scan_load_chip),
                   .scan_load_chain (scan_load_chain)
                   );
 
 
   //-----------------------------------------
   //  Testbench
   //-----------------------------------------
 
   initial begin
 
      $dumpvars(0, tbench);
 
      $display("Starting scan chain test");
 
      scan_phi  = 0;
      scan_phi_bar = 0;
      scan_data_in = 0;
      scan_load_chip = 0;
      scan_load_chain = 0;
 
      scan_reset = 1'b1;
 
      rotate_chain();
      load_chip();
 
      // Make sure reset worked
      if (chip_internal_write_data_1 !== 1'd0 ||
          chip_internal_write_data_2 !== 2'd3 ||
          chip_internal_write_data_3 !== 3'd0 ||
          chip_internal_write_data_array !== 16'hAA55
          ) begin
         $display("RESET TEST FAILED");
         $finish;
      end else begin
        $display("RESET TEST PASSED");
      end
 
      // Write each variable
      scan_reset = 1'b0;
 
      write_data_1 = 1'd1;
      write_data_2 = 2'd2;
      write_data_3 = 3'd3;
 
      write_data_array_addr = 2'd2;
      write_data_array_data = 4'hB;
 
      rotate_chain();
      load_chip();
 
      // Check that the chip sees the new variables
      if (chip_internal_write_data_1     !== 1'd1 ||
          chip_internal_write_data_2     !== 2'd2 ||
          chip_internal_write_data_3     !== 3'd3 ||
          chip_internal_write_data_array !== 16'hAB55) begin
         $display("TEST 1 FAILED");
         $display("%d %d %d %h",
                  chip_internal_write_data_1,
                  chip_internal_write_data_2,
                  chip_internal_write_data_3,
                  chip_internal_write_data_array);
         $finish;
      end else
        $display("TEST 1 PASSED");
 
      // Set internal values to read out      
      chip_internal_read_data_1 = 1'd0;  // As if the chip had this value internally
      chip_internal_read_data_2 = 2'd3;
      chip_internal_read_data_3 = 3'd5;
 
      chip_internal_read_data_array = 16'hABCD;
 
      // Read all of the values for both writable and non-writable variables
      read_data_array_addr = 2'd1;
 
      rotate_chain();
      load_chain();
      rotate_chain();
 
      // Check to see that we read out all values properly
      if (write_data_1_read         !== 1'd1 ||
          write_data_2_read         !== 2'd2 ||
          write_data_3_read         !== 3'd3 ||
          read_data_1_read          !== 1'd0 ||
          read_data_2_read          !== 2'd3 ||
          read_data_3_read          !== 3'd5 ||
          read_data_array_data_read !== 4'hC) begin
         $display("TEST 2 FAILED");
         $display("%d %d %d %d %d %d %h",
                  write_data_1_read,
                  write_data_2_read,
                  write_data_3_read,
                  read_data_1_read,
                  read_data_2_read,
                  read_data_3_read,
                  read_data_array_data_read);
         $finish;
      end else
        $display("TEST 2 PASSED");
 
      $finish;
   end
 
   //////////
 
endmodule // tbench
 
 

Line No.	Rev	Author	Line
1	3	Quanticles
2	9	Quanticles	`define SCAN_DELAY #2
3	3	Quanticles
4			`module tbench();`
5
6			`// Scan`
7			`reg scan_phi, scan_phi_bar, scan_data_in, scan_load_chip, scan_load_chain;`
8			`wire scan_data_out;`
9
10			`//-----------------------------------------`
11			`// Scan Chain Registers and Tasks`
12			`//-----------------------------------------`
13
14			`// Scan Registers and Initializations`
15
16			`PERL begin`
17			`/*`
18			`DEPERLIFY_INCLUDE(scan_signal_list.pl);`
19
20			print "`define SCAN_CHAIN_LENGTH $scan_chain_length\n\n";
21
22			`for (my $i = 0; $i < scalar @signal_list; $i++) {`
23
24	4	Quanticles	`my $name = $signal_list[$i]{name};`
25			`my $size = $signal_list[$i]{size};`
26			`my $addr_bits = $signal_list[$i]{addr_bits};`
27			`my $data_bits = $signal_list[$i]{data_bits};`
28
29			`if ($signal_list[$i]{addr_bits} == 0) {`
30			`print " reg [$size-1:0] ${name};\n";`
31			`print " reg [$size-1:0] ${name}_read;\n";`
32			`print " initial ${name} = ${size}'d0;\n";`
33			`print " initial ${name}_read = ${size}'d0;\n";`
34			`} else {`
35			`print " reg [$addr_bits-1:0] ${name}_addr;\n";`
36			`print " reg [$data_bits-1:0] ${name}_data;\n";`
37			`print " reg [$data_bits-1:0] ${name}_data_read;\n";`
38			`print " initial ${name}_addr = ${addr_bits}'d0;\n";`
39			`print " initial ${name}_data = ${data_bits}'d0;\n";`
40			`print " initial ${name}_data_read = ${data_bits}'d0;\n";`
41			`}`
42
43	3	Quanticles	`}`
44
45			`*/`
46			`end`
47
48			`// Scan chain tasks`
49
50			`task load_chip;`
51			`begin`
52			`SCAN_DELAY scan_load_chip = 1;
53			`SCAN_DELAY scan_load_chip = 0;
54			`end`
55			`endtask`
56
57			`task load_chain;`
58			`begin`
59			`SCAN_DELAY scan_load_chain = 1;
60			`SCAN_DELAY scan_phi = 1;
61			`SCAN_DELAY scan_phi = 0;
62			`SCAN_DELAY scan_phi_bar = 1;
63			`SCAN_DELAY scan_phi_bar = 0;
64			`SCAN_DELAY scan_load_chain = 0;
65			`end`
66			`endtask`
67
68			`task rotate_chain;`
69
70			`integer i;`
71
72			reg [`SCAN_CHAIN_LENGTH-1:0] data_in;
73			reg [`SCAN_CHAIN_LENGTH-1:0] data_out;
74
75			`begin`
76			`PERL begin`
77			`/*`
78			`DEPERLIFY_INCLUDE(scan_signal_list.pl);`
79
80			`for (my $i = 0; $i < scalar @signal_list; $i++) {`
81
82	4	Quanticles	`if ($signal_list[$i]{addr_bits} == 0) {`
83			`my $begin = $signal_list[$i]{start};`
84			`my $end = $signal_list[$i]{start} + $signal_list[$i]{size} - 1;`
85
86			`print " data_in[$end:$begin] = " . $signal_list[$i]{name} . ";\n";`
87			`} else {`
88			`my $begin = $signal_list[$i]{start};`
89			`my $end = $signal_list[$i]{start} + $signal_list[$i]{addr_bits} + $signal_list[$i]{data_bits} - 1;`
90
91			`print " data_in[$end:$begin] = {" . $signal_list[$i]{name} . "_data, " . $signal_list[$i]{name} . "_addr};\n";`
92			`}`
93	3	Quanticles	`}`
94
95			`*/`
96			`end`
97
98			for (i = 0; i < `SCAN_CHAIN_LENGTH; i=i+1) begin
99			`scan_data_in = data_in[0];`
100			data_out = {scan_data_out, data_out[`SCAN_CHAIN_LENGTH-1:1]};
101			`SCAN_DELAY scan_phi = 1;
102			`SCAN_DELAY scan_phi = 0;
103			`SCAN_DELAY scan_phi_bar = 1;
104			`SCAN_DELAY scan_phi_bar = 0;
105			`SCAN_DELAY data_in = data_in >> 1;
106			`end`
107
108			`PERL begin`
109			`/*`
110			`DEPERLIFY_INCLUDE(scan_signal_list.pl);`
111
112			`for (my $i = 0; $i < scalar @signal_list; $i++) {`
113
114	4	Quanticles	`if ($signal_list[$i]{addr_bits} == 0) {`
115			`my $begin = $signal_list[$i]{start};`
116			`my $end = $signal_list[$i]{start} + $signal_list[$i]{size} - 1;`
117
118			`print " " . $signal_list[$i]{name} . "_read = data_out[$end:$begin];\n";`
119			`} else {`
120			`my $begin = $signal_list[$i]{start} + $signal_list[$i]{addr_bits};`
121			`my $end = $signal_list[$i]{start} + $signal_list[$i]{addr_bits} + $signal_list[$i]{data_bits} - 1;`
122
123			`print " " . $signal_list[$i]{name} . "_data_read = data_out[$end:$begin];\n";`
124			`}`
125	3	Quanticles	`}`
126
127			`*/`
128			`end`
129			`end`
130
131			`endtask`
132
133			`//-----------------------------------------`
134			`// Scan chain DUT`
135			`//-----------------------------------------`
136
137			`// We're going to use the name chip_iternal_<NAME> for the signals that would`
138			`// normally be inside the chip that we're interacting with. We'll generate them`
139			`// here`
140
141			`PERL begin`
142			`/*`
143			`DEPERLIFY_INCLUDE(scan_signal_list.pl);`
144
145			`for (my $i = 0; $i < scalar @signal_list; $i++) {`
146			`if ($signal_list[$i]{writable} == 1) {`
147			`print " wire ";`
148			`} else {`
149			`print " reg ";`
150			`}`
151
152			`print "[$signal_list[$i]{size}-1:0] chip_internal_$signal_list[$i]{name};\n";`
153			`}`
154
155			`*/`
156			`end`
157
158			`scan scan_dut ( // Inputs & outputs to the chip`
159			`PERL begin`
160			`/*`
161			`DEPERLIFY_INCLUDE(scan_signal_list.pl);`
162
163			`for (my $i = 0; $i < scalar @signal_list; $i++) {`
164			`print " .$signal_list[$i]{name}(chip_internal_$signal_list[$i]{name}),\n";`
165			`}`
166
167			`*/`
168			`end`
169
170			`// To the pads`
171			`.scan_phi (scan_phi),`
172			`.scan_phi_bar (scan_phi_bar),`
173			`.scan_data_in (scan_data_in),`
174			`.scan_data_out (scan_data_out),`
175			`.scan_load_chip (scan_load_chip),`
176			`.scan_load_chain (scan_load_chain)`
177			`);`
178
179
180			`//-----------------------------------------`
181			`// Testbench`
182			`//-----------------------------------------`
183
184			`initial begin`
185
186	4	Quanticles	`$dumpvars(0, tbench);`
187
188	3	Quanticles	`$display("Starting scan chain test");`
189
190			`scan_phi = 0;`
191			`scan_phi_bar = 0;`
192			`scan_data_in = 0;`
193			`scan_load_chip = 0;`
194			`scan_load_chain = 0;`
195	4	Quanticles
196			`scan_reset = 1'b1;`
197	3	Quanticles
198			`rotate_chain();`
199			`load_chip();`
200
201	4	Quanticles	`// Make sure reset worked`
202	11	Quanticles	`if (chip_internal_write_data_1 !== 1'd0 \|\|`
203			`chip_internal_write_data_2 !== 2'd3 \|\|`
204			`chip_internal_write_data_3 !== 3'd0 \|\|`
205			`chip_internal_write_data_array !== 16'hAA55`
206			`) begin`
207			`$display("RESET TEST FAILED");`
208			`$finish;`
209			`end else begin`
210	4	Quanticles	`$display("RESET TEST PASSED");`
211	11	Quanticles	`end`
212
213	4	Quanticles	`// Write each variable`
214			`scan_reset = 1'b0;`
215
216	3	Quanticles	`write_data_1 = 1'd1;`
217			`write_data_2 = 2'd2;`
218			`write_data_3 = 3'd3;`
219
220	4	Quanticles	`write_data_array_addr = 2'd2;`
221	11	Quanticles	`write_data_array_data = 4'hB;`
222	4	Quanticles
223	3	Quanticles	`rotate_chain();`
224			`load_chip();`
225
226			`// Check that the chip sees the new variables`
227	4	Quanticles	`if (chip_internal_write_data_1 !== 1'd1 \|\|`
228			`chip_internal_write_data_2 !== 2'd2 \|\|`
229			`chip_internal_write_data_3 !== 3'd3 \|\|`
230	11	Quanticles	`chip_internal_write_data_array !== 16'hAB55) begin`
231	4	Quanticles	`$display("TEST 1 FAILED");`
232			`$display("%d %d %d %h",`
233			`chip_internal_write_data_1,`
234			`chip_internal_write_data_2,`
235			`chip_internal_write_data_3,`
236			`chip_internal_write_data_array);`
237	11	Quanticles	`$finish;`
238	4	Quanticles	`end else`
239	3	Quanticles	`$display("TEST 1 PASSED");`
240
241			`// Set internal values to read out`
242			`chip_internal_read_data_1 = 1'd0; // As if the chip had this value internally`
243			`chip_internal_read_data_2 = 2'd3;`
244			`chip_internal_read_data_3 = 3'd5;`
245
246	4	Quanticles	`chip_internal_read_data_array = 16'hABCD;`
247
248	3	Quanticles	`// Read all of the values for both writable and non-writable variables`
249	4	Quanticles	`read_data_array_addr = 2'd1;`
250
251			`rotate_chain();`
252	3	Quanticles	`load_chain();`
253			`rotate_chain();`
254
255			`// Check to see that we read out all values properly`
256	4	Quanticles	`if (write_data_1_read !== 1'd1 \|\|`
257			`write_data_2_read !== 2'd2 \|\|`
258			`write_data_3_read !== 3'd3 \|\|`
259			`read_data_1_read !== 1'd0 \|\|`
260			`read_data_2_read !== 2'd3 \|\|`
261			`read_data_3_read !== 3'd5 \|\|`
262			`read_data_array_data_read !== 4'hC) begin`
263	3	Quanticles	`$display("TEST 2 FAILED");`
264	4	Quanticles	`$display("%d %d %d %d %d %d %h",`
265	3	Quanticles	`write_data_1_read,`
266			`write_data_2_read,`
267			`write_data_3_read,`
268			`read_data_1_read,`
269			`read_data_2_read,`
270	4	Quanticles	`read_data_3_read,`
271			`read_data_array_data_read);`
272	11	Quanticles	`$finish;`
273	3	Quanticles	`end else`
274			`$display("TEST 2 PASSED");`
275
276			`$finish;`
277			`end`
278
279			`//////////`
280
281			`endmodule // tbench`
282
283	2	Quanticles

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Subversion Repositories scan_based_serial_communication

[/] [scan_based_serial_communication/] [trunk/] [scan_testbench.perl.v] - Blame information for rev 11