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[/] [scan_based_serial_communication/] [trunk/] [scan_testbench.perl.v] - Blame information for rev 2

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1 2 Quanticles
 
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`define SCAN_DELAY #1
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module tbench();
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   // Scan
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   reg       scan_phi, scan_phi_bar, scan_data_in, scan_load_chip, scan_load_chain;
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   wire      scan_data_out;
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   //-----------------------------------------
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   //  Scan Chain Registers and Tasks
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   //-----------------------------------------
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   // Scan Registers and Initializations
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   PERL begin
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      /*
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       DEPERLIFY_INCLUDE(scan_signal_list.pl);
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       print "`define SCAN_CHAIN_LENGTH $scan_chain_length\n\n";
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       for (my $i = 0; $i < scalar @signal_list; $i++) {
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          my $begin = 0;
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          my $end   = $signal_list[$i]{size} - 1;
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         print "   reg [$end:$begin] " . $signal_list[$i]{name} . ";\n";
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         print "   reg [$end:$begin] " . $signal_list[$i]{name} . "_read;\n";
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         print "   initial " . $signal_list[$i]{name} . " = " .$signal_list[$i]{size} . "'d0;\n";
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         print "   initial " . $signal_list[$i]{name} . "_read = " .$signal_list[$i]{size} . "'d0;\n";
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       }
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       */
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   end
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   // Scan chain tasks
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   task load_chip;
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      begin
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         `SCAN_DELAY scan_load_chip = 1;
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         `SCAN_DELAY scan_load_chip = 0;
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      end
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   endtask
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   task load_chain;
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      begin
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         `SCAN_DELAY scan_load_chain = 1;
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         `SCAN_DELAY scan_phi = 1;
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         `SCAN_DELAY scan_phi = 0;
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         `SCAN_DELAY scan_phi_bar = 1;
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         `SCAN_DELAY scan_phi_bar = 0;
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         `SCAN_DELAY scan_load_chain = 0;
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      end
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   endtask
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   task rotate_chain;
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      integer i;
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      reg [`SCAN_CHAIN_LENGTH-1:0] data_in;
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      reg [`SCAN_CHAIN_LENGTH-1:0] data_out;
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      begin
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         PERL begin
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            /*
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             DEPERLIFY_INCLUDE(scan_signal_list.pl);
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             for (my $i = 0; $i < scalar @signal_list; $i++) {
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                my $begin = $signal_list[$i]{start};
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                my $end   = $signal_list[$i]{start} + $signal_list[$i]{size} - 1;
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                print "         data_in[$end:$begin] = " . $signal_list[$i]{name} . ";\n";
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             }
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             */
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         end
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         for (i = 0; i < `SCAN_CHAIN_LENGTH; i=i+1) begin
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            scan_data_in = data_in[0];
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            data_out     = {scan_data_out, data_out[`SCAN_CHAIN_LENGTH-1:1]};
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            `SCAN_DELAY scan_phi = 1;
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            `SCAN_DELAY scan_phi = 0;
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            `SCAN_DELAY scan_phi_bar = 1;
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            `SCAN_DELAY scan_phi_bar = 0;
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            `SCAN_DELAY data_in = data_in >> 1;
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         end
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         PERL begin
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            /*
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             DEPERLIFY_INCLUDE(scan_signal_list.pl);
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             for (my $i = 0; $i < scalar @signal_list; $i++) {
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                my $begin = $signal_list[$i]{start};
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                my $end   = $signal_list[$i]{start} + $signal_list[$i]{size} - 1;
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                print "         " . $signal_list[$i]{name} . "_read = data_out[$end:$begin];\n";
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             }
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             */
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         end
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      end
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   endtask
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   //-----------------------------------------
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   //  Scan chain DUT
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   //-----------------------------------------
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   // We're going to use the name chip_iternal_<NAME> for the signals that would
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   // normally be inside the chip that we're interacting with. We'll generate them
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   // here
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   PERL begin
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      /*
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       DEPERLIFY_INCLUDE(scan_signal_list.pl);
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       for (my $i = 0; $i < scalar @signal_list; $i++) {
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           if ($signal_list[$i]{writable} == 1) {
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                print "    wire ";
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           } else {
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                print "    reg  ";
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           }
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            print "[$signal_list[$i]{size}-1:0]  chip_internal_$signal_list[$i]{name};\n";
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       }
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       */
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   end
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   scan scan_dut ( // Inputs & outputs to the chip
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             PERL begin
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             /*
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              DEPERLIFY_INCLUDE(scan_signal_list.pl);
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              for (my $i = 0; $i < scalar @signal_list; $i++) {
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                 print "              .$signal_list[$i]{name}(chip_internal_$signal_list[$i]{name}),\n";
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              }
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              */
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             end
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                   // To the pads
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                   .scan_phi        (scan_phi),
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                   .scan_phi_bar    (scan_phi_bar),
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                   .scan_data_in    (scan_data_in),
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                   .scan_data_out   (scan_data_out),
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                   .scan_load_chip  (scan_load_chip),
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                   .scan_load_chain (scan_load_chain)
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                   );
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   //-----------------------------------------
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   //  Testbench
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   //-----------------------------------------
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   initial begin
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      $display("Starting scan chain test");
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      scan_phi  = 0;
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      scan_phi_bar = 0;
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      scan_data_in = 0;
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      scan_load_chip = 0;
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      scan_load_chain = 0;
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      rotate_chain();
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      load_chip();
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          // Write each variable
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      write_data_1 = 1'd1;
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      write_data_2 = 2'd2;
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      write_data_3 = 3'd3;
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      rotate_chain();
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      load_chip();
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      // Check that the chip sees the new variables
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      if (chip_internal_write_data_1 != 1'd1 ||
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          chip_internal_write_data_2 != 2'd2 ||
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          chip_internal_write_data_3 != 3'd3 )
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        $display("TEST 1 FAILED");
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      else
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        $display("TEST 1 PASSED");
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      // Set internal values to read out      
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      chip_internal_read_data_1 = 1'd0;  // As if the chip had this value internally
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      chip_internal_read_data_2 = 2'd3;
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      chip_internal_read_data_3 = 3'd5;
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      // Read all of the values for both writable and non-writable variables
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      load_chain();
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      rotate_chain();
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      // Check to see that we read out all values properly
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      if (write_data_1_read != 1'd1 ||
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          write_data_2_read != 2'd2 ||
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          write_data_3_read != 3'd3 ||
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          read_data_1_read  != 1'd0 ||
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          read_data_2_read  != 2'd3 ||
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          read_data_3_read  != 3'd5 ) begin
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         $display("TEST 2 FAILED");
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         $display("%d %d %d %d %d %d",
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                  write_data_1_read,
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                  write_data_2_read,
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                  write_data_3_read,
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                  read_data_1_read,
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                  read_data_2_read,
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                  read_data_3_read);
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      end else
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        $display("TEST 2 PASSED");
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      $finish;
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   end
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   //////////
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endmodule // tbench
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