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# Intel(r) Wireless MMX(tm) technology testcase for TINSR
# mach: xscale
# as: -mcpu=xscale+iwmmxt
 
        .include "testutils.inc"
 
        start
 
        .global tinsr
tinsr:
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.
 
        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0
 
        # Test Byte Wide Insertion
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x111111ff
 
        tmcrr      wr0, r0, r1
 
        tinsrb     wr0, r2, #3
 
        tmrrc      r0, r1, wr0
 
        test_h_gr  r0, 0xff345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x111111ff
 
        # Test Half Word Wide Insertion
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x111111ff
 
        tmcrr      wr0, r0, r1
 
        tinsrh     wr0, r2, #2
 
        tmrrc      r0, r1, wr0
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abc11ff
        test_h_gr  r2, 0x111111ff
 
        # Test Word Wide Insertion
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x111111ff
 
        tmcrr      wr0, r0, r1
 
        tinsrw     wr0, r2, #1
 
        tmrrc      r0, r1, wr0
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x111111ff
        test_h_gr  r2, 0x111111ff
 
        pass

Line No.	Rev	Author	Line
1	26	jlechner	`# Intel(r) Wireless MMX(tm) technology testcase for TINSR`
2			`# mach: xscale`
3			`# as: -mcpu=xscale+iwmmxt`
4
5			`.include "testutils.inc"`
6
7			`start`
8
9			`.global tinsr`
10			`tinsr:`
11			`# Enable access to CoProcessors 0 & 1 before`
12			`# we attempt these instructions.`
13
14			`mvi_h_gr r1, 3`
15			`mcr p15, 0, r1, cr15, cr1, 0`
16
17			`# Test Byte Wide Insertion`
18
19			`mvi_h_gr r0, 0x12345678`
20			`mvi_h_gr r1, 0x9abcdef0`
21			`mvi_h_gr r2, 0x111111ff`
22
23			`tmcrr wr0, r0, r1`
24
25			`tinsrb wr0, r2, #3`
26
27			`tmrrc r0, r1, wr0`
28
29			`test_h_gr r0, 0xff345678`
30			`test_h_gr r1, 0x9abcdef0`
31			`test_h_gr r2, 0x111111ff`
32
33			`# Test Half Word Wide Insertion`
34
35			`mvi_h_gr r0, 0x12345678`
36			`mvi_h_gr r1, 0x9abcdef0`
37			`mvi_h_gr r2, 0x111111ff`
38
39			`tmcrr wr0, r0, r1`
40
41			`tinsrh wr0, r2, #2`
42
43			`tmrrc r0, r1, wr0`
44
45			`test_h_gr r0, 0x12345678`
46			`test_h_gr r1, 0x9abc11ff`
47			`test_h_gr r2, 0x111111ff`
48
49			`# Test Word Wide Insertion`
50
51			`mvi_h_gr r0, 0x12345678`
52			`mvi_h_gr r1, 0x9abcdef0`
53			`mvi_h_gr r2, 0x111111ff`
54
55			`tmcrr wr0, r0, r1`
56
57			`tinsrw wr0, r2, #1`
58
59			`tmrrc r0, r1, wr0`
60
61			`test_h_gr r0, 0x12345678`
62			`test_h_gr r1, 0x111111ff`
63			`test_h_gr r2, 0x111111ff`
64
65			`pass`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [tinsr.cgs] - Blame information for rev 26