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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [hw/] [rv-n-cris/] [trivial1.ms] - Blame information for rev 26

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#mach: crisv32
#sim(crisv32): --hw-info
#output: /\n
#output: /rv\n
#output: /rv/reg 0xd0000000 0x40\n
#output: /rv/remote-reg 0xa8800\n
#output: /rv/intnum 0x4 0x2\n
#output: /rv/mem 0x20000 0x400\n
#output: /rv/remote-mem 0xe000\n
#output: /rv/mbox 0xc000f000\n
#output: /rv > int int /cris\n
#output: /cris\n
#output: /cris/vec-for-int 0x4 0x33 0x8 0x34 0xaa 0xea\n
 
# Test expected --hw-info output and startup paths of components.
 
 .include "quit.s"

Line No.	Rev	Author	Line
1	26	jlechner	`#mach: crisv32`
2			`#sim(crisv32): --hw-info`
3			`#output: /\n`
4			`#output: /rv\n`
5			`#output: /rv/reg 0xd0000000 0x40\n`
6			`#output: /rv/remote-reg 0xa8800\n`
7			`#output: /rv/intnum 0x4 0x2\n`
8			`#output: /rv/mem 0x20000 0x400\n`
9			`#output: /rv/remote-mem 0xe000\n`
10			`#output: /rv/mbox 0xc000f000\n`
11			`#output: /rv > int int /cris\n`
12			`#output: /cris\n`
13			`#output: /cris/vec-for-int 0x4 0x33 0x8 0x34 0xaa 0xea\n`
14
15			`# Test expected --hw-info output and startup paths of components.`
16
17			`.include "quit.s"`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [hw/] [rv-n-cris/] [trivial1.ms] - Blame information for rev 26