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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fr550/] [mqaddhus.cgs] - Blame information for rev 26

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Line No. Rev Author Line
1 26 jlechner 
# frv testcase for mqaddhus $FRi,$FRj,$FRj
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# mach: all
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        .include "../testutils.inc"
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        start
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        .global mqaddhus
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mqaddhus:
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        set_fr_iimmed   0x0000,0x0000,fr10
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        set_fr_iimmed   0xdead,0x0000,fr11
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        set_fr_iimmed   0x0000,0x0000,fr12
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        set_fr_iimmed   0x0000,0xbeef,fr13
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        mqaddhus        fr10,fr12,fr14
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        test_fr_limmed  0x0000,0x0000,fr14
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        test_fr_limmed  0xdead,0xbeef,fr15
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
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        set_fr_iimmed   0x0000,0xdead,fr10
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        set_fr_iimmed   0x1234,0x5678,fr11
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        set_fr_iimmed   0xbeef,0x0000,fr12
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        set_fr_iimmed   0x1111,0x1111,fr13
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        mqaddhus        fr10,fr12,fr14
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        test_fr_limmed  0xbeef,0xdead,fr14
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        test_fr_limmed  0x2345,0x6789,fr15
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
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        set_fr_iimmed   0x7ffe,0x7ffe,fr10
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        set_fr_iimmed   0xfffe,0xfffe,fr11
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        set_fr_iimmed   0x0002,0x0001,fr12
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        set_fr_iimmed   0x0001,0x0002,fr13
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        mqaddhus        fr10,fr12,fr14
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        test_fr_limmed  0x8000,0x7fff,fr14
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        test_fr_limmed  0xffff,0xffff,fr15
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        test_spr_bits   0x3c,2,1,msr0           ; msr0.sie is set
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        test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
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        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
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        set_spr_immed   0,msr0
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        set_fr_iimmed   0x0002,0x0001,fr10
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        set_fr_iimmed   0x0001,0x0001,fr11
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        set_fr_iimmed   0xfffe,0xfffe,fr12
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        set_fr_iimmed   0x8000,0x8000,fr13
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        mqaddhus.p      fr10,fr10,fr14
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        mqaddhus        fr12,fr12,fr16
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        test_fr_limmed  0x0004,0x0002,fr14
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        test_fr_limmed  0x0002,0x0002,fr15
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        test_fr_limmed  0xffff,0xffff,fr16
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        test_fr_limmed  0xffff,0xffff,fr17
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        test_spr_bits   0x3c,2,0xf,msr0         ; msr0.sie is set
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        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
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        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
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        pass

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