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# frv testcase for tic $ICCi_2,$GRi,$s12
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global tic
tic:
        and_spr_immed   -4081,tbr               ; clear tbr.tt
        set_gr_spr      tbr,gr7
        inc_gr_immed    2112,gr7                ; address of exception handler
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
 
        set_spr_immed   128,lcr
        set_gr_immed    0,gr7
 
        set_spr_addr    bad,lr
        set_icc         0x0 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok1,lr
        set_icc         0x1 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok1:
        set_spr_addr    bad,lr
        set_icc         0x2 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok3,lr
        set_icc         0x3 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok3:
        set_spr_addr    bad,lr
        set_icc         0x4 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok5,lr
        set_icc         0x5 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok5:
        set_spr_addr    bad,lr
        set_icc         0x6 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok7,lr
        set_icc         0x7 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok7:
        set_spr_addr    bad,lr
        set_icc         0x8 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok9,lr
        set_icc         0x9 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok9:
        set_spr_addr    bad,lr
        set_icc         0xa 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    okb,lr
        set_icc         0xb 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
okb:
        set_spr_addr    bad,lr
        set_icc         0xc 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    okd,lr
        set_icc         0xd 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
okd:
        set_spr_addr    bad,lr
        set_icc         0xe 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    okf,lr
        set_icc         0xf 0
        tic             icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
okf:
        pass
bad:
        fail

Line No.	Rev	Author	Line
1	26	jlechner	`# frv testcase for tic $ICCi_2,$GRi,$s12`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global tic`
9			`tic:`
10			`and_spr_immed -4081,tbr ; clear tbr.tt`
11			`set_gr_spr tbr,gr7`
12			`inc_gr_immed 2112,gr7 ; address of exception handler`
13			`set_bctrlr_0_0 gr7 ; bctrlr 0,0`
14
15			`set_spr_immed 128,lcr`
16			`set_gr_immed 0,gr7`
17
18			`set_spr_addr bad,lr`
19			`set_icc 0x0 0`
20			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
21
22			`set_psr_et 1`
23			`set_spr_addr ok1,lr`
24			`set_icc 0x1 0`
25			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
26			`fail`
27			`ok1:`
28			`set_spr_addr bad,lr`
29			`set_icc 0x2 0`
30			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
31
32			`set_psr_et 1`
33			`set_spr_addr ok3,lr`
34			`set_icc 0x3 0`
35			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
36			`fail`
37			`ok3:`
38			`set_spr_addr bad,lr`
39			`set_icc 0x4 0`
40			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
41
42			`set_psr_et 1`
43			`set_spr_addr ok5,lr`
44			`set_icc 0x5 0`
45			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
46			`fail`
47			`ok5:`
48			`set_spr_addr bad,lr`
49			`set_icc 0x6 0`
50			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
51
52			`set_psr_et 1`
53			`set_spr_addr ok7,lr`
54			`set_icc 0x7 0`
55			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
56			`fail`
57			`ok7:`
58			`set_spr_addr bad,lr`
59			`set_icc 0x8 0`
60			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
61
62			`set_psr_et 1`
63			`set_spr_addr ok9,lr`
64			`set_icc 0x9 0`
65			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
66			`fail`
67			`ok9:`
68			`set_spr_addr bad,lr`
69			`set_icc 0xa 0`
70			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
71
72			`set_psr_et 1`
73			`set_spr_addr okb,lr`
74			`set_icc 0xb 0`
75			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
76			`fail`
77			`okb:`
78			`set_spr_addr bad,lr`
79			`set_icc 0xc 0`
80			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
81
82			`set_psr_et 1`
83			`set_spr_addr okd,lr`
84			`set_icc 0xd 0`
85			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
86			`fail`
87			`okd:`
88			`set_spr_addr bad,lr`
89			`set_icc 0xe 0`
90			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
91
92			`set_psr_et 1`
93			`set_spr_addr okf,lr`
94			`set_icc 0xf 0`
95			`tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
96			`fail`
97			`okf:`
98			`pass`
99			`bad:`
100			`fail`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [tic.cgs] - Blame information for rev 26