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# sh testcase for paddc
# mach:  shdsp
# as(shdsp):    -defsym sim_cpu=1 -dsp
 
        .include "testutils.inc"
 
        start
        set_grs_a5a5
        lds     r0, a0
        pcopy   a0, a1
        lds     r0, x0
        lds     r0, x1
        lds     r0, y0
        lds     r0, y1
        pcopy   x0, m0
        pcopy   y1, m1
 
        # 2 + 2 = 4
        set_dcfalse
        mov     #2, r0
        lds     r0, x0
        lds     r0, y0
        paddc   x0, y0, a0
        assert_sreg     4, a0
 
        # 2 + 2 + carry = 5
        set_dctrue
        paddc   x0, y0, a1
        assert_sreg2    5, a1
 
        set_greg        0xa5a5a5a5, r0
        test_grs_a5a5
        assert_sreg     0xa5a5a5a5, x1
        assert_sreg     0xa5a5a5a5, y1
        assert_sreg2    0xa5a5a5a5, m0
        assert_sreg2    0xa5a5a5a5, m1
 
        pass
        exit 0

Line No.	Rev	Author	Line
1	26	jlechner	`# sh testcase for paddc`
2			`# mach: shdsp`
3			`# as(shdsp): -defsym sim_cpu=1 -dsp`
4
5			`.include "testutils.inc"`
6
7			`start`
8			`set_grs_a5a5`
9			`lds r0, a0`
10			`pcopy a0, a1`
11			`lds r0, x0`
12			`lds r0, x1`
13			`lds r0, y0`
14			`lds r0, y1`
15			`pcopy x0, m0`
16			`pcopy y1, m1`
17
18			`# 2 + 2 = 4`
19			`set_dcfalse`
20			`mov #2, r0`
21			`lds r0, x0`
22			`lds r0, y0`
23			`paddc x0, y0, a0`
24			`assert_sreg 4, a0`
25
26			`# 2 + 2 + carry = 5`
27			`set_dctrue`
28			`paddc x0, y0, a1`
29			`assert_sreg2 5, a1`
30
31			`set_greg 0xa5a5a5a5, r0`
32			`test_grs_a5a5`
33			`assert_sreg 0xa5a5a5a5, x1`
34			`assert_sreg 0xa5a5a5a5, y1`
35			`assert_sreg2 0xa5a5a5a5, m0`
36			`assert_sreg2 0xa5a5a5a5, m1`
37
38			`pass`
39			`exit 0`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [paddc.s] - Blame information for rev 26