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[/] [scct/] [trunk/] [test/] [test_scct.v] - Blame information for rev 2

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// $Id: test_scct.v 2 2015-06-15 13:52:02Z fkluge $
// Test bed for scct
 
`include "scct_constants.v"
 
module test_scct;
 
   // Make a regular pulsing clock.
   reg clk = 1;
   always #1 clk = !clk;
 
   // Make a reset that pulses once.
   reg rst = 0;
 
   reg [4:0] address = 0;
   reg       read = 0;
   wire [31:0] readdata = 0;
   reg [31:0]  writedata = 0;
   reg         write = 0;
   wire        irq = 0;
 
   // Conduit interface
   wire [`SCCT_N_CHANNELS-1:0] pins_i;
   wire [`SCCT_N_CHANNELS-1:0] pins_o;
 
   reg inp = 0;
   wire iSig;
   assign iSig = inp ? 1 : 0;
   wire oSig;
 
   //assign pins[0] = (msi == `SCCT_CH_MS_IC) ? iSig : oSig;
   assign pins_i[0] = iSig;
 
 
   scct scct(clk, rst, address, read, readdata, writedata, write, irq, pins_i, pins_o);
 
   initial
     begin
        $dumpfile("test.lxt2");
        $dumpvars;
     end
 
 
   initial
     begin
        # 0 rst = 1;
 
 
        # 1 rst = 0;
 
        # 1
          address = `SCCT_PSC;
        writedata = 32'b1;
        write = 1;
        # 3 write = 0;
 
 
        // set IC @ ch0, OC @ ch1
        # 1
          address = `SCCT_CH_MS;
        writedata = { 24'b0, 6'b0, `SCCT_CH_MS_OC, `SCCT_CH_MS_IC};
        write = 1;
        # 2 write = 0;
 
        // force ch1 outpin to low
        # 2
          address = `SCCT_CH_ACT;
        writedata = { 24'b0, 4'b0, `SCCT_OC_LOW, 2'b0 };
        write = 1;
        # 2 write = 0;
        # 2
          address = `SCCT_CH_OCF;
        writedata = { 24'b0, 6'b0, 1'b1, 1'b0 };
        write = 1;
        # 2 write = 0;
 
 
        // detect ANYEDGE @ ch0, TOGGLE @ ch1
        # 2
          address = `SCCT_CH_ACT;
        writedata = {24'b0, 4'b0, `SCCT_OC_TOGGLE, `SCCT_IC_ANYEDGE};
        write = 1;
        # 2 write = 0;
 
        # 2
          address = `SCCT_CH_CCR1;
        writedata = 32'h16;
        write = 1;
        # 2 write = 0;
 
        // enable IRQ @ ch0 + ch1
        # 2
          address = `SCCT_CH_IE;
        writedata = 32'b11;
        write = 1;
        # 2 write = 0;
 
        # 2 inp = 1;
 
        # 6 address = `SCCT_CH_IS;
        writedata = 32'b1;
        write = 1;
        # 2 write = 0;
 
        # 4 inp = 0;
 
        # 6 address = `SCCT_CH_IS;
        writedata = 32'b1;
        write = 1;
        # 2 write = 0;
 
        # 50 write = 0;
 
 
        // reset OC
        # 8 address = `SCCT_CH_IS;
        writedata = 32'b10;
        write = 1;
        # 2 write = 0;
 
 
        # 10 $stop;
     end
 
endmodule // test_scct

Line No.	Rev	Author	Line
1	2	fkluge	`// $Id: test_scct.v 2 2015-06-15 13:52:02Z fkluge $`
2			`// Test bed for scct`
3
4			`include "scct_constants.v"
5
6			`module test_scct;`
7
8			`// Make a regular pulsing clock.`
9			`reg clk = 1;`
10			`always #1 clk = !clk;`
11
12			`// Make a reset that pulses once.`
13			`reg rst = 0;`
14
15			`reg [4:0] address = 0;`
16			`reg read = 0;`
17			`wire [31:0] readdata = 0;`
18			`reg [31:0] writedata = 0;`
19			`reg write = 0;`
20			`wire irq = 0;`
21
22			`// Conduit interface`
23			wire [`SCCT_N_CHANNELS-1:0] pins_i;
24			wire [`SCCT_N_CHANNELS-1:0] pins_o;
25
26			`reg inp = 0;`
27			`wire iSig;`
28			`assign iSig = inp ? 1 : 0;`
29			`wire oSig;`
30
31			//assign pins[0] = (msi == `SCCT_CH_MS_IC) ? iSig : oSig;
32			`assign pins_i[0] = iSig;`
33
34
35			`scct scct(clk, rst, address, read, readdata, writedata, write, irq, pins_i, pins_o);`
36
37			`initial`
38			`begin`
39			`$dumpfile("test.lxt2");`
40			`$dumpvars;`
41			`end`
42
43
44			`initial`
45			`begin`
46			`# 0 rst = 1;`
47
48
49			`# 1 rst = 0;`
50
51			`# 1`
52			address = `SCCT_PSC;
53			`writedata = 32'b1;`
54			`write = 1;`
55			`# 3 write = 0;`
56
57
58			`// set IC @ ch0, OC @ ch1`
59			`# 1`
60			address = `SCCT_CH_MS;
61			writedata = { 24'b0, 6'b0, `SCCT_CH_MS_OC, `SCCT_CH_MS_IC};
62			`write = 1;`
63			`# 2 write = 0;`
64
65			`// force ch1 outpin to low`
66			`# 2`
67			address = `SCCT_CH_ACT;
68			writedata = { 24'b0, 4'b0, `SCCT_OC_LOW, 2'b0 };
69			`write = 1;`
70			`# 2 write = 0;`
71			`# 2`
72			address = `SCCT_CH_OCF;
73			`writedata = { 24'b0, 6'b0, 1'b1, 1'b0 };`
74			`write = 1;`
75			`# 2 write = 0;`
76
77
78			`// detect ANYEDGE @ ch0, TOGGLE @ ch1`
79			`# 2`
80			address = `SCCT_CH_ACT;
81			writedata = {24'b0, 4'b0, `SCCT_OC_TOGGLE, `SCCT_IC_ANYEDGE};
82			`write = 1;`
83			`# 2 write = 0;`
84
85			`# 2`
86			address = `SCCT_CH_CCR1;
87			`writedata = 32'h16;`
88			`write = 1;`
89			`# 2 write = 0;`
90
91			`// enable IRQ @ ch0 + ch1`
92			`# 2`
93			address = `SCCT_CH_IE;
94			`writedata = 32'b11;`
95			`write = 1;`
96			`# 2 write = 0;`
97
98			`# 2 inp = 1;`
99
100			# 6 address = `SCCT_CH_IS;
101			`writedata = 32'b1;`
102			`write = 1;`
103			`# 2 write = 0;`
104
105			`# 4 inp = 0;`
106
107			# 6 address = `SCCT_CH_IS;
108			`writedata = 32'b1;`
109			`write = 1;`
110			`# 2 write = 0;`
111
112			`# 50 write = 0;`
113
114
115			`// reset OC`
116			# 8 address = `SCCT_CH_IS;
117			`writedata = 32'b10;`
118			`write = 1;`
119			`# 2 write = 0;`
120
121
122			`# 10 $stop;`
123			`end`
124
125			`endmodule // test_scct`

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