URL https://opencores.org/ocsvn/scct/scct/trunk

Subversion Repositories scct

[/] [scct/] [trunk/] [verilog/] [scct.v] - Blame information for rev 2

Details | Compare with Previous | View Log


// $Id: scct.v 2 2015-06-15 13:52:02Z fkluge $
// Simple Capture/Compare Timer
// Implementation assumed 32 bit platform
 
`include "scct_constants.v"
 
module scct (
             clk,
             rst,
             address,
             read,
             readdata,
             writedata,
             write,
             irq,
             pins_i,
             pins_o
             );
 
   input clk;
   input rst;
 
   // Avalon interface
   input [4:0] address;
   input                          read;
   output [31:0]                   readdata;
   input [31:0]            writedata;
   input                          write;
   output                         irq;
 
   // Conduit interface
   input [`SCCT_N_CHANNELS-1:0]   pins_i;
   output [`SCCT_N_CHANNELS-1:0]  pins_o;
 
 
   reg [31:0]              readdata;
 
 
   // internal counter interface
   // TODO: replace single-bit X_i, X_i_wen signals by a single signal
   wire [`SCCT_COUNTER_CTR_WIDTH-1:0] counter;
   reg                                ctr_irq_enable_i;
   reg                                ctr_irq_enable_i_wen;
   reg                                ctr_irq_status_i;
   reg                                ctr_irq_status_i_wen;
   reg [`SCCT_COUNTER_PSC_WIDTH-1:0]  ctr_prescaler_i;
   reg                                ctr_prescaler_i_wen;
   wire                               ctr_irq_enable_o;
   wire                               ctr_irq_status_o;
   wire [`SCCT_COUNTER_PSC_WIDTH-1:0] ctr_prescaler_o;
   wire                               ctr_counter_changed;
 
 
   // internal channels interface
   // TODO: replace single-bit X_i, X_i_wen signals by a single signal
   reg [`SCCT_N_CHANNELS-1:0]          ch_icoc_select_i;
   reg                                ch_icoc_select_i_wen;
   reg [`SCCT_N_CHANNELS*2-1:0]       ch_icoc_action_i;
   reg                                ch_icoc_action_i_wen;
   reg [`SCCT_COUNTER_CTR_WIDTH-1:0]  ch_i_cc_reg [0:`SCCT_N_CHANNELS-1];
   reg [`SCCT_N_CHANNELS-1:0]          ch_i_cc_reg_wen;
   reg [`SCCT_N_CHANNELS-1:0]          ch_irq_enable_i;
   reg                                ch_irq_enable_i_wen;
   reg [`SCCT_N_CHANNELS-1:0]          ch_irq_status_i;
   reg                                ch_irq_status_i_wen;
   reg [`SCCT_N_CHANNELS-1:0]          ch_force_oc_i;
   reg                                ch_force_oc_i_wen;
   wire [`SCCT_N_CHANNELS-1:0]         ch_icoc_select_o;
   wire [`SCCT_N_CHANNELS*2-1:0]      ch_icoc_action_o;
   wire [`SCCT_COUNTER_CTR_WIDTH-1:0] ch_cc_reg_o [0:`SCCT_N_CHANNELS-1];
   wire [`SCCT_N_CHANNELS-1:0]         ch_irq_enable_o;
   wire [`SCCT_N_CHANNELS-1:0]         ch_irq_status_o;
   // pins through conduit interface
   reg                                irq;
 
   //assign irq = ((ctr_irq_status_o == 0) && (ch_irq_status_o == `SCCT_N_CHANNELS'b00)) ? 0 : 1;
   //assign irq = ((ctr_irq_status_o == 1) || (ch_irq_status_o != 0)) ? 1 : 0;
 
 
   //assign irq = ( (ctr_irq_status_o == 1) || (ch_irq_status_o[1] == 1) ) ? 1 : 0;
   //assign irq = ( ctr_irq_status_o | ch_irq_status_o[0] | ch_irq_status_o[1] | ch_irq_status_o[2] | ch_irq_status_o[3] | ch_irq_status_o[4] | ch_irq_status_o[5] | ch_irq_status_o[6] | ch_irq_status_o[7] );
   //assign irq = (ch_irq_status_o === `SCCT_N_CHANNELS'b0) ? 0 : 1;
   //assign irq = ( ctr_irq_status_o || ch_irq_status_o[0] || ch_irq_status_o[1] || ch_irq_status_o[2] || ch_irq_status_o[3] || ch_irq_status_o[4] || ch_irq_status_o[5] || ch_irq_status_o[6] || ch_irq_status_o[7] );
   //assign irq = ( (ctr_irq_status_o == 1) | (ch_irq_status_o[0] == 1) | (ch_irq_status_o[1] == 1) | (ch_irq_status_o[2] == 1) | (ch_irq_status_o[3] == 1) | (ch_irq_status_o[4] == 1) | (ch_irq_status_o[5] == 1) | (ch_irq_status_o[6] == 1) | (ch_irq_status_o[7] == 1) );
   //assign irq = ch_irq_status_o[0];
 
   // assignment of irq wire results in 'x' once an irq is asserted,
   // so we have to do it this way...
   always @(ctr_irq_status_o or ch_irq_status_o)
     irq <= ((ctr_irq_status_o == 1) || (ch_irq_status_o != 0)) ? 1 : 0;
     //irq <= ( (ctr_irq_status_o == 1) | (ch_irq_status_o[0] == 1) | (ch_irq_status_o[1] == 1) | (ch_irq_status_o[2] == 1) | (ch_irq_status_o[3] == 1) | (ch_irq_status_o[4] == 1) | (ch_irq_status_o[5] == 1) | (ch_irq_status_o[6] == 1) | (ch_irq_status_o[7] == 1) );
 
 
   /*
   always @ (ch_irq_status_o) begin
      $display("@%0d ch_irq_status %b, irq %b",$time,ch_irq_status_o, irq);
      #3 $display("@%0d ch_irq_status %b, irq %b",$time,ch_irq_status_o, irq);
   end
   */
 
   scct_counter my_counter(
                           .clk(clk),
                           .rst(rst),
                           .counter(counter),
                           .counter_changed(ctr_counter_changed),
                           .irq_enable_i(ctr_irq_enable_i),
                           .irq_enable_i_wen(ctr_irq_enable_i_wen),
                           .irq_status_i(ctr_irq_status_i),
                           .irq_status_i_wen(ctr_irq_status_i_wen),
                           .prescaler_i(ctr_prescaler_i),
                           .prescaler_i_wen(ctr_prescaler_i_wen),
                           .irq_enable_o(ctr_irq_enable_o),
                           .irq_status_o(ctr_irq_status_o),
                           .prescaler_o(ctr_prescaler_o)
                           );
 
 
 
   // Channel definitions were created with ./mkch.pl
 
   // Channel 0
   scct_channel channel0(
                    .clk(clk),
                    .rst(rst),
                    .counter(counter),
                    .counter_changed(ctr_counter_changed),
                    .icoc_select_i(ch_icoc_select_i[0]),
                    .icoc_select_i_wen(ch_icoc_select_i_wen),
                    .icoc_action_i(ch_icoc_action_i[1:0]),
                    .icoc_action_i_wen(ch_icoc_action_i_wen),
                    .i_cc_reg(ch_i_cc_reg[0]),
                    .i_cc_reg_wen(ch_i_cc_reg_wen[0]),
                    .irq_enable_i(ch_irq_enable_i[0]),
                    .irq_enable_i_wen(ch_irq_enable_i_wen),
                    .irq_status_i(ch_irq_status_i[0]),
                    .irq_status_i_wen(ch_irq_status_i_wen),
                    .force_oc_i(ch_force_oc_i[0]),
                    .force_oc_i_wen(ch_force_oc_i_wen),
                    .icoc_select_o(ch_icoc_select_o[0]),
                    .icoc_action_o(ch_icoc_action_o[1:0]),
                    .cc_reg_o(ch_cc_reg_o[0]),
                    .irq_enable_o(ch_irq_enable_o[0]),
                    .irq_status_o(ch_irq_status_o[0]),
                    .pin_i(pins_i[0]),
                    .pin_o(pins_o[0])
                    );
 
   // Channel 1
   scct_channel channel1(
                    .clk(clk),
                    .rst(rst),
                    .counter(counter),
                    .counter_changed(ctr_counter_changed),
                    .icoc_select_i(ch_icoc_select_i[1]),
                    .icoc_select_i_wen(ch_icoc_select_i_wen),
                    .icoc_action_i(ch_icoc_action_i[3:2]),
                    .icoc_action_i_wen(ch_icoc_action_i_wen),
                    .i_cc_reg(ch_i_cc_reg[1]),
                    .i_cc_reg_wen(ch_i_cc_reg_wen[1]),
                    .irq_enable_i(ch_irq_enable_i[1]),
                    .irq_enable_i_wen(ch_irq_enable_i_wen),
                    .irq_status_i(ch_irq_status_i[1]),
                    .irq_status_i_wen(ch_irq_status_i_wen),
                    .force_oc_i(ch_force_oc_i[1]),
                    .force_oc_i_wen(ch_force_oc_i_wen),
                    .icoc_select_o(ch_icoc_select_o[1]),
                    .icoc_action_o(ch_icoc_action_o[3:2]),
                    .cc_reg_o(ch_cc_reg_o[1]),
                    .irq_enable_o(ch_irq_enable_o[1]),
                    .irq_status_o(ch_irq_status_o[1]),
                    .pin_i(pins_i[1]),
                    .pin_o(pins_o[1])
                    );
 
   // Channel 2
   scct_channel channel2(
                    .clk(clk),
                    .rst(rst),
                    .counter(counter),
                    .counter_changed(ctr_counter_changed),
                    .icoc_select_i(ch_icoc_select_i[2]),
                    .icoc_select_i_wen(ch_icoc_select_i_wen),
                    .icoc_action_i(ch_icoc_action_i[5:4]),
                    .icoc_action_i_wen(ch_icoc_action_i_wen),
                    .i_cc_reg(ch_i_cc_reg[2]),
                    .i_cc_reg_wen(ch_i_cc_reg_wen[2]),
                    .irq_enable_i(ch_irq_enable_i[2]),
                    .irq_enable_i_wen(ch_irq_enable_i_wen),
                    .irq_status_i(ch_irq_status_i[2]),
                    .irq_status_i_wen(ch_irq_status_i_wen),
                    .force_oc_i(ch_force_oc_i[2]),
                    .force_oc_i_wen(ch_force_oc_i_wen),
                    .icoc_select_o(ch_icoc_select_o[2]),
                    .icoc_action_o(ch_icoc_action_o[5:4]),
                    .cc_reg_o(ch_cc_reg_o[2]),
                    .irq_enable_o(ch_irq_enable_o[2]),
                    .irq_status_o(ch_irq_status_o[2]),
                    .pin_i(pins_i[2]),
                    .pin_o(pins_o[2])
                    );
 
   // Channel 3
   scct_channel channel3(
                    .clk(clk),
                    .rst(rst),
                    .counter(counter),
                    .counter_changed(ctr_counter_changed),
                    .icoc_select_i(ch_icoc_select_i[3]),
                    .icoc_select_i_wen(ch_icoc_select_i_wen),
                    .icoc_action_i(ch_icoc_action_i[7:6]),
                    .icoc_action_i_wen(ch_icoc_action_i_wen),
                    .i_cc_reg(ch_i_cc_reg[3]),
                    .i_cc_reg_wen(ch_i_cc_reg_wen[3]),
                    .irq_enable_i(ch_irq_enable_i[3]),
                    .irq_enable_i_wen(ch_irq_enable_i_wen),
                    .irq_status_i(ch_irq_status_i[3]),
                    .irq_status_i_wen(ch_irq_status_i_wen),
                    .force_oc_i(ch_force_oc_i[3]),
                    .force_oc_i_wen(ch_force_oc_i_wen),
                    .icoc_select_o(ch_icoc_select_o[3]),
                    .icoc_action_o(ch_icoc_action_o[7:6]),
                    .cc_reg_o(ch_cc_reg_o[3]),
                    .irq_enable_o(ch_irq_enable_o[3]),
                    .irq_status_o(ch_irq_status_o[3]),
                    .pin_i(pins_i[3]),
                    .pin_o(pins_o[3])
                    );
 
   // Channel 4
   scct_channel channel4(
                    .clk(clk),
                    .rst(rst),
                    .counter(counter),
                    .counter_changed(ctr_counter_changed),
                    .icoc_select_i(ch_icoc_select_i[4]),
                    .icoc_select_i_wen(ch_icoc_select_i_wen),
                    .icoc_action_i(ch_icoc_action_i[9:8]),
                    .icoc_action_i_wen(ch_icoc_action_i_wen),
                    .i_cc_reg(ch_i_cc_reg[4]),
                    .i_cc_reg_wen(ch_i_cc_reg_wen[4]),
                    .irq_enable_i(ch_irq_enable_i[4]),
                    .irq_enable_i_wen(ch_irq_enable_i_wen),
                    .irq_status_i(ch_irq_status_i[4]),
                    .irq_status_i_wen(ch_irq_status_i_wen),
                    .force_oc_i(ch_force_oc_i[4]),
                    .force_oc_i_wen(ch_force_oc_i_wen),
                    .icoc_select_o(ch_icoc_select_o[4]),
                    .icoc_action_o(ch_icoc_action_o[9:8]),
                    .cc_reg_o(ch_cc_reg_o[4]),
                    .irq_enable_o(ch_irq_enable_o[4]),
                    .irq_status_o(ch_irq_status_o[4]),
                    .pin_i(pins_i[4]),
                    .pin_o(pins_o[4])
                    );
 
   // Channel 5
   scct_channel channel5(
                    .clk(clk),
                    .rst(rst),
                    .counter(counter),
                    .counter_changed(ctr_counter_changed),
                    .icoc_select_i(ch_icoc_select_i[5]),
                    .icoc_select_i_wen(ch_icoc_select_i_wen),
                    .icoc_action_i(ch_icoc_action_i[11:10]),
                    .icoc_action_i_wen(ch_icoc_action_i_wen),
                    .i_cc_reg(ch_i_cc_reg[5]),
                    .i_cc_reg_wen(ch_i_cc_reg_wen[5]),
                    .irq_enable_i(ch_irq_enable_i[5]),
                    .irq_enable_i_wen(ch_irq_enable_i_wen),
                    .irq_status_i(ch_irq_status_i[5]),
                    .irq_status_i_wen(ch_irq_status_i_wen),
                    .force_oc_i(ch_force_oc_i[5]),
                    .force_oc_i_wen(ch_force_oc_i_wen),
                    .icoc_select_o(ch_icoc_select_o[5]),
                    .icoc_action_o(ch_icoc_action_o[11:10]),
                    .cc_reg_o(ch_cc_reg_o[5]),
                    .irq_enable_o(ch_irq_enable_o[5]),
                    .irq_status_o(ch_irq_status_o[5]),
                    .pin_i(pins_i[5]),
                    .pin_o(pins_o[5])
                    );
 
   // Channel 6
   scct_channel channel6(
                    .clk(clk),
                    .rst(rst),
                    .counter(counter),
                    .counter_changed(ctr_counter_changed),
                    .icoc_select_i(ch_icoc_select_i[6]),
                    .icoc_select_i_wen(ch_icoc_select_i_wen),
                    .icoc_action_i(ch_icoc_action_i[13:12]),
                    .icoc_action_i_wen(ch_icoc_action_i_wen),
                    .i_cc_reg(ch_i_cc_reg[6]),
                    .i_cc_reg_wen(ch_i_cc_reg_wen[6]),
                    .irq_enable_i(ch_irq_enable_i[6]),
                    .irq_enable_i_wen(ch_irq_enable_i_wen),
                    .irq_status_i(ch_irq_status_i[6]),
                    .irq_status_i_wen(ch_irq_status_i_wen),
                    .force_oc_i(ch_force_oc_i[6]),
                    .force_oc_i_wen(ch_force_oc_i_wen),
                    .icoc_select_o(ch_icoc_select_o[6]),
                    .icoc_action_o(ch_icoc_action_o[13:12]),
                    .cc_reg_o(ch_cc_reg_o[6]),
                    .irq_enable_o(ch_irq_enable_o[6]),
                    .irq_status_o(ch_irq_status_o[6]),
                    .pin_i(pins_i[6]),
                    .pin_o(pins_o[6])
                    );
 
   // Channel 7
   scct_channel channel7(
                    .clk(clk),
                    .rst(rst),
                    .counter(counter),
                    .counter_changed(ctr_counter_changed),
                    .icoc_select_i(ch_icoc_select_i[7]),
                    .icoc_select_i_wen(ch_icoc_select_i_wen),
                    .icoc_action_i(ch_icoc_action_i[15:14]),
                    .icoc_action_i_wen(ch_icoc_action_i_wen),
                    .i_cc_reg(ch_i_cc_reg[7]),
                    .i_cc_reg_wen(ch_i_cc_reg_wen[7]),
                    .irq_enable_i(ch_irq_enable_i[7]),
                    .irq_enable_i_wen(ch_irq_enable_i_wen),
                    .irq_status_i(ch_irq_status_i[7]),
                    .irq_status_i_wen(ch_irq_status_i_wen),
                    .force_oc_i(ch_force_oc_i[7]),
                    .force_oc_i_wen(ch_force_oc_i_wen),
                    .icoc_select_o(ch_icoc_select_o[7]),
                    .icoc_action_o(ch_icoc_action_o[15:14]),
                    .cc_reg_o(ch_cc_reg_o[7]),
                    .irq_enable_o(ch_irq_enable_o[7]),
                    .irq_status_o(ch_irq_status_o[7]),
                    .pin_i(pins_i[7]),
                    .pin_o(pins_o[7])
                    );
 
 
   // read   
   always @(posedge clk or posedge rst)
     begin
        if (rst)
          begin
             readdata <= 0;
          end
        else
          begin
             if (read)
               begin
                  case (address)
                    `SCCT_CTR: readdata <= counter;
                    `SCCT_PSC: readdata <= ctr_prescaler_o;
                    `SCCT_CTR_IE: readdata <= ctr_irq_enable_o;
                    `SCCT_CTR_IS: readdata <= ctr_irq_status_o;
                    `SCCT_CH_MS: readdata <= {24'b0, ch_icoc_select_o};
                    `SCCT_CH_ACT: readdata <= {16'b0, ch_icoc_action_o};
                    `SCCT_CH_IE: readdata <= {24'b0, ch_irq_enable_o};
                    `SCCT_CH_IS: readdata <= {24'b0, ch_irq_status_o};
                    `SCCT_CH_OCF: readdata <= 32'b0;
                    `SCCT_CH_INP: readdata <= {24'b0, pins_i};
                    `SCCT_CH_OUT: readdata <= {24'b0, pins_o};
                    `SCCT_CH_CCR0: readdata <= ch_cc_reg_o[0];
                    `SCCT_CH_CCR1: readdata <= ch_cc_reg_o[1];
                    `SCCT_CH_CCR2: readdata <= ch_cc_reg_o[2];
                    `SCCT_CH_CCR3: readdata <= ch_cc_reg_o[3];
                    `SCCT_CH_CCR4: readdata <= ch_cc_reg_o[4];
                    `SCCT_CH_CCR5: readdata <= ch_cc_reg_o[5];
                    `SCCT_CH_CCR6: readdata <= ch_cc_reg_o[6];
                    `SCCT_CH_CCR7: readdata <= ch_cc_reg_o[7];
                    default:;
                  endcase // case (address)
               end
          end
     end
 
 
   // write
   always @(posedge clk or posedge rst)
     begin
        if (rst)
          begin
          end
        else
          begin
          end
     end
 
   // reset write_enable signals
   always @(posedge clk or posedge rst)
     begin
        if (rst)
          begin
             ctr_prescaler_i_wen <= 0;
             ctr_irq_enable_i_wen <= 0;
             ctr_irq_status_i_wen <= 0;
             ch_icoc_select_i_wen <= 0;
             ch_icoc_action_i_wen <= 0;
             ch_irq_enable_i_wen <= 0;
             ch_irq_status_i_wen <= 0;
             ch_force_oc_i_wen <= 0;
             ch_i_cc_reg_wen[0] <= 0;
             ch_i_cc_reg_wen[1] <= 0;
             ch_i_cc_reg_wen[2] <= 0;
             ch_i_cc_reg_wen[3] <= 0;
             ch_i_cc_reg_wen[4] <= 0;
             ch_i_cc_reg_wen[5] <= 0;
             ch_i_cc_reg_wen[6] <= 0;
             ch_i_cc_reg_wen[7] <= 0;
          end
        else
          begin
             if (write)
               begin
                  case (address)
                    //`SCCT_COUNTER:;
                    `SCCT_PSC: begin
                       ctr_prescaler_i <= writedata;
                       ctr_prescaler_i_wen <= 1;
                    end
 
                    `SCCT_CTR_IE: begin
                       ctr_irq_enable_i <= writedata;
                       ctr_irq_enable_i_wen <= 1;
                    end
 
                    `SCCT_CTR_IS: begin
                       ctr_irq_status_i <= writedata;
                       ctr_irq_status_i_wen <= 1;
                    end
 
                    `SCCT_CH_MS: begin
                       ch_icoc_select_i <= writedata[7:0];
                       ch_icoc_select_i_wen <= 1;
                    end
 
                    `SCCT_CH_ACT: begin
                       ch_icoc_action_i <= writedata[15:0];
                       ch_icoc_action_i_wen <= 1;
                    end
 
                    `SCCT_CH_IE: begin
                       ch_irq_enable_i <= writedata[7:0];
                       ch_irq_enable_i_wen <= 1;
                    end
 
                    `SCCT_CH_IS: begin
                       ch_irq_status_i <= writedata[7:0];
                       ch_irq_status_i_wen <= 1;
                    end
 
                    `SCCT_CH_OCF: begin
                       ch_force_oc_i <= writedata[7:0];
                       ch_force_oc_i_wen <= 1;
                    end
 
                    `SCCT_CH_CCR0: begin
                       ch_i_cc_reg[0] <= writedata;
                       ch_i_cc_reg_wen[0] <= 1;
                    end
 
                    `SCCT_CH_CCR1: begin
                       ch_i_cc_reg[1] <= writedata;
                       ch_i_cc_reg_wen[1] <= 1;
                    end
 
                    `SCCT_CH_CCR2: begin
                       ch_i_cc_reg[2] <= writedata;
                       ch_i_cc_reg_wen[2] <= 1;
                    end
 
                    `SCCT_CH_CCR3: begin
                       ch_i_cc_reg[3] <= writedata;
                       ch_i_cc_reg_wen[3] <= 1;
                    end
 
                    `SCCT_CH_CCR4: begin
                       ch_i_cc_reg[4] <= writedata;
                       ch_i_cc_reg_wen[4] <= 1;
                    end
 
                    `SCCT_CH_CCR5: begin
                       ch_i_cc_reg[5] <= writedata;
                       ch_i_cc_reg_wen[5] <= 1;
                    end
 
                    `SCCT_CH_CCR6: begin
                       ch_i_cc_reg[6] <= writedata;
                       ch_i_cc_reg_wen[6] <= 1;
                    end
 
                    `SCCT_CH_CCR7: begin
                       ch_i_cc_reg[7] <= writedata;
                       ch_i_cc_reg_wen[7] <= 1;
                    end
 
                    default: begin
                    end
 
                  endcase // case (address)
               end // if (write)
             else // !if (write)
               begin
                  if (ctr_prescaler_i_wen) ctr_prescaler_i_wen <= 0;
                  if (ctr_irq_enable_i_wen) ctr_irq_enable_i_wen <= 0;
                  if (ctr_irq_status_i_wen) ctr_irq_status_i_wen <= 0;
                  if (ch_icoc_select_i_wen) ch_icoc_select_i_wen <= 0;
                  if (ch_icoc_action_i_wen) ch_icoc_action_i_wen <= 0;
                  if (ch_irq_enable_i_wen) ch_irq_enable_i_wen <= 0;
                  if (ch_irq_status_i_wen) ch_irq_status_i_wen <= 0;
                  if (ch_force_oc_i_wen) ch_force_oc_i_wen <= 0;
                  if (ch_i_cc_reg_wen[0]) ch_i_cc_reg_wen[0] <= 0;
                  if (ch_i_cc_reg_wen[1]) ch_i_cc_reg_wen[1] <= 0;
                  if (ch_i_cc_reg_wen[2]) ch_i_cc_reg_wen[2] <= 0;
                  if (ch_i_cc_reg_wen[3]) ch_i_cc_reg_wen[3] <= 0;
                  if (ch_i_cc_reg_wen[4]) ch_i_cc_reg_wen[4] <= 0;
                  if (ch_i_cc_reg_wen[5]) ch_i_cc_reg_wen[5] <= 0;
                  if (ch_i_cc_reg_wen[6]) ch_i_cc_reg_wen[6] <= 0;
                  if (ch_i_cc_reg_wen[7]) ch_i_cc_reg_wen[7] <= 0;
               end // !if(write)
          end // else: !if(rst)
     end // always @ (posedge clk or posedge rst)   
 
endmodule // cct

Browse

Tools

Subversion Repositories scct

[/] [scct/] [trunk/] [verilog/] [scct.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	fkluge	`// $Id: scct.v 2 2015-06-15 13:52:02Z fkluge $`
2			`// Simple Capture/Compare Timer`
3			`// Implementation assumed 32 bit platform`
4
5			`include "scct_constants.v"
6
7			`module scct (`
8			`clk,`
9			`rst,`
10			`address,`
11			`read,`
12			`readdata,`
13			`writedata,`
14			`write,`
15			`irq,`
16			`pins_i,`
17			`pins_o`
18			`);`
19
20			`input clk;`
21			`input rst;`
22
23			`// Avalon interface`
24			`input [4:0] address;`
25			`input read;`
26			`output [31:0] readdata;`
27			`input [31:0] writedata;`
28			`input write;`
29			`output irq;`
30
31			`// Conduit interface`
32			input [`SCCT_N_CHANNELS-1:0] pins_i;
33			output [`SCCT_N_CHANNELS-1:0] pins_o;
34
35
36			`reg [31:0] readdata;`
37
38
39			`// internal counter interface`
40			`// TODO: replace single-bit X_i, X_i_wen signals by a single signal`
41			wire [`SCCT_COUNTER_CTR_WIDTH-1:0] counter;
42			`reg ctr_irq_enable_i;`
43			`reg ctr_irq_enable_i_wen;`
44			`reg ctr_irq_status_i;`
45			`reg ctr_irq_status_i_wen;`
46			reg [`SCCT_COUNTER_PSC_WIDTH-1:0] ctr_prescaler_i;
47			`reg ctr_prescaler_i_wen;`
48			`wire ctr_irq_enable_o;`
49			`wire ctr_irq_status_o;`
50			wire [`SCCT_COUNTER_PSC_WIDTH-1:0] ctr_prescaler_o;
51			`wire ctr_counter_changed;`
52
53
54			`// internal channels interface`
55			`// TODO: replace single-bit X_i, X_i_wen signals by a single signal`
56			reg [`SCCT_N_CHANNELS-1:0] ch_icoc_select_i;
57			`reg ch_icoc_select_i_wen;`
58			reg [`SCCT_N_CHANNELS*2-1:0] ch_icoc_action_i;
59			`reg ch_icoc_action_i_wen;`
60			reg [`SCCT_COUNTER_CTR_WIDTH-1:0] ch_i_cc_reg [0:`SCCT_N_CHANNELS-1];
61			reg [`SCCT_N_CHANNELS-1:0] ch_i_cc_reg_wen;
62			reg [`SCCT_N_CHANNELS-1:0] ch_irq_enable_i;
63			`reg ch_irq_enable_i_wen;`
64			reg [`SCCT_N_CHANNELS-1:0] ch_irq_status_i;
65			`reg ch_irq_status_i_wen;`
66			reg [`SCCT_N_CHANNELS-1:0] ch_force_oc_i;
67			`reg ch_force_oc_i_wen;`
68			wire [`SCCT_N_CHANNELS-1:0] ch_icoc_select_o;
69			wire [`SCCT_N_CHANNELS*2-1:0] ch_icoc_action_o;
70			wire [`SCCT_COUNTER_CTR_WIDTH-1:0] ch_cc_reg_o [0:`SCCT_N_CHANNELS-1];
71			wire [`SCCT_N_CHANNELS-1:0] ch_irq_enable_o;
72			wire [`SCCT_N_CHANNELS-1:0] ch_irq_status_o;
73			`// pins through conduit interface`
74			`reg irq;`
75
76			//assign irq = ((ctr_irq_status_o == 0) && (ch_irq_status_o == `SCCT_N_CHANNELS'b00)) ? 0 : 1;
77			`//assign irq = ((ctr_irq_status_o == 1) \|\| (ch_irq_status_o != 0)) ? 1 : 0;`
78
79
80			`//assign irq = ( (ctr_irq_status_o == 1) \|\| (ch_irq_status_o[1] == 1) ) ? 1 : 0;`
81			`//assign irq = ( ctr_irq_status_o \| ch_irq_status_o[0] \| ch_irq_status_o[1] \| ch_irq_status_o[2] \| ch_irq_status_o[3] \| ch_irq_status_o[4] \| ch_irq_status_o[5] \| ch_irq_status_o[6] \| ch_irq_status_o[7] );`
82			//assign irq = (ch_irq_status_o === `SCCT_N_CHANNELS'b0) ? 0 : 1;
83			`//assign irq = ( ctr_irq_status_o \|\| ch_irq_status_o[0] \|\| ch_irq_status_o[1] \|\| ch_irq_status_o[2] \|\| ch_irq_status_o[3] \|\| ch_irq_status_o[4] \|\| ch_irq_status_o[5] \|\| ch_irq_status_o[6] \|\| ch_irq_status_o[7] );`
84			`//assign irq = ( (ctr_irq_status_o == 1) \| (ch_irq_status_o[0] == 1) \| (ch_irq_status_o[1] == 1) \| (ch_irq_status_o[2] == 1) \| (ch_irq_status_o[3] == 1) \| (ch_irq_status_o[4] == 1) \| (ch_irq_status_o[5] == 1) \| (ch_irq_status_o[6] == 1) \| (ch_irq_status_o[7] == 1) );`
85			`//assign irq = ch_irq_status_o[0];`
86
87			`// assignment of irq wire results in 'x' once an irq is asserted,`
88			`// so we have to do it this way...`
89			`always @(ctr_irq_status_o or ch_irq_status_o)`
90			`irq <= ((ctr_irq_status_o == 1) \|\| (ch_irq_status_o != 0)) ? 1 : 0;`
91			`//irq <= ( (ctr_irq_status_o == 1) \| (ch_irq_status_o[0] == 1) \| (ch_irq_status_o[1] == 1) \| (ch_irq_status_o[2] == 1) \| (ch_irq_status_o[3] == 1) \| (ch_irq_status_o[4] == 1) \| (ch_irq_status_o[5] == 1) \| (ch_irq_status_o[6] == 1) \| (ch_irq_status_o[7] == 1) );`
92
93
94			`/*`
95			`always @ (ch_irq_status_o) begin`
96			`$display("@%0d ch_irq_status %b, irq %b",$time,ch_irq_status_o, irq);`
97			`#3 $display("@%0d ch_irq_status %b, irq %b",$time,ch_irq_status_o, irq);`
98			`end`
99			`*/`
100
101			`scct_counter my_counter(`
102			`.clk(clk),`
103			`.rst(rst),`
104			`.counter(counter),`
105			`.counter_changed(ctr_counter_changed),`
106			`.irq_enable_i(ctr_irq_enable_i),`
107			`.irq_enable_i_wen(ctr_irq_enable_i_wen),`
108			`.irq_status_i(ctr_irq_status_i),`
109			`.irq_status_i_wen(ctr_irq_status_i_wen),`
110			`.prescaler_i(ctr_prescaler_i),`
111			`.prescaler_i_wen(ctr_prescaler_i_wen),`
112			`.irq_enable_o(ctr_irq_enable_o),`
113			`.irq_status_o(ctr_irq_status_o),`
114			`.prescaler_o(ctr_prescaler_o)`
115			`);`
116
117
118
119			`// Channel definitions were created with ./mkch.pl`
120
121			`// Channel 0`
122			`scct_channel channel0(`
123			`.clk(clk),`
124			`.rst(rst),`
125			`.counter(counter),`
126			`.counter_changed(ctr_counter_changed),`
127			`.icoc_select_i(ch_icoc_select_i[0]),`
128			`.icoc_select_i_wen(ch_icoc_select_i_wen),`
129			`.icoc_action_i(ch_icoc_action_i[1:0]),`
130			`.icoc_action_i_wen(ch_icoc_action_i_wen),`
131			`.i_cc_reg(ch_i_cc_reg[0]),`
132			`.i_cc_reg_wen(ch_i_cc_reg_wen[0]),`
133			`.irq_enable_i(ch_irq_enable_i[0]),`
134			`.irq_enable_i_wen(ch_irq_enable_i_wen),`
135			`.irq_status_i(ch_irq_status_i[0]),`
136			`.irq_status_i_wen(ch_irq_status_i_wen),`
137			`.force_oc_i(ch_force_oc_i[0]),`
138			`.force_oc_i_wen(ch_force_oc_i_wen),`
139			`.icoc_select_o(ch_icoc_select_o[0]),`
140			`.icoc_action_o(ch_icoc_action_o[1:0]),`
141			`.cc_reg_o(ch_cc_reg_o[0]),`
142			`.irq_enable_o(ch_irq_enable_o[0]),`
143			`.irq_status_o(ch_irq_status_o[0]),`
144			`.pin_i(pins_i[0]),`
145			`.pin_o(pins_o[0])`
146			`);`
147
148			`// Channel 1`
149			`scct_channel channel1(`
150			`.clk(clk),`
151			`.rst(rst),`
152			`.counter(counter),`
153			`.counter_changed(ctr_counter_changed),`
154			`.icoc_select_i(ch_icoc_select_i[1]),`
155			`.icoc_select_i_wen(ch_icoc_select_i_wen),`
156			`.icoc_action_i(ch_icoc_action_i[3:2]),`
157			`.icoc_action_i_wen(ch_icoc_action_i_wen),`
158			`.i_cc_reg(ch_i_cc_reg[1]),`
159			`.i_cc_reg_wen(ch_i_cc_reg_wen[1]),`
160			`.irq_enable_i(ch_irq_enable_i[1]),`
161			`.irq_enable_i_wen(ch_irq_enable_i_wen),`
162			`.irq_status_i(ch_irq_status_i[1]),`
163			`.irq_status_i_wen(ch_irq_status_i_wen),`
164			`.force_oc_i(ch_force_oc_i[1]),`
165			`.force_oc_i_wen(ch_force_oc_i_wen),`
166			`.icoc_select_o(ch_icoc_select_o[1]),`
167			`.icoc_action_o(ch_icoc_action_o[3:2]),`
168			`.cc_reg_o(ch_cc_reg_o[1]),`
169			`.irq_enable_o(ch_irq_enable_o[1]),`
170			`.irq_status_o(ch_irq_status_o[1]),`
171			`.pin_i(pins_i[1]),`
172			`.pin_o(pins_o[1])`
173			`);`
174
175			`// Channel 2`
176			`scct_channel channel2(`
177			`.clk(clk),`
178			`.rst(rst),`
179			`.counter(counter),`
180			`.counter_changed(ctr_counter_changed),`
181			`.icoc_select_i(ch_icoc_select_i[2]),`
182			`.icoc_select_i_wen(ch_icoc_select_i_wen),`
183			`.icoc_action_i(ch_icoc_action_i[5:4]),`
184			`.icoc_action_i_wen(ch_icoc_action_i_wen),`
185			`.i_cc_reg(ch_i_cc_reg[2]),`
186			`.i_cc_reg_wen(ch_i_cc_reg_wen[2]),`
187			`.irq_enable_i(ch_irq_enable_i[2]),`
188			`.irq_enable_i_wen(ch_irq_enable_i_wen),`
189			`.irq_status_i(ch_irq_status_i[2]),`
190			`.irq_status_i_wen(ch_irq_status_i_wen),`
191			`.force_oc_i(ch_force_oc_i[2]),`
192			`.force_oc_i_wen(ch_force_oc_i_wen),`
193			`.icoc_select_o(ch_icoc_select_o[2]),`
194			`.icoc_action_o(ch_icoc_action_o[5:4]),`
195			`.cc_reg_o(ch_cc_reg_o[2]),`
196			`.irq_enable_o(ch_irq_enable_o[2]),`
197			`.irq_status_o(ch_irq_status_o[2]),`
198			`.pin_i(pins_i[2]),`
199			`.pin_o(pins_o[2])`
200			`);`
201
202			`// Channel 3`
203			`scct_channel channel3(`
204			`.clk(clk),`
205			`.rst(rst),`
206			`.counter(counter),`
207			`.counter_changed(ctr_counter_changed),`
208			`.icoc_select_i(ch_icoc_select_i[3]),`
209			`.icoc_select_i_wen(ch_icoc_select_i_wen),`
210			`.icoc_action_i(ch_icoc_action_i[7:6]),`
211			`.icoc_action_i_wen(ch_icoc_action_i_wen),`
212			`.i_cc_reg(ch_i_cc_reg[3]),`
213			`.i_cc_reg_wen(ch_i_cc_reg_wen[3]),`
214			`.irq_enable_i(ch_irq_enable_i[3]),`
215			`.irq_enable_i_wen(ch_irq_enable_i_wen),`
216			`.irq_status_i(ch_irq_status_i[3]),`
217			`.irq_status_i_wen(ch_irq_status_i_wen),`
218			`.force_oc_i(ch_force_oc_i[3]),`
219			`.force_oc_i_wen(ch_force_oc_i_wen),`
220			`.icoc_select_o(ch_icoc_select_o[3]),`
221			`.icoc_action_o(ch_icoc_action_o[7:6]),`
222			`.cc_reg_o(ch_cc_reg_o[3]),`
223			`.irq_enable_o(ch_irq_enable_o[3]),`
224			`.irq_status_o(ch_irq_status_o[3]),`
225			`.pin_i(pins_i[3]),`
226			`.pin_o(pins_o[3])`
227			`);`
228
229			`// Channel 4`
230			`scct_channel channel4(`
231			`.clk(clk),`
232			`.rst(rst),`
233			`.counter(counter),`
234			`.counter_changed(ctr_counter_changed),`
235			`.icoc_select_i(ch_icoc_select_i[4]),`
236			`.icoc_select_i_wen(ch_icoc_select_i_wen),`
237			`.icoc_action_i(ch_icoc_action_i[9:8]),`
238			`.icoc_action_i_wen(ch_icoc_action_i_wen),`
239			`.i_cc_reg(ch_i_cc_reg[4]),`
240			`.i_cc_reg_wen(ch_i_cc_reg_wen[4]),`
241			`.irq_enable_i(ch_irq_enable_i[4]),`
242			`.irq_enable_i_wen(ch_irq_enable_i_wen),`
243			`.irq_status_i(ch_irq_status_i[4]),`
244			`.irq_status_i_wen(ch_irq_status_i_wen),`
245			`.force_oc_i(ch_force_oc_i[4]),`
246			`.force_oc_i_wen(ch_force_oc_i_wen),`
247			`.icoc_select_o(ch_icoc_select_o[4]),`
248			`.icoc_action_o(ch_icoc_action_o[9:8]),`
249			`.cc_reg_o(ch_cc_reg_o[4]),`
250			`.irq_enable_o(ch_irq_enable_o[4]),`
251			`.irq_status_o(ch_irq_status_o[4]),`
252			`.pin_i(pins_i[4]),`
253			`.pin_o(pins_o[4])`
254			`);`
255
256			`// Channel 5`
257			`scct_channel channel5(`
258			`.clk(clk),`
259			`.rst(rst),`
260			`.counter(counter),`
261			`.counter_changed(ctr_counter_changed),`
262			`.icoc_select_i(ch_icoc_select_i[5]),`
263			`.icoc_select_i_wen(ch_icoc_select_i_wen),`
264			`.icoc_action_i(ch_icoc_action_i[11:10]),`
265			`.icoc_action_i_wen(ch_icoc_action_i_wen),`
266			`.i_cc_reg(ch_i_cc_reg[5]),`
267			`.i_cc_reg_wen(ch_i_cc_reg_wen[5]),`
268			`.irq_enable_i(ch_irq_enable_i[5]),`
269			`.irq_enable_i_wen(ch_irq_enable_i_wen),`
270			`.irq_status_i(ch_irq_status_i[5]),`
271			`.irq_status_i_wen(ch_irq_status_i_wen),`
272			`.force_oc_i(ch_force_oc_i[5]),`
273			`.force_oc_i_wen(ch_force_oc_i_wen),`
274			`.icoc_select_o(ch_icoc_select_o[5]),`
275			`.icoc_action_o(ch_icoc_action_o[11:10]),`
276			`.cc_reg_o(ch_cc_reg_o[5]),`
277			`.irq_enable_o(ch_irq_enable_o[5]),`
278			`.irq_status_o(ch_irq_status_o[5]),`
279			`.pin_i(pins_i[5]),`
280			`.pin_o(pins_o[5])`
281			`);`
282
283			`// Channel 6`
284			`scct_channel channel6(`
285			`.clk(clk),`
286			`.rst(rst),`
287			`.counter(counter),`
288			`.counter_changed(ctr_counter_changed),`
289			`.icoc_select_i(ch_icoc_select_i[6]),`
290			`.icoc_select_i_wen(ch_icoc_select_i_wen),`
291			`.icoc_action_i(ch_icoc_action_i[13:12]),`
292			`.icoc_action_i_wen(ch_icoc_action_i_wen),`
293			`.i_cc_reg(ch_i_cc_reg[6]),`
294			`.i_cc_reg_wen(ch_i_cc_reg_wen[6]),`
295			`.irq_enable_i(ch_irq_enable_i[6]),`
296			`.irq_enable_i_wen(ch_irq_enable_i_wen),`
297			`.irq_status_i(ch_irq_status_i[6]),`
298			`.irq_status_i_wen(ch_irq_status_i_wen),`
299			`.force_oc_i(ch_force_oc_i[6]),`
300			`.force_oc_i_wen(ch_force_oc_i_wen),`
301			`.icoc_select_o(ch_icoc_select_o[6]),`
302			`.icoc_action_o(ch_icoc_action_o[13:12]),`
303			`.cc_reg_o(ch_cc_reg_o[6]),`
304			`.irq_enable_o(ch_irq_enable_o[6]),`
305			`.irq_status_o(ch_irq_status_o[6]),`
306			`.pin_i(pins_i[6]),`
307			`.pin_o(pins_o[6])`
308			`);`
309
310			`// Channel 7`
311			`scct_channel channel7(`
312			`.clk(clk),`
313			`.rst(rst),`
314			`.counter(counter),`
315			`.counter_changed(ctr_counter_changed),`
316			`.icoc_select_i(ch_icoc_select_i[7]),`
317			`.icoc_select_i_wen(ch_icoc_select_i_wen),`
318			`.icoc_action_i(ch_icoc_action_i[15:14]),`
319			`.icoc_action_i_wen(ch_icoc_action_i_wen),`
320			`.i_cc_reg(ch_i_cc_reg[7]),`
321			`.i_cc_reg_wen(ch_i_cc_reg_wen[7]),`
322			`.irq_enable_i(ch_irq_enable_i[7]),`
323			`.irq_enable_i_wen(ch_irq_enable_i_wen),`
324			`.irq_status_i(ch_irq_status_i[7]),`
325			`.irq_status_i_wen(ch_irq_status_i_wen),`
326			`.force_oc_i(ch_force_oc_i[7]),`
327			`.force_oc_i_wen(ch_force_oc_i_wen),`
328			`.icoc_select_o(ch_icoc_select_o[7]),`
329			`.icoc_action_o(ch_icoc_action_o[15:14]),`
330			`.cc_reg_o(ch_cc_reg_o[7]),`
331			`.irq_enable_o(ch_irq_enable_o[7]),`
332			`.irq_status_o(ch_irq_status_o[7]),`
333			`.pin_i(pins_i[7]),`
334			`.pin_o(pins_o[7])`
335			`);`
336
337
338			`// read`
339			`always @(posedge clk or posedge rst)`
340			`begin`
341			`if (rst)`
342			`begin`
343			`readdata <= 0;`
344			`end`
345			`else`
346			`begin`
347			`if (read)`
348			`begin`
349			`case (address)`
350			`SCCT_CTR: readdata <= counter;
351			`SCCT_PSC: readdata <= ctr_prescaler_o;
352			`SCCT_CTR_IE: readdata <= ctr_irq_enable_o;
353			`SCCT_CTR_IS: readdata <= ctr_irq_status_o;
354			`SCCT_CH_MS: readdata <= {24'b0, ch_icoc_select_o};
355			`SCCT_CH_ACT: readdata <= {16'b0, ch_icoc_action_o};
356			`SCCT_CH_IE: readdata <= {24'b0, ch_irq_enable_o};
357			`SCCT_CH_IS: readdata <= {24'b0, ch_irq_status_o};
358			`SCCT_CH_OCF: readdata <= 32'b0;
359			`SCCT_CH_INP: readdata <= {24'b0, pins_i};
360			`SCCT_CH_OUT: readdata <= {24'b0, pins_o};
361			`SCCT_CH_CCR0: readdata <= ch_cc_reg_o[0];
362			`SCCT_CH_CCR1: readdata <= ch_cc_reg_o[1];
363			`SCCT_CH_CCR2: readdata <= ch_cc_reg_o[2];
364			`SCCT_CH_CCR3: readdata <= ch_cc_reg_o[3];
365			`SCCT_CH_CCR4: readdata <= ch_cc_reg_o[4];
366			`SCCT_CH_CCR5: readdata <= ch_cc_reg_o[5];
367			`SCCT_CH_CCR6: readdata <= ch_cc_reg_o[6];
368			`SCCT_CH_CCR7: readdata <= ch_cc_reg_o[7];
369			`default:;`
370			`endcase // case (address)`
371			`end`
372			`end`
373			`end`
374
375
376			`// write`
377			`always @(posedge clk or posedge rst)`
378			`begin`
379			`if (rst)`
380			`begin`
381			`end`
382			`else`
383			`begin`
384			`end`
385			`end`
386
387			`// reset write_enable signals`
388			`always @(posedge clk or posedge rst)`
389			`begin`
390			`if (rst)`
391			`begin`
392			`ctr_prescaler_i_wen <= 0;`
393			`ctr_irq_enable_i_wen <= 0;`
394			`ctr_irq_status_i_wen <= 0;`
395			`ch_icoc_select_i_wen <= 0;`
396			`ch_icoc_action_i_wen <= 0;`
397			`ch_irq_enable_i_wen <= 0;`
398			`ch_irq_status_i_wen <= 0;`
399			`ch_force_oc_i_wen <= 0;`
400			`ch_i_cc_reg_wen[0] <= 0;`
401			`ch_i_cc_reg_wen[1] <= 0;`
402			`ch_i_cc_reg_wen[2] <= 0;`
403			`ch_i_cc_reg_wen[3] <= 0;`
404			`ch_i_cc_reg_wen[4] <= 0;`
405			`ch_i_cc_reg_wen[5] <= 0;`
406			`ch_i_cc_reg_wen[6] <= 0;`
407			`ch_i_cc_reg_wen[7] <= 0;`
408			`end`
409			`else`
410			`begin`
411			`if (write)`
412			`begin`
413			`case (address)`
414			//`SCCT_COUNTER:;
415			`SCCT_PSC: begin
416			`ctr_prescaler_i <= writedata;`
417			`ctr_prescaler_i_wen <= 1;`
418			`end`
419
420			`SCCT_CTR_IE: begin
421			`ctr_irq_enable_i <= writedata;`
422			`ctr_irq_enable_i_wen <= 1;`
423			`end`
424
425			`SCCT_CTR_IS: begin
426			`ctr_irq_status_i <= writedata;`
427			`ctr_irq_status_i_wen <= 1;`
428			`end`
429
430			`SCCT_CH_MS: begin
431			`ch_icoc_select_i <= writedata[7:0];`
432			`ch_icoc_select_i_wen <= 1;`
433			`end`
434
435			`SCCT_CH_ACT: begin
436			`ch_icoc_action_i <= writedata[15:0];`
437			`ch_icoc_action_i_wen <= 1;`
438			`end`
439
440			`SCCT_CH_IE: begin
441			`ch_irq_enable_i <= writedata[7:0];`
442			`ch_irq_enable_i_wen <= 1;`
443			`end`
444
445			`SCCT_CH_IS: begin
446			`ch_irq_status_i <= writedata[7:0];`
447			`ch_irq_status_i_wen <= 1;`
448			`end`
449
450			`SCCT_CH_OCF: begin
451			`ch_force_oc_i <= writedata[7:0];`
452			`ch_force_oc_i_wen <= 1;`
453			`end`
454
455			`SCCT_CH_CCR0: begin
456			`ch_i_cc_reg[0] <= writedata;`
457			`ch_i_cc_reg_wen[0] <= 1;`
458			`end`
459
460			`SCCT_CH_CCR1: begin
461			`ch_i_cc_reg[1] <= writedata;`
462			`ch_i_cc_reg_wen[1] <= 1;`
463			`end`
464
465			`SCCT_CH_CCR2: begin
466			`ch_i_cc_reg[2] <= writedata;`
467			`ch_i_cc_reg_wen[2] <= 1;`
468			`end`
469
470			`SCCT_CH_CCR3: begin
471			`ch_i_cc_reg[3] <= writedata;`
472			`ch_i_cc_reg_wen[3] <= 1;`
473			`end`
474
475			`SCCT_CH_CCR4: begin
476			`ch_i_cc_reg[4] <= writedata;`
477			`ch_i_cc_reg_wen[4] <= 1;`
478			`end`
479
480			`SCCT_CH_CCR5: begin
481			`ch_i_cc_reg[5] <= writedata;`
482			`ch_i_cc_reg_wen[5] <= 1;`
483			`end`
484
485			`SCCT_CH_CCR6: begin
486			`ch_i_cc_reg[6] <= writedata;`
487			`ch_i_cc_reg_wen[6] <= 1;`
488			`end`
489
490			`SCCT_CH_CCR7: begin
491			`ch_i_cc_reg[7] <= writedata;`
492			`ch_i_cc_reg_wen[7] <= 1;`
493			`end`
494
495			`default: begin`
496			`end`
497
498			`endcase // case (address)`
499			`end // if (write)`
500			`else // !if (write)`
501			`begin`
502			`if (ctr_prescaler_i_wen) ctr_prescaler_i_wen <= 0;`
503			`if (ctr_irq_enable_i_wen) ctr_irq_enable_i_wen <= 0;`
504			`if (ctr_irq_status_i_wen) ctr_irq_status_i_wen <= 0;`
505			`if (ch_icoc_select_i_wen) ch_icoc_select_i_wen <= 0;`
506			`if (ch_icoc_action_i_wen) ch_icoc_action_i_wen <= 0;`
507			`if (ch_irq_enable_i_wen) ch_irq_enable_i_wen <= 0;`
508			`if (ch_irq_status_i_wen) ch_irq_status_i_wen <= 0;`
509			`if (ch_force_oc_i_wen) ch_force_oc_i_wen <= 0;`
510			`if (ch_i_cc_reg_wen[0]) ch_i_cc_reg_wen[0] <= 0;`
511			`if (ch_i_cc_reg_wen[1]) ch_i_cc_reg_wen[1] <= 0;`
512			`if (ch_i_cc_reg_wen[2]) ch_i_cc_reg_wen[2] <= 0;`
513			`if (ch_i_cc_reg_wen[3]) ch_i_cc_reg_wen[3] <= 0;`
514			`if (ch_i_cc_reg_wen[4]) ch_i_cc_reg_wen[4] <= 0;`
515			`if (ch_i_cc_reg_wen[5]) ch_i_cc_reg_wen[5] <= 0;`
516			`if (ch_i_cc_reg_wen[6]) ch_i_cc_reg_wen[6] <= 0;`
517			`if (ch_i_cc_reg_wen[7]) ch_i_cc_reg_wen[7] <= 0;`
518			`end // !if(write)`
519			`end // else: !if(rst)`
520			`end // always @ (posedge clk or posedge rst)`
521
522			`endmodule // cct`