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[/] [scct/] [trunk/] [verilog/] [scct_channel.v] - Blame information for rev 2

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// $Id: scct_channel.v 2 2015-06-15 13:52:02Z fkluge $
// Simple timer channel
 
`include "scct_constants.v"
 
module scct_channel (
                 clk, rst, counter, counter_changed,
                 icoc_select_i, icoc_select_i_wen,
                 icoc_action_i, icoc_action_i_wen,
                 i_cc_reg, i_cc_reg_wen,
                 irq_enable_i, irq_enable_i_wen,
                 irq_status_i, irq_status_i_wen,
                 force_oc_i, force_oc_i_wen,
                 icoc_select_o, icoc_action_o, cc_reg_o, irq_enable_o, irq_status_o,
                 pin_i, pin_o
                 );
 
   input                             clk;
   input                             rst;
   input [`SCCT_COUNTER_CTR_WIDTH-1:0] counter;
   input                               counter_changed;
 
   // TODO: replace single-bit X_i, X_i_wen signals by a single signal
   input                               icoc_select_i;
   input                               icoc_select_i_wen;
   input [1:0]                          icoc_action_i;
   input                               icoc_action_i_wen;
   input [`SCCT_COUNTER_CTR_WIDTH-1:0] i_cc_reg;
   input                               i_cc_reg_wen;
   input                               irq_enable_i;
   input                               irq_enable_i_wen;
   input                               irq_status_i; // write 1 to clear flag
   input                               irq_status_i_wen;
   input                               force_oc_i;
   input                               force_oc_i_wen;
 
   output                              icoc_select_o;
   output [1:0]                 icoc_action_o;
   output [`SCCT_COUNTER_CTR_WIDTH-1:0] cc_reg_o;
   output                               irq_enable_o;
   output                               irq_status_o;
   input                                pin_i;
   output                               pin_o;
 
   reg                                  outval;
   reg                                  icoc_select;
   reg [1:0]                             icoc_action;
   reg                                  irq_enable;
   reg                                  irq_status;
 
   reg                                  icirq; // set when IC detects an edge that is interesting according to icoc_action
   reg                                  ocirq; // set when counter matches cc_reg
   wire                                 intistat;
 
   // Capture/Compare Register
   reg [`SCCT_COUNTER_CTR_WIDTH-1:0]     cc_reg;
   wire                                 oc_match;
 
   reg                                  last_input_state;
 
 
 
 
   assign icoc_select_o = icoc_select;
   assign icoc_action_o = icoc_action;
   assign cc_reg_o = cc_reg;
   assign irq_enable_o = irq_enable;
   assign irq_status_o = irq_status;
 
 
   //assign pin = (icoc_select == `SCCT_CH_MS_IC) ? 1'bz : outval;
   assign pin_o = outval;
 
 
 
   assign intistat = (icoc_select == `SCCT_CH_MS_IC) ? icirq : ocirq;
 
   assign oc_match = (cc_reg == counter) && counter_changed;
 
 
   always @(posedge clk or posedge rst)
     begin
        if (rst)
          begin
             cc_reg <= `SCCT_COUNTER_CTR_WIDTH'b0;
             icoc_select <= `SCCT_CH_MS_IC;
             icoc_action <= `SCCT_IC_NONE;
             irq_enable <= 1'b0;
             icirq <= 1'b0;
             ocirq <= 1'b0;
             irq_status <= 1'b0;
             outval <= 1'b0;
             last_input_state <= 1'b0;
          end
        else
          begin
             // write
             if (icoc_select_i_wen)
               begin
                  icoc_select <= icoc_select_i;
                  // reset old irq states
                  case (icoc_select_i)
                    `SCCT_CH_MS_IC: icirq <= 0;
                    `SCCT_CH_MS_OC: ocirq <= 0;
                  endcase // case (icoc_select_i)
               end
             if (icoc_action_i_wen)
               icoc_action <= icoc_action_i;
             if (i_cc_reg_wen)
               cc_reg <= i_cc_reg;
             if (irq_enable_i_wen)
               irq_enable <= irq_enable_i;
             if ( (irq_status_i_wen) && (irq_status_i == 1) )
               begin
                  icirq <= 0;
                  ocirq <= 0;
                  irq_status <= 0;
               end
             else
               irq_status <= irq_enable ? intistat : 0;
 
             //if (force_oc_i_wen)
               //outval <= force_oc_i;
 
             if (icoc_select == `SCCT_CH_MS_OC)
               begin
                  if ( oc_match || (force_oc_i_wen && force_oc_i) )
                    begin
                       case (icoc_action)
                         `SCCT_OC_HIGH: outval = 1;
                         `SCCT_OC_LOW: outval = 0;
                         `SCCT_OC_TOGGLE: outval = !outval;
                       endcase
                       if (oc_match) ocirq <= 1;
                    end
               end // if (icoc_select == `SCCT_CH_MS_OC)
             else if (icoc_select == `SCCT_CH_MS_IC)
               begin
                  if ( (icoc_action[`SCCT_IC_POSEDGE_BIT] == 1) && (last_input_state == 0) && (pin_i == 1) )
                    begin
                       cc_reg <= counter;
                       icirq <= 1;
                    end
                  else if ( (icoc_action[`SCCT_IC_NEGEDGE_BIT] == 1) && (last_input_state == 1) && (pin_i == 0) )
                    begin
                       cc_reg <= counter;
                       icirq <= 1;
 
                    end
               end
             last_input_state = pin_i;
          end
 
     end
 
 
endmodule // channel
 
 

Line No.	Rev	Author	Line
1	2	fkluge	`// $Id: scct_channel.v 2 2015-06-15 13:52:02Z fkluge $`
2			`// Simple timer channel`
3
4			`include "scct_constants.v"
5
6			`module scct_channel (`
7			`clk, rst, counter, counter_changed,`
8			`icoc_select_i, icoc_select_i_wen,`
9			`icoc_action_i, icoc_action_i_wen,`
10			`i_cc_reg, i_cc_reg_wen,`
11			`irq_enable_i, irq_enable_i_wen,`
12			`irq_status_i, irq_status_i_wen,`
13			`force_oc_i, force_oc_i_wen,`
14			`icoc_select_o, icoc_action_o, cc_reg_o, irq_enable_o, irq_status_o,`
15			`pin_i, pin_o`
16			`);`
17
18			`input clk;`
19			`input rst;`
20			input [`SCCT_COUNTER_CTR_WIDTH-1:0] counter;
21			`input counter_changed;`
22
23			`// TODO: replace single-bit X_i, X_i_wen signals by a single signal`
24			`input icoc_select_i;`
25			`input icoc_select_i_wen;`
26			`input [1:0] icoc_action_i;`
27			`input icoc_action_i_wen;`
28			input [`SCCT_COUNTER_CTR_WIDTH-1:0] i_cc_reg;
29			`input i_cc_reg_wen;`
30			`input irq_enable_i;`
31			`input irq_enable_i_wen;`
32			`input irq_status_i; // write 1 to clear flag`
33			`input irq_status_i_wen;`
34			`input force_oc_i;`
35			`input force_oc_i_wen;`
36
37			`output icoc_select_o;`
38			`output [1:0] icoc_action_o;`
39			output [`SCCT_COUNTER_CTR_WIDTH-1:0] cc_reg_o;
40			`output irq_enable_o;`
41			`output irq_status_o;`
42			`input pin_i;`
43			`output pin_o;`
44
45			`reg outval;`
46			`reg icoc_select;`
47			`reg [1:0] icoc_action;`
48			`reg irq_enable;`
49			`reg irq_status;`
50
51			`reg icirq; // set when IC detects an edge that is interesting according to icoc_action`
52			`reg ocirq; // set when counter matches cc_reg`
53			`wire intistat;`
54
55			`// Capture/Compare Register`
56			reg [`SCCT_COUNTER_CTR_WIDTH-1:0] cc_reg;
57			`wire oc_match;`
58
59			`reg last_input_state;`
60
61
62
63
64			`assign icoc_select_o = icoc_select;`
65			`assign icoc_action_o = icoc_action;`
66			`assign cc_reg_o = cc_reg;`
67			`assign irq_enable_o = irq_enable;`
68			`assign irq_status_o = irq_status;`
69
70
71			//assign pin = (icoc_select == `SCCT_CH_MS_IC) ? 1'bz : outval;
72			`assign pin_o = outval;`
73
74
75
76			assign intistat = (icoc_select == `SCCT_CH_MS_IC) ? icirq : ocirq;
77
78			`assign oc_match = (cc_reg == counter) && counter_changed;`
79
80
81			`always @(posedge clk or posedge rst)`
82			`begin`
83			`if (rst)`
84			`begin`
85			cc_reg <= `SCCT_COUNTER_CTR_WIDTH'b0;
86			icoc_select <= `SCCT_CH_MS_IC;
87			icoc_action <= `SCCT_IC_NONE;
88			`irq_enable <= 1'b0;`
89			`icirq <= 1'b0;`
90			`ocirq <= 1'b0;`
91			`irq_status <= 1'b0;`
92			`outval <= 1'b0;`
93			`last_input_state <= 1'b0;`
94			`end`
95			`else`
96			`begin`
97			`// write`
98			`if (icoc_select_i_wen)`
99			`begin`
100			`icoc_select <= icoc_select_i;`
101			`// reset old irq states`
102			`case (icoc_select_i)`
103			`SCCT_CH_MS_IC: icirq <= 0;
104			`SCCT_CH_MS_OC: ocirq <= 0;
105			`endcase // case (icoc_select_i)`
106			`end`
107			`if (icoc_action_i_wen)`
108			`icoc_action <= icoc_action_i;`
109			`if (i_cc_reg_wen)`
110			`cc_reg <= i_cc_reg;`
111			`if (irq_enable_i_wen)`
112			`irq_enable <= irq_enable_i;`
113			`if ( (irq_status_i_wen) && (irq_status_i == 1) )`
114			`begin`
115			`icirq <= 0;`
116			`ocirq <= 0;`
117			`irq_status <= 0;`
118			`end`
119			`else`
120			`irq_status <= irq_enable ? intistat : 0;`
121
122			`//if (force_oc_i_wen)`
123			`//outval <= force_oc_i;`
124
125			if (icoc_select == `SCCT_CH_MS_OC)
126			`begin`
127			`if ( oc_match \|\| (force_oc_i_wen && force_oc_i) )`
128			`begin`
129			`case (icoc_action)`
130			`SCCT_OC_HIGH: outval = 1;
131			`SCCT_OC_LOW: outval = 0;
132			`SCCT_OC_TOGGLE: outval = !outval;
133			`endcase`
134			`if (oc_match) ocirq <= 1;`
135			`end`
136			end // if (icoc_select == `SCCT_CH_MS_OC)
137			else if (icoc_select == `SCCT_CH_MS_IC)
138			`begin`
139			if ( (icoc_action[`SCCT_IC_POSEDGE_BIT] == 1) && (last_input_state == 0) && (pin_i == 1) )
140			`begin`
141			`cc_reg <= counter;`
142			`icirq <= 1;`
143			`end`
144			else if ( (icoc_action[`SCCT_IC_NEGEDGE_BIT] == 1) && (last_input_state == 1) && (pin_i == 0) )
145			`begin`
146			`cc_reg <= counter;`
147			`icirq <= 1;`
148
149			`end`
150			`end`
151			`last_input_state = pin_i;`
152			`end`
153
154			`end`
155
156
157			`endmodule // channel`
158
159

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[/] [scct/] [trunk/] [verilog/] [scct_channel.v] - Blame information for rev 2