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[/] [scct/] [trunk/] [verilog/] [scct_counter.v] - Blame information for rev 2

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// $Id: scct_counter.v 2 2015-06-15 13:52:02Z fkluge $
// simple counter
 
`include "scct_constants.v"
 
module scct_counter (
                     clk,
                     rst,
                     counter,
                     counter_changed,
                     irq_enable_i, irq_enable_i_wen,
                     irq_status_i, irq_status_i_wen,
                     prescaler_i, prescaler_i_wen,
                     irq_enable_o,
                     irq_status_o,
                     prescaler_o
                     );
 
   input         clk;
   input         rst;
   output [`SCCT_COUNTER_CTR_WIDTH-1:0] counter;
   // TODO: replace single-bit X_i, X_i_wen signals by a single signal
   input                                irq_enable_i;
   input                                irq_enable_i_wen;
   input                                irq_status_i;
   input                                irq_status_i_wen;
   input [`SCCT_COUNTER_PSC_WIDTH-1:0]   prescaler_i;
   input                                prescaler_i_wen;
   output                               irq_enable_o;
   output                               irq_status_o;
   output [`SCCT_COUNTER_PSC_WIDTH-1:0] prescaler_o;
   output                               counter_changed;
 
 
   // The actual counter register is 1 bit wider to account for overflows
   reg [`SCCT_COUNTER_CTR_WIDTH:0]       my_counter;
   // this signals is set to 1 when the counter value has changed. After one cycle it is reset to 0
   reg                                  counter_changed;
 
   reg [`SCCT_COUNTER_PSC_WIDTH-1:0]     prescaler;
   reg [`SCCT_COUNTER_PSC_WIDTH-1:0]     prescaler_shadow; // used for actual prescaling
   reg [`SCCT_COUNTER_PSC_WIDTH-1:0]     prescaler_count;
   reg                                  irq_enable;
   reg                                  irq_status;
 
   wire                                 prescaler_match;
   wire                                 counter_overflow;
 
 
   assign prescaler_match = (prescaler_count == prescaler_shadow);
   assign counter[`SCCT_COUNTER_CTR_WIDTH-1:0] = my_counter[`SCCT_COUNTER_CTR_WIDTH-1:0];
   assign counter_overflow = my_counter[`SCCT_COUNTER_CTR_OV_BIT];
   assign prescaler_o = prescaler;
   //assign irq_status_o = irq_enable ? irq_status : 0;
   assign irq_status_o = irq_status;
 
   // writing to registers
   always @(posedge clk or posedge rst)
     begin
        if (rst)
          begin
          end
        else
          begin
          end // else: !if(rst)
     end // always @ (posedge clock or psedge reset_n)
 
 
   // counter operation
   always @(posedge clk or posedge rst)
     begin
        if(rst)
          begin
             prescaler_shadow <= `SCCT_COUNTER_PSC_WIDTH'b0;
             prescaler_count <= `SCCT_COUNTER_PSC_WIDTH'b0;
             my_counter <= 0;
             irq_status <= 0;
             prescaler <= `SCCT_COUNTER_PSC_WIDTH'b0;
             irq_enable <= 0;
             counter_changed <= 0;
          end // if (rst)
        else
          begin
             prescaler_count <= prescaler_count + 1;
 
             if (prescaler_match)
               begin
                  my_counter <= my_counter + 1;
                  prescaler_count <= `SCCT_COUNTER_PSC_WIDTH'b0;
                  prescaler_shadow <= prescaler;
                  counter_changed <= 1;
               end
             else
               begin
                  counter_changed <= 0;
               end // else: !if(prescaler_match)
 
 
             if (counter_overflow)
               begin
                  my_counter[`SCCT_COUNTER_CTR_OV_BIT] <= 0;
                  irq_status <= irq_enable ? 1 : 0;
               end
             // write requests
             if (irq_enable_i_wen)
               irq_enable <= irq_enable_i;
 
             // if an overflow occurs in the same cycle as the reset request
             // for irq_status, ignore the reset.
             if ( (irq_status_i_wen) && (irq_status_i == 1) && (!counter_overflow))
               begin
                  irq_status <= 0;
               end
             if (prescaler_i_wen)
               prescaler <= prescaler_i;
          end // else: !if(rst)
     end // always @ (posedge clk or posedge rst)
 
endmodule // counter

Line No.	Rev	Author	Line
1	2	fkluge	`// $Id: scct_counter.v 2 2015-06-15 13:52:02Z fkluge $`
2			`// simple counter`
3
4			`include "scct_constants.v"
5
6			`module scct_counter (`
7			`clk,`
8			`rst,`
9			`counter,`
10			`counter_changed,`
11			`irq_enable_i, irq_enable_i_wen,`
12			`irq_status_i, irq_status_i_wen,`
13			`prescaler_i, prescaler_i_wen,`
14			`irq_enable_o,`
15			`irq_status_o,`
16			`prescaler_o`
17			`);`
18
19			`input clk;`
20			`input rst;`
21			output [`SCCT_COUNTER_CTR_WIDTH-1:0] counter;
22			`// TODO: replace single-bit X_i, X_i_wen signals by a single signal`
23			`input irq_enable_i;`
24			`input irq_enable_i_wen;`
25			`input irq_status_i;`
26			`input irq_status_i_wen;`
27			input [`SCCT_COUNTER_PSC_WIDTH-1:0] prescaler_i;
28			`input prescaler_i_wen;`
29			`output irq_enable_o;`
30			`output irq_status_o;`
31			output [`SCCT_COUNTER_PSC_WIDTH-1:0] prescaler_o;
32			`output counter_changed;`
33
34
35			`// The actual counter register is 1 bit wider to account for overflows`
36			reg [`SCCT_COUNTER_CTR_WIDTH:0] my_counter;
37			`// this signals is set to 1 when the counter value has changed. After one cycle it is reset to 0`
38			`reg counter_changed;`
39
40			reg [`SCCT_COUNTER_PSC_WIDTH-1:0] prescaler;
41			reg [`SCCT_COUNTER_PSC_WIDTH-1:0] prescaler_shadow; // used for actual prescaling
42			reg [`SCCT_COUNTER_PSC_WIDTH-1:0] prescaler_count;
43			`reg irq_enable;`
44			`reg irq_status;`
45
46			`wire prescaler_match;`
47			`wire counter_overflow;`
48
49
50			`assign prescaler_match = (prescaler_count == prescaler_shadow);`
51			assign counter[`SCCT_COUNTER_CTR_WIDTH-1:0] = my_counter[`SCCT_COUNTER_CTR_WIDTH-1:0];
52			assign counter_overflow = my_counter[`SCCT_COUNTER_CTR_OV_BIT];
53			`assign prescaler_o = prescaler;`
54			`//assign irq_status_o = irq_enable ? irq_status : 0;`
55			`assign irq_status_o = irq_status;`
56
57			`// writing to registers`
58			`always @(posedge clk or posedge rst)`
59			`begin`
60			`if (rst)`
61			`begin`
62			`end`
63			`else`
64			`begin`
65			`end // else: !if(rst)`
66			`end // always @ (posedge clock or psedge reset_n)`
67
68
69			`// counter operation`
70			`always @(posedge clk or posedge rst)`
71			`begin`
72			`if(rst)`
73			`begin`
74			prescaler_shadow <= `SCCT_COUNTER_PSC_WIDTH'b0;
75			prescaler_count <= `SCCT_COUNTER_PSC_WIDTH'b0;
76			`my_counter <= 0;`
77			`irq_status <= 0;`
78			prescaler <= `SCCT_COUNTER_PSC_WIDTH'b0;
79			`irq_enable <= 0;`
80			`counter_changed <= 0;`
81			`end // if (rst)`
82			`else`
83			`begin`
84			`prescaler_count <= prescaler_count + 1;`
85
86			`if (prescaler_match)`
87			`begin`
88			`my_counter <= my_counter + 1;`
89			prescaler_count <= `SCCT_COUNTER_PSC_WIDTH'b0;
90			`prescaler_shadow <= prescaler;`
91			`counter_changed <= 1;`
92			`end`
93			`else`
94			`begin`
95			`counter_changed <= 0;`
96			`end // else: !if(prescaler_match)`
97
98
99			`if (counter_overflow)`
100			`begin`
101			my_counter[`SCCT_COUNTER_CTR_OV_BIT] <= 0;
102			`irq_status <= irq_enable ? 1 : 0;`
103			`end`
104			`// write requests`
105			`if (irq_enable_i_wen)`
106			`irq_enable <= irq_enable_i;`
107
108			`// if an overflow occurs in the same cycle as the reset request`
109			`// for irq_status, ignore the reset.`
110			`if ( (irq_status_i_wen) && (irq_status_i == 1) && (!counter_overflow))`
111			`begin`
112			`irq_status <= 0;`
113			`end`
114			`if (prescaler_i_wen)`
115			`prescaler <= prescaler_i;`
116			`end // else: !if(rst)`
117			`end // always @ (posedge clk or posedge rst)`
118
119			`endmodule // counter`

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[/] [scct/] [trunk/] [verilog/] [scct_counter.v] - Blame information for rev 2