Subversion Repositories sd_mmc_emulator

--------------------------------------------------------------------------

--------------------------------------------------------------------------

-- Package containing SD Card interface modules,

-- and related support modules.

--

-- 15-Aug-2017 RMR Backdoor opcodes not needed, SPI debugger still at 3000040

-- xx-Jun-2017 RMR Changed SPI debugger to 'w 03000040' so backdoor opcode could use 3000030 

-- 31-Mar-2017 RMR Added SPI debug capability to 'w 03000030'

--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

library work;

use work.sd_card_pack.all;

use work.sd_host_pack.all;

package mmc_test_pack is

  component mmc_test_cmd_rx

  port(

    -- Asynchronous reset

    sys_rst_n   : in  std_logic;

    -- SD/MMC card command signals

    sd_clk_i    : in  std_logic;

    sd_cmd_i    : in  std_logic;

    -- Command outputs

    cmd_raw_o   : out unsigned(47 downto 0);

    -- Status and done indicator

    cmd_done_o  : out std_logic;

    crc_err_o   : out std_logic;

    stop_err_o  : out std_logic

  );

  end component;

  component mmc_tester

  generic (

    SYS_CLK_RATE        : real; -- The clock rate at which the FPGA runs

    SYS_LEDS            : natural; -- Number of LED outputs on the board

    SYS_SWITCHES        : natural; -- Number of Switch inputs on the board

    EXT_CSD_INIT_FILE   : string; -- Initial contents of EXT_CSD

    HOST_RAM_ADR_BITS   : natural; -- Determines amount of BRAM in MMC host

    MMC_FIFO_DEPTH      : integer;

    MMC_FILL_LEVEL_BITS : integer; -- Should be at least int(floor(log2(FIFO_DEPTH))+1.0)

    RSP_FILL_LEVEL_BITS : integer;

    MMC_RAM_ADR_BITS    : integer

  );

  port (

    -- Asynchronous reset

    sys_rst_n      : in  std_logic;

    sys_clk        : in  std_logic;

    -- Asynchronous serial interface

    cmd_i          : in  std_logic;

    resp_o         : out std_logic;

    -- Board related

    switch_i       : in  unsigned(SYS_SWITCHES-1 downto 0);

    led_o          : out unsigned(SYS_LEDS-1 downto 0);

    -- Interface for SD/MMC traffic logging

    -- via asynchronous serial transmission

    tlm_send_i     : in  std_logic;

    tlm_o          : out std_logic;

    -- Tester Function Enables

    slave_en_i     : in  std_logic; -- OR with register bit

    host_en_i      : in  std_logic; -- OR with register bit

    -- SD/MMC card signals

    mmc_clk_i      : in  std_logic;

    mmc_clk_o      : out std_logic;

    mmc_clk_oe_o   : out std_logic;

    mmc_cmd_i      : in  std_logic;

    mmc_cmd_o      : out std_logic;

    mmc_cmd_oe_o   : out std_logic;

    mmc_dat_i      : in  unsigned(7 downto 0);

    mmc_dat_o      : out unsigned(7 downto 0);

    mmc_dat_oe_o   : out std_logic;

    mmc_od_mode_o  : out std_logic; -- Open drain mode

    mmc_dat_siz_o  : out unsigned(1 downto 0);

    dbg_spi_data0_o     : out unsigned(7 downto 0);

    dbg_spi_data1_o     : out unsigned(7 downto 0);

    dbg_spi_data2_o     : out unsigned(7 downto 0);

    dbg_spi_data3_o     : out unsigned(7 downto 0);

    dbg_spi_data4_o     : out unsigned(7 downto 0);

    dbg_spi_data5_o     : out unsigned(7 downto 0);

    dbg_spi_data6_o     : out unsigned(7 downto 0);

    dbg_spi_data7_o     : out unsigned(7 downto 0);

    dbg_spi_data8_o     : out unsigned(7 downto 0);

    dbg_spi_data9_o     : out unsigned(7 downto 0);

    dbg_spi_dataA_o     : out unsigned(7 downto 0);

    dbg_spi_dataB_o     : out unsigned(7 downto 0);

    dbg_spi_dataC_o     : out unsigned(7 downto 0);

    dbg_spi_dataD_o     : out unsigned(7 downto 0);

    dbg_spi_bytes_io    : inout unsigned(3 downto 0); --bytes to send

    dbg_spi_start_o     : out std_logic;

    dbg_spi_device_o    : out unsigned(2 downto 0); --1=VGA, 2=SYN, 3=DDS, 4=ZMON

    dbg_spi_busy_i      : in  std_logic;

    dbg_enables_o       : out unsigned(15 downto 0);  --toggle various enables/wires

    ------ Connect MMC fifos to opcode processor ----------

    -- Read from MMC fifo connections

    opc_fif_dat_o       : out unsigned( 7 downto 0);    -- MMC opcode fifo

    opc_fif_ren_i       : in  std_logic;                -- mmc fifo read enable

    opc_fif_mt_o        : out std_logic;                -- mmc opcode fifo empty

    opc_rd_cnt_o        : out unsigned(MMC_FILL_LEVEL_BITS-1 downto 0); -- mmc opcode fifo fill level 

    opc_rd_reset_i      : in  std_logic;                -- Synchronous mmc opcode fifo reset

    -- Write to MMC fifo connections

    opc_rspf_dat_i      : in  unsigned( 7 downto 0);    -- MMC response fifo

    opc_rspf_we_i       : in  std_logic;                -- response fifo write line             

    opc_rspf_mt_o       : out std_logic;                -- response fifo empty

    opc_rspf_fl_o       : out std_logic;                -- response fifo full

    opc_rspf_reset_i    : in std_logic;                 -- Synchronous mmc response fifo reset

    opc_rspf_cnt_o      : out unsigned(MMC_FILL_LEVEL_BITS-1 downto 0); -- mmc response fifo fill level 

    -- UART debugger can show these values

    opc_oc_cnt_i        : in  unsigned(31 downto 0);    -- count of opcodes processed

    opc_status1_i       : in  unsigned(31 downto 0);    -- LS 16 bits=opc status, MS 16-bits=opc_state

    opc_status2_i       : in  unsigned(31 downto 0);    -- rsp_fifo_count__opc_fifo_count    

    opc_status3_i       : in  unsigned(31 downto 0);    -- LS 16 bits=MS 8 bits=RSP fifo level, LS 8 bits=OPC fifo level

    sys_status4_i       : in  unsigned(31 downto 0);    -- system frequency setting in Hertz

    sys_status5_i       : in  unsigned(31 downto 0);    -- MS 16 bits=SYN_STAT pin,1=PLL_LOCK, 0=not, LS 12 bits=system power, dBm x 10

    sys_status6_i       : in  unsigned(31 downto 0)     -- LS 16 bits: PTN_Status__PTN_Busy(running) 

  );

  end component;

end mmc_test_pack;

package body mmc_test_pack is

end mmc_test_pack;

-------------------------------------------------------------------------------

-- SD/MMC Testing Command Receiver

-------------------------------------------------------------------------------

--

-- Author: John Clayton

-- Update: July 29, 2016 Copied code from sd_card_cmd_rx, and modified

--                       the description and interface to better suit

--                       test needs, e.g. capturing commands and replies

--                       on an SD/MMC bus.

--

-- Description

-------------------------------------------------------------------------------

-- This module is meant to be part of a system that tests, or snoops on

-- an SD/MMC card.

--

-- This module clocks incoming serial bits from the cmd signal into a 48 bit

-- shift register.  It starts when a '0' (start) bit is found, and then shifts

-- in 47 additional bits.  The expected format of the command is:

--

-- 0 x [index] [arg] [crc] 1

--

-- Where:

--   x     = direction bit. '1'=host to card, '0'=reply from card.

--   index = 6 bits

--   arg   = 32 bits

--   crc   = 7  bits

--

-- The test command receiver checks that the last bit is a '1' (stop) bit,

-- in the expected position (bit 47; start bit is bit 0).

-- The seven bits immediately prior to the stop bit are

-- checked using a CRC-7 code.

--

-- If any of the checks does not pass, the associated error bits are set.

-- Regardless of errors, however, the received data bits are presented

-- at the cmd_raw_o output.  The cmd_rx_done_o output is pulsed high for

-- one clock cycle to notify the downstream entities that newly received

-- data is available.

--

-- In the interest of simplicity and in an effort to remain practical,

-- only 48 bit responses are captured correctly by this unit.  For R2

-- responses, which are 136 bits long, only the first 48 bits are presented.

-- Because the R2 type responses are 136 bits long, specific logic is

-- included to try and detect them, and prevent errors from being flagged

-- by their occurrence.  The first eight bits of an R2 response are

-- "00111111".  Unfortunately, the first eight bits of a 48 bit R3

-- response are also "00111111".  Fortunately, the CRC field of an R3

-- response is always set to "1111111".  So, the logic checks for these

-- conditions and behaves accordingly.  In the case of an R2 response, that

-- includes ignoring further activity on the command line for another 88

-- clocks after the initial 48 bits are received...

--

-- Note that this receiver runs entirely within the sd_clk_i clock domain.

-- Therefore, care must be taken when using the outputs.  A FIFO can form

-- a natural "clock domain boundary crossing" or the user may need to

-- implement other special handshaking to safely transfer signals into a

-- different clock domain.

--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

library work;

use work.ucrc_pack.all;

entity mmc_test_cmd_rx is

  port (

    -- Asynchronous reset

    sys_rst_n   : in  std_logic;

    -- SD/MMC card command signals

    sd_clk_i    : in  std_logic;

    sd_cmd_i    : in  std_logic;

    -- Command outputs

    cmd_raw_o   : out unsigned(47 downto 0);

    -- Status and done indicator

    cmd_done_o  : out std_logic;

    crc_err_o   : out std_logic;

    stop_err_o  : out std_logic

  );

end mmc_test_cmd_rx;

architecture beh of mmc_test_cmd_rx is

  -- CRC related

signal crc_clk        : std_logic;

signal crc_clr        : std_logic;

signal crc_match      : std_logic;

signal crc_val        : unsigned(6 downto 0);

  -- Related to the incoming command

signal sd_cmd_r1      : std_logic;

signal counter        : unsigned(5 downto 0);

signal rx_sr          : unsigned(47 downto 0);

signal cmd_raw_l      : unsigned(47 downto 0);

signal ignore_counter : unsigned(6 downto 0);

begin

--------------------------------------------

-- CRC generator

  crc0 : ucrc_ser

  generic map (

    POLYNOMIAL => "0001001",

    INIT_VALUE => "0000000"

  )

  port map (

    -- System clock and asynchronous reset

    sys_clk    => crc_clk,

    sys_rst_n  => sys_rst_n,

    sys_clk_en => '1',

    -- Input and Control

    clear_i    => crc_clr,

    data_i     => rx_sr(0),

    flush_i    => '0',

    -- Output

    match_o    => crc_match,

    crc_o      => crc_val

  );

  -- Falling edge was used for a while...

  -- Rising edge is now being used, per the specification.

  --crc_clk <= not sd_clk_i;

  crc_clk <= sd_clk_i;

  crc_clr <= '1' when counter=0 else '0';

--------------------------------------------

-- Command receiver

command_rx_proc : process(sys_rst_n, sd_clk_i)

begin

  if (sys_rst_n='0') then

    ignore_counter <= (others=>'0');

    counter <= (others=>'0');

    rx_sr <= (others=>'0');

    sd_cmd_r1 <= '1';

    cmd_raw_l <= (others=>'1');

    cmd_done_o  <= '0';

    crc_err_o   <= '0';

    stop_err_o  <= '0';

--  elsif (sd_clk_i'event and sd_clk_i='0') then -- falling edge is used, when data is stable.

  elsif (sd_clk_i'event and sd_clk_i='1') then -- rising edge is used, per the specification.

    -- Default values

    cmd_done_o  <= '0';

    crc_err_o   <= '0';

    stop_err_o  <= '0';

    -- Metastability mitigation (synchronization) flip flops

    sd_cmd_r1 <= sd_cmd_i;

    -- The shift register is the second synchronization flip flop

    rx_sr(0)  <= sd_cmd_r1;

    rx_sr(47 downto 1) <= rx_sr(46 downto 0);

    -- Decrement the counter when it is non-zero

    if (counter>0) then

      counter <= counter-1;

    end if;

    -- Decrement the ignore counter when it is non-zero

    if (ignore_counter>0) then

      ignore_counter <= ignore_counter-1;

    end if;

    -- Load the counter when a start bit is seen

    if (ignore_counter=0 and counter=0 and sd_cmd_r1='0') then

      counter <= to_unsigned(48,counter'length);

    end if;

    -- Store the output when the counter is expiring

    if (counter=1) then

      cmd_raw_l <= rx_sr;

      cmd_done_o <= '1';

      -- Determine if this is a long R2 type response

      if (rx_sr(47 downto 40)="00111111" and rx_sr(7 downto 1)/="1111111") then

        ignore_counter <= to_unsigned(88,ignore_counter'length);

        -- No errors are generated for long R2 responses

      else

        -- Perform error checks

        if (rx_sr(0)='0') then

          stop_err_o <= '1';

        end if;

        if (crc_match='0') then

          crc_err_o <= '1';

        end if;

      end if;

    end if;

  end if;

end process;

-- Split out fields of the command

cmd_raw_o   <= cmd_raw_l;

end beh;

---------------------------------------------------------------------------------------

--

-- Author: John Clayton

-- Date  : May 16, 2016

-- Update: 05/16/16 Wrote the description, began writing code

--

-- Description

---------------------------------------------------------------------------------------

-- This is a collection of modules put together which allow testing of an MMC system.

-- In particular, this module contains an MMC host, plus an "MMC data pipe" which

-- impersonates an MMC.  

--

-- In order to interact with this collection of MMC modules in hardware, an 

-- "async_syscon" serial terminal command interpreter is provided, having a 32-bit

-- address and a 32-bit data bus.  There is an automatic baud rate synchronization

-- unit, which synchronizes by looking for the 0x0D character, so that simply

-- pressing "Enter" in a serial terminal program should bring up the link at the

-- correct speed, anything in the range 19200 to 921600 Baud should work.

-- The parity setting is "None" and hardware handshaking is not supported.

--

-- Because of the different modules present in this MMC tester, it is helpful to

-- summarize the memory map here:

--

-- Address          Length     Function

-- --------------   --------   --------------------------------------------

-- 0x0300_0000      0x10       MMC host registers

-- 0x0300_0010      0x10       MMC slave registers

-- 0x0300_0020      0x10       MMC tester registers

-- 0x0400_0000      0x4000     MMC host RAM

-- 0x0500_0000      0x10000    MMC slave RAM

--

-- Note that the size of the MMC slave RAM can be modified by setting the

-- constant MMC_RAM_ADR_BITS within this module.  Similarly, the size of the

-- MMC host RAM can be modified by setting the constant HOST_RAM_ADR_BITS.

--

-- For a description of the MMC host registers, please refer to the

-- description given in the sd_controller_8bit_bram entity.

-- The code is contained in the "sd_host_pack.vhd" file.

--

-- For a description of the MMC slave registers, please refer to the

-- description given in the sd_card_emulator, which is an entity instantiated

-- inside the mmc_data_pipe unit.

-- The code is contained in the "sd_card_pack.vhd" file.

--

-- A detailed description of the local registers is given here, below.

--

-- Wouldn't it be nice to have a block diagram showing all of the modules

-- or cores instantiated within this one?  Yes, I believe it would be nice.

-- However, in lieu of a nice ASCII-art pictorial drawing, a few lines of

-- descriptive text will be better than nothing.  Here goes!

------------------------------------------------------------------------------

-- Brief Description of local test functions:

--

--   Within this unit, there is steering logic that selects how the SD/MMC bus

--   is driven and used, with regard to the tri-state output enables.  Actual

--   tri-state buffers are to be implemented at the top level of the FPGA

--   by means of the output enable signals.

--

--   The steering logic allows the SD/MMC host to communicate directly with

--   the sd_card_emulator and RAM/FIFOs contained in the mmc_data_pipe, or it

--   can also be set up to route the signals from the MMC controller host to

--   an external SD/MMC card.

--

--   In like manner, it can be set up so that an external SD/MMC host can talk

--   to the local mmc_data_pipe unit.

--

--   A third option is to disable both the local sd_controller_8bit_bram

--   and the local mmc_data_pipe unit from the bus.  In this configuration,

--   the user of this MMC tester is enabled to "snoop" on the activity and

--   traffic occurring between an external SD/MMC host and its attached card.

--   This requires, of course, some appropriate "interposer" cabling to give

--   the FPGA access to monitor the signals passing along the external SD/MMC

--   bus being monitored.

--

--   In order to keep track of commands on the SD/MMC bus for test and debug,

--   there is a dedicated, stand alone command receiver separate from the MMC

--   host and slave units.  This receiver looks for start bits on the SD/MMC

--   cmd line, and then captures the contents of the transfer, whether it be

--   from the host to the card, or a cmd response from the card to the host.

--   Some responses from an SD/MMC card are 136 bits long, but most responses

--   are 48 bits long.  In the interest of expediency, this special receiver

--   only captures the first 48 bits of a command transfer.  It does, however,

--   refrain from generating error flags for 136 bit long responses, by

--   checking the command index field, which is "111111b" for 136 bit long

--   responses.

--

--   For test and debug purposes, there are some counters, and data capture

--   mechanisms:

--

--     1. A counter that counts command transfer events, filtered based on

--        register settings.

--     2. A data transfer counter, which simply increments each time a data

--        transfer is started.  It is reset whenever a new host to card

--        command transfer of the selected command index type is detected.

--        In reality there are two such counters, a 32 bit one that is

--        accessible via registers, and an 8-bit one ("tlm_d_count") that is

--        used in the telemetry output.  The telemetry one is a relative

--        count; it gets cleared at every command transfer event.

--     3. An SD/MMC traffic reporting "telemetry sender" that emits a stream

--        of information meant to be used as a timestamped archive record

--        of SD/MMC activity.  A new record is emitted each time the command

--        transfer counter increments.  The telemetry records are 12 byte

--        bursts meant to be captured in a FIFO external to this module, or

--        sent out via a UART.

--

--   The format of the telemetry record burst is:

--      Byte Number     Contents       Purpose

--      -----------     --------       -----------------------------------------

--           0          0xEB           Synchronization character

--           1          frame ID       A modulo-256 incrementing value

--           2          tlm_d_count    Data transfers completed, modulo 256

--          3-5         time           time, in microseconds

--          6-11        cmd            48 bits of command or reply

--

------------------------------------------------------------------------------

-- Local Registers

--

-- 0x0300_0020  R0   LED outputs register (READ/WRITE)

--                   This register contains a number of bits meant for

--                   controlling LEDs on the test board, just for fun.  The

--                   number of bits implemented in this register is set by

--                   the SYS_LEDS generic, which should be set in the range

--                   [1..32].  For SYS_LEDS settings less than 32, the unused

--                   bits are the most significant bits, which read as '0'.

--

-- 0x0300_0021  R1   Switch inputs register (READ ONLY)

--                   This register allows reading the status of the switch_i

--                   inputs on the test board.  The number of bits implemented

--                   in this register is set by the SYS_SWITCHES generic,

--                   which should be set in the range [1..32].  For

--                   SYS_SWITCHES settings less than 32, the unused bits are

--                   the most significant bits, which read as '0'.

--

-- 0x0300_0022  R2   MMC Tester Mode (READ/WRITE)

--                   Bit [0] = Slave Enable Reg.  Setting this bit causes the

--                             internal MMC_data_pipe slave to be active

--                             on the SD/MMC bus.

--                   Bit [1] = Host Enable Reg.  Setting this bit causes the

--                             internal sd_controller_8bit_bram unit to

--                             be active on the SD/MMC bus.

--                   Bits [3..2] = "00" (Reserved)

--                   Bit [4] = Slave Enabled (READ ONLY).  This bit is the

--                             logical OR of bit[0] and the slave_en_i input.

--                             Thus we see that the MMC_data_pipe slave can

--                             be made active by the signal input, or the

--                             register bit.

--                   Bit [5] = Host Enabled (READ ONLY).  This bit is the

--                             logical OR of bit[1] and the host_en_i input.

--                             Thus we see that the sd_controller_8bit_bram

--                             host unit can be made active by the signal

--                             input, or the register bit.

--                   Bits [7..6] = "00" (Reserved)

--                   Bit [8] = Telemetry log register read access enable.

--                             When this bit is set, then telemetry log

--                             FIFO contents can be read out via register

--                             R10, and the asynchronous serial transmitter

--                             is disabled.  When clear, the asynchronous

--                             serial transmitter has access to the telemetry

--                             log FIFO instead of register R10.

--

-- 0x0300_0023  R3   Test Command Receiver Filter (READ/WRITE)

--                   Bits [7:0] determine what type of command creates a

--                   "command event."

--                   Except for the setting of 0x80, setting bit [7] means

--                   "capture and count everything," including all command

--                   indices, in both directions.

--                   Example settings:

--                     0x81..0xFF => Capture and count everything.

--                     0x80 => Capture and count nothing. Nada. Zilch.

--                     0x7F => Capture and count all host-to-card commands

--                     0x3F => Capture and count all card-to-host responses

--                     0x59 => Capture and count CMD25 from host-to-card only

--                     0x28 => Capture and count CMD40 R5 responses only

--                     0x27 => Capture and count CMD39 R4 responses only

--                     0x19 => Capture and count CMD25 R1 responses only

--                     0x00 => Capture and count CMD0 R1 responses only

--

--   To explain more clearly how these filter settings work, it is helpful to

--   recall that the first eight bits of the command or response are:

--

--     [0][d][cccccc]

--

--     Where: 0 = start bit (always low)

--            d = direction bit (1 for host to card, 0 for card response)

--            cccccc = command index, ranging from 0 to 56, (or 63 for

--                     long responses and/or 48-bit R3 OCR responses.)

--

--     Therefore, it becomes clear that the operation of the filter is

--     not perfect.  For example, there is no way to act on only R3

--     responses.  However, there is really no need for a perfect

--     filter.  This one is, well, you know, good enough!

--

-- 0x0300_0024  R4   Error-free Command Events (READ/WRITE)

--                   Writing to this register resets it back to zero.

--

-- 0x0300_0025  R5   Command Events with CRC error (READ/WRITE)

--                   Writing to this register resets it back to zero.

--

-- 0x0300_0026  R6   Command Events with stop bit error (READ/WRITE)

--                   Writing to this register resets it back to zero.

--

-- 0x0300_0027  R7   Number of data transfers completed(READ/WRITE)

--                   No means are provided for the tester to determine

--                   what direction the data is flowing over the SD/MMC

--                   data lines.  Therefore, this register simply contains

--                   the total number of transfers started in both

--                   directions.  Writing to this register clears the count

--                   back to zero.  Note that this 32-bit counter is distinct

--                   from the eight bit "tlm_d_count" data transfer counter

--                   in the telemetry, which is a relative count, cleared at

--                   every command transfer event.

--

-- 0x0300_0028  R8   reg_dbus_size (READ/WRITE)

--                     0 => 1 bit data bus transfers

--                     1 => 4 bit data bus transfers

--                     2 => 8 bit data bus transfers

--                   In order for the tester to determine when a data transfer

--                   is completed, so that it can count valid start bits, it

--                   is required to know the data bus size.  Logic is present

--                   to decode when a host-to-card command of index 6 (CMD6),

--                   the SWITCH command, is seen with an argument 0x03B70s00,

--                   where s contains the new data bus size.  This 2-bit

--                   setting is then stored in the reg_dbus_size register,

--                   and used to set the "dstart_wait" parameter used for

--                   ignoring data bus activity during an active data

--                   transfer.  The reg_dbus_size starts out at "00b", and

--                   is expected to change to "01b" for 4-bit SD activity,

--                   and to "10b" for 8-bit MMC activity.

--                   Writing to this register simply clears it back to zero.

--

-- 0x0300_0029  R9   SD/MMC traffic log FIFO fill level (READ/WRITE)

--                   This register returns the number of bytes stored in the

--                   FIFO, awaiting commission to the log archive or telemetry

--                   link.  Writing to this register clears out the FIFO.

--

-- 0x0300_002A  R10  SD/MMC traffic log FIFO read port (READ ONLY)

--                   Telemetry bytes can be read out of the traffic log FIFO

--                   whenever enabled in R2 bit 8.  For convenience in reading

--                   the data, the bytes are packed into 32-bit words.  If R2

--                   bit 8 is clear, then reading this register returns

--                   0x55555555.

--

-- 0x0300_002C  R12  S4 Enables/lines

--

-- 0x0300_002D  R13  MMC_data_pipe write data FIFO fill level (READ/WRITE)

--                   Reading this register returns the number of bytes in

--                   the MMC slave write data FIFO.  The FIFO holds data

--                   that are meant to flow from the MMC slave to the host.

--                   Writing to this register clears the MMC slave

--                   write data FIFO.

--

-- 0x0300_002E  R14  MMC_data_pipe read data FIFO fill level (READ/WRITE)

--                   Reading this register returns the number of bytes in

--                   the MMC slave read data FIFO.  The FIFO holds data

--                   that have been sent from the host to the MMC slave.

--                   Writing to this register clears the MMC slave

--                   read data FIFO.

--

-- 0x0300_002F  R15  MMC_data_pipe FIFO data (READ/WRITE)

--                   Writing to this address loads another byte into

--                   the MMC slave write data FIFO, thereby enqueueing

--                   it to be read by the host from the MMC slave.

--                   However, if the write data FIFO is full, then nothing

--                   happens, and the byte is thrown into the "bit bucket."

--                   Reading from this address removes another byte

--                   of data from the MMC slave read data FIFO, which

--                   was previously delivered from the host to the

--                   MMC slave.

--                   However, if the read data FIFO is empty, then no valid

--                   data is actually delivered.

--

-- 0x0300_0030  R16  Rd:Opcode processor status, 8 lsbs, Wr:SPI data, device, #bytes, 14 bytes data

--

-- 0x3000_0031  R17  Opcode processor opcode counter, 32 bits

--

-- 0x3000_0032  R18  Opcode processor internal state, 8 bits

--

-- 0x3000_0033  R19  Opcode processor overall system state, 16 bits

--

-- 0x3000_0034  R20  Opcode processor overall system mode, 32 bits

--

-- 0x3000_0035  R21  Frequency processor status, 16 msbs, power processor status, 16 lsbs

--

-- 0x3000_0036  R22  Phase processor status, 16 msbs, pulse processor status, 16 lsbs

--

-- 0x3000_0037  R23  Pattern processor status, 16 msbs, opc_response_ready flag, 16 lsbs 

--

------------------------------------------------------------------------------

-- Further Discussion, for the enquiring minds that want to know...

-- The below explanations might in some way repeat what was stated above,

-- but could still be useful.

--

-- Register 2, bit[0] : "slave enable"

--   When high, this bit causes the MMC slave to receive commands, and respond to

--   them.  When this bit is enabled, the MMC slave will drive signals onto mmc_cmd_o

--   and mmc_dat_o, including driving the mmc_cmd_oe_o and mmc_dat_oe_o lines when

--   appropriate.  When this bit is low, the MMC slave cmd input will be held high,

--   and the MMC slave will not have anything to do.

--

-- Register 2, bit[1] : "host enable"

--   When high, this bit causes the MMC host to send commands, and receive responses

--   to them.  When this bit is enabled, the MMC host can drive signals onto mmc_cmd_o

--   and mmc_dat_o, including driving the mmc_cmd_oe_o and mmc_dat_oe_o lines when

--   appropriate.  When this bit is low, the MMC host cmd output will be cut off

--   from affecting mmc_cmd_o, and the MMC host will not be able to influence the

--   MMC bus signals.

--

-- If both of these bits are low, then the only function active in this core is to

-- monitor the mmc commands which occur on the MMC bus due to the action of any

-- outside MMC hosts, such as card readers, which may send commands to an MMC card

-- on the bus.

-- Register 3 can be used to filter on a certain host command index.

--

-- With "host_enable" set, the tester can be used to communicate with a real

-- external SD/MMC device, perhaps for the purpose of reading or writing some

-- sectors, or reading the device registers including the CID, CSD and the 512

-- byte EXT_CSD.

--

-- With "slave_enable" set, on the other hand, an MMC slave can be used with an

-- external SD/MMC card reader.  The MMC slave in this case uses a small amount

-- of RAM, plus a pair of FIFO buffers.  Writing data to the card at addresses

-- below the upper boundary of the RAM, simply places the data into RAM.  Beyond

-- the RAM upper boundary, the data goes into the write FIFO.  Reading is handled

-- the same way.

--

-- An alternative to using the register bits to enable the slave and host, is to

-- use the input signals "slave_en_i" and "host_en_i".  These signals are simply

-- logically ORed with the register bits.

--

-- There are no "buried tri-states" present within this module.  Therefore, each

-- signal, or related bus of signals, has a drive signal provided to allow the

-- tri-state connections to be made at the top level.  The one for the mmc_clk

-- had to be provided because this module can both give and receive an MMC

-- clock signal.

--

-- An asynchronous system controller (async_syscon) is provided here for ease

-- of debugging by humans.  A person can access the entire memory map of this

-- tester by means of simple command line style commands, using an asynchronous

-- serial terminal.

--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

library work;

use work.dds_pack.all;

use work.fifo_pack.all;

use work.convert_pack.all;

use work.sd_card_pack.all;

use work.sd_host_pack.all;

use work.flancter_pack.all;

use work.mmc_test_pack.all;

use work.block_ram_pack.all;

use work.auto_baud_pack.all;

use work.uart_sqclk_pack.all;

use work.async_syscon_pack.all;

  entity mmc_tester is

  generic (

    SYS_CLK_RATE        : real    := 50000000.0; -- The clock rate at which the FPGA runs

    SYS_LEDS            : natural := 8; -- Number of LED outputs on the board

    SYS_SWITCHES        : natural := 4; -- Number of Switch inputs on the board

    EXT_CSD_INIT_FILE   : string  := "ext_csd_init.txt"; -- Initial contents of EXT_CSD

    HOST_RAM_ADR_BITS   : natural := 14; -- Determines amount of BRAM in MMC host

    MMC_FIFO_DEPTH      : integer := 2048;

    MMC_FILL_LEVEL_BITS : integer := 14; -- Should be at least int(floor(log2(FIFO_DEPTH))+1.0)

    RSP_FILL_LEVEL_BITS : integer := 10;

    MMC_RAM_ADR_BITS    : integer := 14  -- 16 Kilobytes

  );

  port (

    -- Asynchronous reset

    sys_rst_n      : in  std_logic;

    sys_clk        : in  std_logic;

    -- Asynchronous serial interface

    cmd_i          : in  std_logic;

    resp_o         : out std_logic;

    -- Board related

    switch_i       : in  unsigned(SYS_SWITCHES-1 downto 0);

    led_o          : out unsigned(SYS_LEDS-1 downto 0);

    -- Interface for SD/MMC traffic logging

    -- via asynchronous serial transmission

    tlm_send_i     : in  std_logic;

    tlm_o          : out std_logic;

    -- Tester Function Enables

    slave_en_i     : in  std_logic; -- OR with register bit

    host_en_i      : in  std_logic; -- OR with register bit