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[/] [sdcard_mass_storage_controller/] [trunk/] [backend/] [Actel/] [proasic3_redused.v] - Blame information for rev 13

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1 2 tac2 
/********************************************************************
2 
        Actel ProASIC3 Verilog Library
3 
        NAME: proasic3.v
4 
        DATE: Oct 31, 2006
5 
*********************************************************************/
6 
 
7 
`timescale 1 ns / 100 ps
8 
 
9 
//----------------------------------------------------------------------
10 
//---             VERILOG LIBRRAY PRIMITIVE SECTION
11 
//----------------------------------------------------------------------
12 
 
13 
 
14 
 
15 
primitive Dffpr (Q, D, CLK, CLR, PRE, E, NOTIFIER_REG);
16 
  output Q;
17 
  input  NOTIFIER_REG;
18 
  input  D, CLK, E, CLR, PRE;
19 
  reg Q;
20 
 
21 
        table
22 
 
23 
        //  D   CLK   CLR  PRE   E  NOTIFIER_REG  :   Qt  :  Qt+1
24 
 
25 
            1   (01)    1   1    0      ?         :   ?   :   1;  // clocked data
26 
 
27 
            1   (01)    1   1    x      ?         :   1   :   1;  // clocked data
28 
 
29 
 
30 
            1   (01)    1   1    x      ?         :   0   :   x;
31 
 
32 
            1   (01)    1   x    0      ?         :   ?   :   1;  // pessimism
33 
            ?    ?      1   x    ?      ?         :   1   :   1;  // pessimism
34 
 
35 
            ?    ?      1   x    ?      ?         :   0   :   x;
36 
            ?    ?      x   x    ?      ?         :   ?   :   x;
37 
            ?    ?      x   0    ?      ?         :   ?   :   x;
38 
            ?    ?      x   1    ?      ?         :   0   :   0;
39 
            ?    ?      x   1    ?      ?         :   1   :   x;
40 
            ?    ?      0   ?    ?      ?         :   ?   :   0;
41 
            ?    ?      1   0    ?      ?         :   ?   :   1;
42 
            1   (x1)    1   1    0      ?         :   1   :   1;  // reducing pessimism
43 
 
44 
            1   (0x)    1   1    0      ?         :   1   :   1;
45 
 
46 
            1   (x1)    1   1    x      ?         :   1   :   1;  // reducing pessimism
47 
 
48 
            1   (0x)    1   1    x      ?         :   1   :   1;
49 
 
50 
            ?  (?1)     1   1    1      ?         :   ?   :   -;  //no action for CE = 1
51 
            ?  (0x)     1   1    1      ?         :   ?   :   -;  //no action for CE = 1
52 
            ?   ?       ?   ?    *      ?         :   ?   :   -;
53 
            ?   (?0)    ?   ?    ?      ?         :   ?   :   -;  // ignore falling clock
54 
            ?   (1x)    ?   ?    ?      ?         :   ?   :   -;  // ignore falling clock
55 
            *    ?      ?   ?    ?      ?         :   ?   :   -;  // ignore data edges
56 
            ?   ?     (?1)  ?    ?      ?         :   ?   :   -;  // ignore the edges on
57 
            ?   ?       ?  (?1)  ?      ?         :   ?   :   -;  //       set and clear
58 
            ?   ?       ?   ?    ?      *         :   ?   :   x;
59 
 
60 
        endtable
61 
 endprimitive
62 
 
63 
 
64 
primitive UDP_MUX2 (Q, A, B, SL);
65 
output Q;
66 
input A, B, SL;
67 
 
68 
// FUNCTION :  TWO TO ONE MULTIPLEXER
69 
 
70 
    table
71 
    //  A   B   SL  :   Q
72 
 
73 
        1   1   ?   :   1 ;
74 
 
75 
 
76 
        1   ?   1   :   1 ;
77 
 
78 
        ?   0   0   :   0 ;
79 
        ?   1   0   :   1 ;
80 
 
81 
    endtable
82 
endprimitive
83 
 
84 
 
85 
 
86 
primitive UDPN_MUX2 (Q, A, B, SL);
87 
output Q;
88 
input A, B, SL;
89 
 
90 
// FUNCTION :  TWO TO ONE MULTIPLEXER
91 
 
92 
    table
93 
    //  A   B   SL  :   Q
94 
 
95 
        1   1   ?   :   0 ;
96 
 
97 
 
98 
        1   ?   1   :   0 ;
99 
 
100 
        ?   0   0   :   1 ;
101 
        ?   1   0   :   0 ;
102 
 
103 
    endtable
104 
endprimitive
105 
 
106 
 
107 
primitive UFPRB (Q, D, CP, RB, NOTIFIER_REG);
108 
 
109 
    output Q;
110 
    input  NOTIFIER_REG,
111 
           D, CP, RB;
112 
    reg    Q;
113 
 
114 
// FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
115 
//            ASYNCHRONOUS CLEAR ( Q OUTPUT UDP ).
116 
 
117 
    table
118 
    //  D   CP      RB     NOTIFIER_REG  :   Qt  :   Qt+1
119 
 
120 
        1   (01)    1         ?          :   ?   :   1;  // clocked data
121 
 
122 
 
123 
 
124 
 
125 
 
126 
        1    0      x         ?          :   0   :   0;  // pessimism
127 
        1    x    (?x)        ?          :   0   :   0;  // pessimism
128 
        1    1    (?x)        ?          :   0   :   0;  // pessimism
129 
        x    0      x         ?          :   0   :   0;  // pessimism
130 
        x    x    (?x)        ?          :   0   :   0;  // pessimism
131 
        x    1    (?x)        ?          :   0   :   0;  // pessimism
132 
        1   (x1)    1         ?          :   1   :   1;  // reducing pessimism
133 
 
134 
        1   (0x)    1         ?          :   1   :   1;
135 
 
136 
        ?   ?       0         ?          :   ?   :   0;  // asynchronous clear
137 
        ?   (?0)    ?         ?          :   ?   :   -;  // ignore falling clock
138 
        ?   (1x)    ?         ?          :   ?   :   -;  // ignore falling clock
139 
        *    ?      ?         ?          :   ?   :   -;  // ignore the edges on data
140 
        ?    ?    (?1)        ?          :   ?   :   -;  // ignore the edges on clear
141 
        ?    ?      ?         *          :   ?   :   x;
142 
    endtable
143 
endprimitive
144 
 
145 
 
146 
 
147 
 
148 
//----------------------------------------------------------------------
149 
//---             VERILOG LIBRRAY MODULES SECTION
150 
//----------------------------------------------------------------------
151 
 
152 
 
153 
 
154 
 
155 
/*--------------------------------------------------------------------
156 
 CELL NAME : AND2
157 
 CELL TYPE : comb
158 
 CELL LOGIC : Y = A & B
159 
---------------------------------------------------------------------*/
160 
 
161 
`suppress_faults
162 
`enable_portfaults
163 
`celldefine
164 
`delay_mode_path
165 
`timescale 1 ns / 100 ps
166 
 
167 
module AND2(Y,A,B);
168 
 input A,B;
169 
 output Y;
170 
 
171 
 and      U2(Y, A, B);
172 
 
173 
       specify
174 
 
175 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
176 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
177 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
178 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
179 
                specparam MacroType = "comb";
180 
 
181 
                //pin to pin path delay
182 
 
183 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
184 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
185 
   endspecify
186 
 
187 
endmodule
188 
 
189 
`endcelldefine
190 
`disable_portfaults
191 
`nosuppress_faults
192 
 
193 
 
194 
 
195 
 
196 
 
197 
/*--------------------------------------------------------------------
198 
 CELL NAME : AO1
199 
 CELL TYPE : comb
200 
 CELL LOGIC : Y = (A & B) + C
201 
---------------------------------------------------------------------*/
202 
 
203 
`suppress_faults
204 
`enable_portfaults
205 
`celldefine
206 
`delay_mode_path
207 
`timescale 1 ns / 100 ps
208 
 
209 
module AO1(Y,A,B,C);
210 
 input A,B,C;
211 
 output Y;
212 
 wire NET_0_0;
213 
 
214 
 and      U142(NET_0_0, A, B);
215 
 or       U143(Y, NET_0_0, C);
216 
 
217 
       specify
218 
 
219 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
220 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
221 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
222 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
223 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
224 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
225 
                specparam MacroType = "comb";
226 
 
227 
                //pin to pin path delay
228 
 
229 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
230 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
231 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
232 
   endspecify
233 
 
234 
endmodule
235 
 
236 
`endcelldefine
237 
`disable_portfaults
238 
`nosuppress_faults
239 
 
240 
 
241 
 
242 
/*--------------------------------------------------------------------
243 
 CELL NAME : AO1A
244 
 CELL TYPE : comb
245 
 CELL LOGIC : Y = (!A & B) + C
246 
---------------------------------------------------------------------*/
247 
 
248 
`suppress_faults
249 
`enable_portfaults
250 
`celldefine
251 
`delay_mode_path
252 
`timescale 1 ns / 100 ps
253 
 
254 
module AO1A(Y,A,B,C);
255 
 input A,B,C;
256 
 output Y;
257 
 wire NET_0_0;
258 
 
259 
 not    INV_31(A_, A);
260 
 and      U147(NET_0_0, A_, B);
261 
 or       U148(Y, NET_0_0, C);
262 
 
263 
       specify
264 
 
265 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
266 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
267 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
268 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
269 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
270 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
271 
                specparam MacroType = "comb";
272 
 
273 
                //pin to pin path delay
274 
 
275 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
276 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
277 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
278 
   endspecify
279 
 
280 
endmodule
281 
 
282 
`endcelldefine
283 
`disable_portfaults
284 
`nosuppress_faults
285 
 
286 
 
287 
/*--------------------------------------------------------------------
288 
 CELL NAME : AO1B
289 
 CELL TYPE : comb
290 
 CELL LOGIC : Y = (A & B) + !C
291 
---------------------------------------------------------------------*/
292 
 
293 
`suppress_faults
294 
`enable_portfaults
295 
`celldefine
296 
`delay_mode_path
297 
`timescale 1 ns / 100 ps
298 
 
299 
module AO1B(Y,A,B,C);
300 
 input A,B,C;
301 
 output Y;
302 
 wire NET_0_0;
303 
 
304 
 not    INV_32(C_, C);
305 
 and      U152(NET_0_0, A, B);
306 
 or       U153(Y, NET_0_0, C_);
307 
 
308 
       specify
309 
 
310 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
311 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
312 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
313 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
314 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
315 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
316 
                specparam MacroType = "comb";
317 
 
318 
                //pin to pin path delay
319 
 
320 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
321 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
322 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
323 
   endspecify
324 
 
325 
endmodule
326 
 
327 
`endcelldefine
328 
`disable_portfaults
329 
`nosuppress_faults
330 
 
331 
 
332 
 
333 
/*--------------------------------------------------------------------
334 
 CELL NAME : AO1D
335 
 CELL TYPE : comb
336 
 CELL LOGIC : Y = (!A & !B) + C
337 
---------------------------------------------------------------------*/
338 
 
339 
`suppress_faults
340 
`enable_portfaults
341 
`celldefine
342 
`delay_mode_path
343 
`timescale 1 ns / 100 ps
344 
 
345 
module AO1D(Y,A,B,C);
346 
 input A,B,C;
347 
 output Y;
348 
 wire NET_0_0;
349 
 
350 
 not    INV_35(A_, A);
351 
 not    INV_36(B_, B);
352 
 and      U162(NET_0_0, A_, B_);
353 
 or       U163(Y, NET_0_0, C);
354 
 
355 
       specify
356 
 
357 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
358 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
359 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
360 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
361 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
362 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
363 
                specparam MacroType = "comb";
364 
 
365 
                //pin to pin path delay
366 
 
367 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
368 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
369 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
370 
   endspecify
371 
 
372 
endmodule
373 
 
374 
`endcelldefine
375 
`disable_portfaults
376 
`nosuppress_faults
377 
 
378 
 
379 
 
380 
/*--------------------------------------------------------------------
381 
 CELL NAME : AOI1
382 
 CELL TYPE : comb
383 
 CELL LOGIC : Y = !(A & B + C)
384 
---------------------------------------------------------------------*/
385 
 
386 
`suppress_faults
387 
`enable_portfaults
388 
`celldefine
389 
`delay_mode_path
390 
`timescale 1 ns / 100 ps
391 
 
392 
module AOI1(Y,A,B,C);
393 
 input A,B,C;
394 
 output Y;
395 
 wire NET_0_0;
396 
 
397 
 and      U192(NET_0_0, A, B);
398 
 nor      U193(Y, NET_0_0, C);
399 
 
400 
       specify
401 
 
402 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
403 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
404 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
405 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
406 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
407 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
408 
                specparam MacroType = "comb";
409 
 
410 
                //pin to pin path delay
411 
 
412 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
413 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
414 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
415 
   endspecify
416 
 
417 
endmodule
418 
 
419 
`endcelldefine
420 
`disable_portfaults
421 
`nosuppress_faults
422 
 
423 
 
424 
 
425 
 
426 
/*--------------------------------------------------------------------
427 
 CELL NAME : AOI1B
428 
 CELL TYPE : comb
429 
 CELL LOGIC : Y = !(A & B + !C)
430 
---------------------------------------------------------------------*/
431 
 
432 
`suppress_faults
433 
`enable_portfaults
434 
`celldefine
435 
`delay_mode_path
436 
`timescale 1 ns / 100 ps
437 
 
438 
module AOI1B(Y,A,B,C);
439 
 input A,B,C;
440 
 output Y;
441 
 wire NET_0_0;
442 
 
443 
 not    INV_45(C_, C);
444 
 and      U202(NET_0_0, A, B);
445 
 nor      U203(Y, NET_0_0, C_);
446 
 
447 
       specify
448 
 
449 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
450 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
451 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
452 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
453 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
454 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
455 
                specparam MacroType = "comb";
456 
 
457 
                //pin to pin path delay
458 
 
459 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
460 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
461 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
462 
   endspecify
463 
 
464 
endmodule
465 
 
466 
`endcelldefine
467 
`disable_portfaults
468 
`nosuppress_faults
469 
 
470 
 
471 
 
472 
/*--------------------------------------------------------------------
473 
 CELL NAME : AO1C
474 
 CELL TYPE : comb
475 
 CELL LOGIC : Y = (!A & B) + !C
476 
---------------------------------------------------------------------*/
477 
 
478 
`suppress_faults
479 
`enable_portfaults
480 
`celldefine
481 
`delay_mode_path
482 
`timescale 1 ns / 100 ps
483 
 
484 
module AO1C(Y,A,B,C);
485 
 input A,B,C;
486 
 output Y;
487 
 wire NET_0_0;
488 
 
489 
 not    INV_33(A_, A);
490 
 not    INV_34(C_, C);
491 
 and      U157(NET_0_0, A_, B);
492 
 or       U158(Y, NET_0_0, C_);
493 
 
494 
       specify
495 
 
496 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
497 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
498 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
499 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
500 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
501 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
502 
                specparam MacroType = "comb";
503 
 
504 
                //pin to pin path delay
505 
 
506 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
507 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
508 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
509 
   endspecify
510 
 
511 
endmodule
512 
 
513 
`endcelldefine
514 
`disable_portfaults
515 
`nosuppress_faults
516 
 
517 
 
518 
/*--------------------------------------------------------------------
519 
 CELL NAME : AX1
520 
 CELL TYPE : comb
521 
 CELL LOGIC : Y = (!A & B) ^ C
522 
---------------------------------------------------------------------*/
523 
 
524 
`suppress_faults
525 
`enable_portfaults
526 
`celldefine
527 
`delay_mode_path
528 
`timescale 1 ns / 100 ps
529 
 
530 
module AX1(Y,A,B,C);
531 
 input A,B,C;
532 
 output Y;
533 
 wire NET_0_0;
534 
 
535 
 not    INV_57(A_, A);
536 
 and      U245(NET_0_0, A_, B);
537 
 xor      U246(Y, NET_0_0, C);
538 
 
539 
       specify
540 
 
541 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
542 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
543 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
544 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
545 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
546 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
547 
                specparam MacroType = "comb";
548 
 
549 
                //pin to pin path delay
550 
 
551 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
552 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
553 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
554 
   endspecify
555 
 
556 
endmodule
557 
 
558 
`endcelldefine
559 
`disable_portfaults
560 
`nosuppress_faults
561 
 
562 
 
563 
 
564 
 
565 
/*--------------------------------------------------------------------
566 
 CELL NAME : AX1B
567 
 CELL TYPE : comb
568 
 CELL LOGIC : Y = (!A & !B) ^ C
569 
---------------------------------------------------------------------*/
570 
 
571 
`suppress_faults
572 
`enable_portfaults
573 
`celldefine
574 
`delay_mode_path
575 
`timescale 1 ns / 100 ps
576 
 
577 
module AX1B(Y,A,B,C);
578 
 input A,B,C;
579 
 output Y;
580 
 wire NET_0_0;
581 
 
582 
 not    INV_59(A_, A);
583 
 not    INV_60(B_, B);
584 
 and      U255(NET_0_0, A_, B_);
585 
 xor      U256(Y, NET_0_0, C);
586 
 
587 
       specify
588 
 
589 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
590 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
591 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
592 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
593 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
594 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
595 
                specparam MacroType = "comb";
596 
 
597 
                //pin to pin path delay
598 
 
599 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
600 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
601 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
602 
   endspecify
603 
 
604 
endmodule
605 
 
606 
`endcelldefine
607 
`disable_portfaults
608 
`nosuppress_faults
609 
 
610 
 
611 
 
612 
 
613 
 
614 
 
615 
/*--------------------------------------------------------------------
616 
 CELL NAME : AX1C
617 
 CELL TYPE : comb
618 
 CELL LOGIC : Y = (A & B) ^ C
619 
---------------------------------------------------------------------*/
620 
 
621 
`suppress_faults
622 
`enable_portfaults
623 
`celldefine
624 
`delay_mode_path
625 
`timescale 1 ns / 100 ps
626 
 
627 
module AX1C(Y,A,B,C);
628 
 input A,B,C;
629 
 output Y;
630 
 wire NET_0_0;
631 
 
632 
 and      U260(NET_0_0, A, B);
633 
 xor      U261(Y, NET_0_0, C);
634 
 
635 
       specify
636 
 
637 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
638 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
639 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
640 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
641 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
642 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
643 
                specparam MacroType = "comb";
644 
 
645 
                //pin to pin path delay
646 
 
647 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
648 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
649 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
650 
   endspecify
651 
 
652 
endmodule
653 
 
654 
`endcelldefine
655 
`disable_portfaults
656 
`nosuppress_faults
657 
 
658 
 
659 
 
660 
/*--------------------------------------------------------------------
661 
 CELL NAME : AX1D
662 
 CELL TYPE : comb
663 
 CELL LOGIC : Y = !((!A & !B) ^ C)
664 
---------------------------------------------------------------------*/
665 
 
666 
`suppress_faults
667 
`enable_portfaults
668 
`celldefine
669 
`delay_mode_path
670 
`timescale 1 ns / 100 ps
671 
 
672 
module AX1D(Y,A,B,C);
673 
 input A,B,C;
674 
 output Y;
675 
 wire NET_0_0;
676 
 
677 
 not    INV_61(A_, A);
678 
 not    INV_62(B_, B);
679 
 and      U265(NET_0_0, A_, B_);
680 
 xnor     U266(Y, NET_0_0, C);
681 
 
682 
       specify
683 
 
684 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
685 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
686 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
687 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
688 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
689 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
690 
                specparam MacroType = "comb";
691 
 
692 
                //pin to pin path delay
693 
 
694 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
695 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
696 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
697 
   endspecify
698 
 
699 
endmodule
700 
 
701 
`endcelldefine
702 
`disable_portfaults
703 
`nosuppress_faults
704 
 
705 
 
706 
 
707 
/*--------------------------------------------------------------------
708 
 CELL NAME : AX1E
709 
 CELL TYPE : comb
710 
 CELL LOGIC : Y = !((A & B) ^ C)
711 
---------------------------------------------------------------------*/
712 
 
713 
`suppress_faults
714 
`enable_portfaults
715 
`celldefine
716 
`delay_mode_path
717 
`timescale 1 ns / 100 ps
718 
 
719 
module AX1E(Y,A,B,C);
720 
 input A,B,C;
721 
 output Y;
722 
 wire NET_0_0;
723 
 
724 
 and      U270(NET_0_0, A, B);
725 
 xnor     U271(Y, NET_0_0, C);
726 
 
727 
       specify
728 
 
729 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
730 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
731 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
732 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
733 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
734 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
735 
                specparam MacroType = "comb";
736 
 
737 
                //pin to pin path delay
738 
 
739 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
740 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
741 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
742 
   endspecify
743 
 
744 
endmodule
745 
 
746 
`endcelldefine
747 
`disable_portfaults
748 
`nosuppress_faults
749 
 
750 
 
751 
/*--------------------------------------------------------------------
752 
 CELL NAME : CLKINT
753 
 CELL TYPE : comb
754 
 CELL LOGIC : Y = A
755 
---------------------------------------------------------------------*/
756 
 
757 
`suppress_faults
758 
`enable_portfaults
759 
`celldefine
760 
`delay_mode_path
761 
`timescale 1 ns / 100 ps
762 
 
763 
module CLKINT(Y,A);
764 
 input A;
765 
 output Y;
766 
 
767 
 assign Y = A;
768 
 
769 
endmodule
770 
 
771 
`endcelldefine
772 
`disable_portfaults
773 
`nosuppress_faults
774 
 
775 
 
776 
 
777 
 
778 
 
779 
/*--------------------------------------------------------------
780 
 CELL NAME : DFN1C1
781 
 CELL TYPE : sequential Logic
782 
 CELL SEQ EQN : DFF[Q=Q,CLK =CLK, CLR=CLR, D=D ];
783 
----------------------------------------------------------------*/
784 
 
785 
`suppress_faults
786 
`enable_portfaults
787 
`celldefine
788 
`delay_mode_path
789 
`timescale 1 ns / 100 ps
790 
 
791 
module DFN1C1(CLR, CLK, Q,D);
792 
 input D,CLR,CLK;
793 
 output Q;
794 
 reg NOTIFY_REG;
795 
 
796 
 not INV_CLR_0(CLR_0, CLR);
797 
 
798 
 UFPRB DF_0( Q, D, CLK, CLR_0, NOTIFY_REG );
799 
 
800 
// some temp signals created for timing checking sections
801 
 
802 
      not U0_I2 (_CLR0, CLR);
803 
      buf U_c0 (Enable01,_CLR0);
804 
       buf U_c2 (Enable02, _CLR0);
805 
      buf U_c6 (Enable05, _CLR0);
806 
 
807 
//--------------------------------------------------------------
808 
//              Timing Checking Section
809 
//-------------------------------------------------------------
810 
 
811 
 specify
812 
 
813 
        specparam   tpdLH_CLK_to_Q = (0.1:0.1:0.1);
814 
        specparam   tpdHL_CLK_to_Q = (0.1:0.1:0.1);
815 
        specparam   tpdLH_CLR_to_Q = (0.1:0.1:0.1);
816 
        specparam   tpdHL_CLR_to_Q = (0.1:0.1:0.1);
817 
 
818 
 
819 
 
820 
        //check timing delay for output
821 
 
822 
        (posedge CLK => (Q +: D))=(tpdLH_CLK_to_Q, tpdHL_CLK_to_Q);
823 
        (posedge CLR => (Q +: 1'b0)) = (tpdLH_CLR_to_Q, tpdHL_CLR_to_Q);
824 
 
825 
        //checking setup and hold timing for inputs
826 
 
827 
        $setup(posedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG);
828 
        $setup(negedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG);
829 
        $hold(posedge CLK &&& Enable01, posedge D,0.0, NOTIFY_REG);
830 
        $hold(posedge CLK &&& Enable01, negedge D,0.0, NOTIFY_REG);
831 
 
832 
        //checking timing for control signals
833 
 
834 
        $hold(posedge CLK, negedge CLR,0.0, NOTIFY_REG);
835 
 
836 
        //checking the pulse width
837 
 
838 
        $width(posedge CLK &&& Enable05 ,0,  0, NOTIFY_REG);
839 
        $width(negedge CLK &&& Enable05, 0, 0, NOTIFY_REG);
840 
        $width(posedge CLR, 0.0, 0, NOTIFY_REG);
841 
 
842 
        //checing the recovery data
843 
 
844 
        $recovery(negedge CLR, posedge CLK, 0.0, NOTIFY_REG);
845 
 
846 
 endspecify
847 
 
848 
endmodule
849 
 
850 
`endcelldefine
851 
`disable_portfaults
852 
`nosuppress_faults
853 
 
854 
 
855 
/*--------------------------------------------------------------
856 
 CELL NAME : DFN1E1C1
857 
 CELL TYPE : sequential Logic
858 
 CELL SEQ EQN : DFF[Q=Q,CLK =CLK, E=E, CLR=CLR, D=D ];
859 
----------------------------------------------------------------*/
860 
 
861 
`suppress_faults
862 
`enable_portfaults
863 
`celldefine
864 
`delay_mode_path
865 
`timescale 1 ns / 100 ps
866 
 
867 
module DFN1E1C1(CLR, E, CLK, Q,D);
868 
 input D,CLR,E,CLK;
869 
 output Q;
870 
 supply1 VCC_0;
871 
 reg NOTIFY_REG;
872 
 
873 
 not INV_CLR_0(CLR_0, CLR);
874 
 not INV_EN_0(E_0, E);
875 
 
876 
 Dffpr DF_0(Q, D,CLK,CLR_0, VCC_0, E_0, NOTIFY_REG);
877 
 
878 
// some temp signals created for timing checking sections
879 
 
880 
      not U0_I2 (_CLR0, CLR);
881 
      and U_c0 (Enable01, E, _CLR0);
882 
      and U_c2 (Enable02, E, _CLR0);
883 
      buf U_c4 (Enable04, E);
884 
      buf U_c6 (Enable05, _CLR0);
885 
 
886 
//--------------------------------------------------------------
887 
//              Timing Checking Section
888 
//-------------------------------------------------------------
889 
 
890 
 specify
891 
 
892 
        specparam   tpdLH_CLK_to_Q = (0.1:0.1:0.1);
893 
        specparam   tpdHL_CLK_to_Q = (0.1:0.1:0.1);
894 
        specparam   tpdLH_CLR_to_Q = (0.1:0.1:0.1);
895 
        specparam   tpdHL_CLR_to_Q = (0.1:0.1:0.1);
896 
 
897 
 
898 
 
899 
        //check timing delay for output
900 
 
901 
        (posedge CLK => (Q +: D))=(tpdLH_CLK_to_Q, tpdHL_CLK_to_Q);
902 
        (posedge CLR => (Q +: 1'b0)) = (tpdLH_CLR_to_Q, tpdHL_CLR_to_Q);
903 
 
904 
        //checking setup and hold timing for inputs
905 
 
906 
        $setup(posedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG);
907 
        $setup(negedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG);
908 
        $hold(posedge CLK &&& Enable01, posedge D,0.0, NOTIFY_REG);
909 
        $hold(posedge CLK &&& Enable01, negedge D,0.0, NOTIFY_REG);
910 
 
911 
        //checking timing for control signals
912 
 
913 
        $setup(posedge E,posedge CLK &&& Enable05,  0.0, NOTIFY_REG);
914 
        $hold(posedge CLK &&& Enable05, posedge E,0.0, NOTIFY_REG);
915 
        $setup(negedge E,posedge CLK &&& Enable05, 0.0, NOTIFY_REG);
916 
        $hold(posedge CLK &&& Enable05, negedge E,0.0, NOTIFY_REG);
917 
        $hold(posedge CLK &&& Enable04, negedge CLR,0.0, NOTIFY_REG);
918 
 
919 
        //checking the pulse width
920 
 
921 
        $width(posedge CLK &&& Enable05 ,0,  0, NOTIFY_REG);
922 
        $width(negedge CLK &&& Enable05, 0, 0, NOTIFY_REG);
923 
        $width(posedge CLR, 0.0, 0, NOTIFY_REG);
924 
 
925 
        //checing the recovery data
926 
 
927 
        $recovery(negedge CLR, posedge CLK &&& Enable04, 0.0, NOTIFY_REG);
928 
 
929 
 endspecify
930 
 
931 
endmodule
932 
 
933 
`endcelldefine
934 
`disable_portfaults
935 
`nosuppress_faults
936 
 
937 
 
938 
 
939 
 
940 
/*--------------------------------------------------------------
941 
 CELL NAME : DFN1E0C1
942 
 CELL TYPE : sequential Logic
943 
 CELL SEQ EQN : DFF[Q=Q,CLK =CLK, _E=E, CLR=CLR, D=D ];
944 
----------------------------------------------------------------*/
945 
 
946 
`suppress_faults
947 
`enable_portfaults
948 
`celldefine
949 
`delay_mode_path
950 
`timescale 1 ns / 100 ps
951 
 
952 
module DFN1E0C1(CLR, E, CLK, Q,D);
953 
 input D,CLR,E,CLK;
954 
 output Q;
955 
 supply1 VCC_0;
956 
 reg NOTIFY_REG;
957 
 
958 
 not INV_CLR_0(CLR_0, CLR);
959 
 
960 
 Dffpr DF_0(Q, D,CLK,CLR_0, VCC_0, E, NOTIFY_REG);
961 
 
962 
// some temp signals created for timing checking sections
963 
 
964 
      not U0_I2 (_CLR0, CLR);
965 
      not U0_I3 (_E0, E);
966 
      and U_c0 (Enable01, _E0, _CLR0);
967 
      and U_c2 (Enable02, _E0, _CLR0);
968 
      buf U_c4 (Enable04, _E0);
969 
      buf U_c6 (Enable05, _CLR0);
970 
 
971 
//--------------------------------------------------------------
972 
//              Timing Checking Section
973 
//-------------------------------------------------------------
974 
 
975 
 specify
976 
 
977 
        specparam   tpdLH_CLK_to_Q = (0.1:0.1:0.1);
978 
        specparam   tpdHL_CLK_to_Q = (0.1:0.1:0.1);
979 
        specparam   tpdLH_CLR_to_Q = (0.1:0.1:0.1);
980 
        specparam   tpdHL_CLR_to_Q = (0.1:0.1:0.1);
981 
 
982 
 
983 
 
984 
        //check timing delay for output
985 
 
986 
        (posedge CLK => (Q +: D))=(tpdLH_CLK_to_Q, tpdHL_CLK_to_Q);
987 
        (posedge CLR => (Q +: 1'b0)) = (tpdLH_CLR_to_Q, tpdHL_CLR_to_Q);
988 
 
989 
        //checking setup and hold timing for inputs
990 
 
991 
        $setup(posedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG);
992 
        $setup(negedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG);
993 
        $hold(posedge CLK &&& Enable01, posedge D,0.0, NOTIFY_REG);
994 
        $hold(posedge CLK &&& Enable01, negedge D,0.0, NOTIFY_REG);
995 
 
996 
        //checking timing for control signals
997 
 
998 
        $setup(posedge E,posedge CLK &&& Enable05,  0.0, NOTIFY_REG);
999 
        $hold(posedge CLK &&& Enable05, posedge E,0.0, NOTIFY_REG);
1000 
        $setup(negedge E,posedge CLK &&& Enable05, 0.0, NOTIFY_REG);
1001 
        $hold(posedge CLK &&& Enable05, negedge E,0.0, NOTIFY_REG);
1002 
        $hold(posedge CLK &&& Enable04, negedge CLR,0.0, NOTIFY_REG);
1003 
 
1004 
        //checking the pulse width
1005 
 
1006 
        $width(posedge CLK &&& Enable05 ,0,  0, NOTIFY_REG);
1007 
        $width(negedge CLK &&& Enable05, 0, 0, NOTIFY_REG);
1008 
        $width(posedge CLR, 0.0, 0, NOTIFY_REG);
1009 
 
1010 
        //checing the recovery data
1011 
 
1012 
        $recovery(negedge CLR, posedge CLK &&& Enable04, 0.0, NOTIFY_REG);
1013 
 
1014 
 endspecify
1015 
 
1016 
endmodule
1017 
 
1018 
`endcelldefine
1019 
`disable_portfaults
1020 
`nosuppress_faults
1021 
 
1022 
 
1023 
 
1024 
 
1025 
/*--------------------------------------------------------------
1026 
 CELL NAME : DFN1E1P1
1027 
 CELL TYPE : sequential Logic
1028 
 CELL SEQ EQN : DFF[Q=Q,CLK =CLK, E=E, PRE=PRE, D=D ];
1029 
----------------------------------------------------------------*/
1030 
 
1031 
`suppress_faults
1032 
`enable_portfaults
1033 
`celldefine
1034 
`delay_mode_path
1035 
`timescale 1 ns / 100 ps
1036 
 
1037 
module DFN1E1P1(PRE, E, CLK, Q,D);
1038 
 input D,PRE,E,CLK;
1039 
 output Q;
1040 
 supply1 VCC_0;
1041 
 reg NOTIFY_REG;
1042 
 
1043 
 not INV_PRE_0(PRE_0, PRE);
1044 
 not INV_EN_0(E_0, E);
1045 
 
1046 
 Dffpr DF_0(Q, D,CLK,VCC_0, PRE_0, E_0, NOTIFY_REG);
1047 
 
1048 
// some temp signals created for timing checking sections
1049 
 
1050 
      not U0_I1 (_PRE0, PRE);
1051 
      and U_c0 (Enable01, E, _PRE0);
1052 
      buf U_c2 (Enable02, E);
1053 
      and U_c4 (Enable04, E, _PRE0);
1054 
       buf U_c6 (Enable05, _PRE0);
1055 
 
1056 
//--------------------------------------------------------------
1057 
//              Timing Checking Section
1058 
//-------------------------------------------------------------
1059 
 
1060 
 specify
1061 
 
1062 
        specparam   tpdLH_CLK_to_Q = (0.1:0.1:0.1);
1063 
        specparam   tpdHL_CLK_to_Q = (0.1:0.1:0.1);
1064 
        specparam   tpdLH_PRE_to_Q = (0.1:0.1:0.1);
1065 
        specparam   tpdHL_PRE_to_Q = (0.1:0.1:0.1);
1066 
 
1067 
 
1068 
 
1069 
        //check timing delay for output
1070 
 
1071 
        (posedge CLK => (Q +: D))=(tpdLH_CLK_to_Q, tpdHL_CLK_to_Q);
1072 
        (posedge PRE => (Q +: 1'b1)) = (tpdLH_PRE_to_Q, tpdHL_PRE_to_Q);
1073 
 
1074 
        //checking setup and hold timing for inputs
1075 
 
1076 
        $setup(posedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG);
1077 
        $setup(negedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG);
1078 
        $hold(posedge CLK &&& Enable01, posedge D,0.0, NOTIFY_REG);
1079 
        $hold(posedge CLK &&& Enable01, negedge D,0.0, NOTIFY_REG);
1080 
 
1081 
        //checking timing for control signals
1082 
 
1083 
        $setup(posedge E,posedge CLK &&& Enable05,  0.0, NOTIFY_REG);
1084 
        $hold(posedge CLK &&& Enable05, posedge E,0.0, NOTIFY_REG);
1085 
        $setup(negedge E,posedge CLK &&& Enable05, 0.0, NOTIFY_REG);
1086 
        $hold(posedge CLK &&& Enable05, negedge E,0.0, NOTIFY_REG);
1087 
 
1088 
        $hold(posedge CLK &&& Enable02, negedge PRE,0.0, NOTIFY_REG);
1089 
 
1090 
        //checking the pulse width
1091 
 
1092 
        $width(posedge CLK &&& Enable05 ,0,  0, NOTIFY_REG);
1093 
        $width(negedge CLK &&& Enable05, 0, 0, NOTIFY_REG);
1094 
        $width(posedge PRE,  0.0, 0, NOTIFY_REG);
1095 
 
1096 
        //checing the recovery data
1097 
 
1098 
        $recovery(negedge PRE, posedge CLK &&& Enable02, 0.0, NOTIFY_REG);
1099 
 
1100 
 endspecify
1101 
 
1102 
endmodule
1103 
 
1104 
`endcelldefine
1105 
`disable_portfaults
1106 
`nosuppress_faults
1107 
 
1108 
 
1109 
 
1110 
 
1111 
 
1112 
/*--------------------------------------------------------------
1113 
 CELL NAME : DFN1P1
1114 
 CELL TYPE : sequential Logic
1115 
 CELL SEQ EQN : DFF[Q=Q,CLK =CLK, PRE=PRE, D=D ];
1116 
----------------------------------------------------------------*/
1117 
 
1118 
`suppress_faults
1119 
`enable_portfaults
1120 
`celldefine
1121 
`delay_mode_path
1122 
`timescale 1 ns / 100 ps
1123 
 
1124 
module DFN1P1(PRE, CLK, Q,D);
1125 
 input D,PRE,CLK;
1126 
 output Q;
1127 
 supply1 VCC_0;
1128 
 supply0 GND_0;
1129 
 reg NOTIFY_REG;
1130 
 
1131 
 not INV_PRE_0(PRE_0, PRE);
1132 
 
1133 
 Dffpr DF_0(Q, D,CLK,VCC_0, PRE_0, GND_0, NOTIFY_REG);
1134 
 
1135 
// some temp signals created for timing checking sections
1136 
 
1137 
      not U0_I1 (_PRE0, PRE);
1138 
      buf U_c0 (Enable01, _PRE0);
1139 
       buf U_c4 (Enable04, _PRE0);
1140 
       buf U_c6 (Enable05, _PRE0);
1141 
 
1142 
//--------------------------------------------------------------
1143 
//              Timing Checking Section
1144 
//-------------------------------------------------------------
1145 
 
1146 
 specify
1147 
 
1148 
        specparam   tpdLH_CLK_to_Q = (0.1:0.1:0.1);
1149 
        specparam   tpdHL_CLK_to_Q = (0.1:0.1:0.1);
1150 
        specparam   tpdLH_PRE_to_Q = (0.1:0.1:0.1);
1151 
        specparam   tpdHL_PRE_to_Q = (0.1:0.1:0.1);
1152 
 
1153 
 
1154 
 
1155 
        //check timing delay for output
1156 
 
1157 
        (posedge CLK => (Q +: D))=(tpdLH_CLK_to_Q, tpdHL_CLK_to_Q);
1158 
        (posedge PRE => (Q +: 1'b1)) = (tpdLH_PRE_to_Q, tpdHL_PRE_to_Q);
1159 
 
1160 
        //checking setup and hold timing for inputs
1161 
 
1162 
        $setup(posedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG);
1163 
        $setup(negedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG);
1164 
        $hold(posedge CLK &&& Enable01, posedge D,0.0, NOTIFY_REG);
1165 
        $hold(posedge CLK &&& Enable01, negedge D,0.0, NOTIFY_REG);
1166 
 
1167 
        //checking timing for control signals
1168 
 
1169 
 
1170 
        $hold(posedge CLK, negedge PRE,0.0, NOTIFY_REG);
1171 
 
1172 
        //checking the pulse width
1173 
 
1174 
        $width(posedge CLK &&& Enable05 ,0,  0, NOTIFY_REG);
1175 
        $width(negedge CLK &&& Enable05, 0, 0, NOTIFY_REG);
1176 
        $width(posedge PRE,  0.0, 0, NOTIFY_REG);
1177 
 
1178 
        //checing the recovery data
1179 
 
1180 
        $recovery(negedge PRE, posedge CLK, 0.0, NOTIFY_REG);
1181 
 
1182 
 endspecify
1183 
 
1184 
endmodule
1185 
 
1186 
`endcelldefine
1187 
`disable_portfaults
1188 
`nosuppress_faults
1189 
 
1190 
 
1191 
/*--------------------------------------------------------------------
1192 
 CELL NAME : GND
1193 
 CELL TYPE : comb
1194 
 CELL LOGIC : Y=0
1195 
---------------------------------------------------------------------*/
1196 
 
1197 
`suppress_faults
1198 
`enable_portfaults
1199 
`celldefine
1200 
`delay_mode_path
1201 
`timescale 1 ns / 100 ps
1202 
 
1203 
module GND(Y);
1204 
 output Y;
1205 
 
1206 
 supply0        Y;
1207 
 
1208 
       specify
1209 
 
1210 
                specparam MacroType = "comb";
1211 
 
1212 
                //pin to pin path delay
1213 
 
1214 
   endspecify
1215 
 
1216 
endmodule
1217 
 
1218 
`endcelldefine
1219 
`disable_portfaults
1220 
`nosuppress_faults
1221 
 
1222 
 
1223 
 
1224 
 
1225 
/*--------------------------------------------------------------------
1226 
 CELL NAME : MX2
1227 
 CELL TYPE : comb
1228 
 CELL LOGIC : Y = (A & !S) + (B & S)
1229 
---------------------------------------------------------------------*/
1230 
 
1231 
`suppress_faults
1232 
`enable_portfaults
1233 
`celldefine
1234 
`delay_mode_path
1235 
`timescale 1 ns / 100 ps
1236 
 
1237 
module MX2(Y,A,S,B);
1238 
 input A,S,B;
1239 
 output Y;
1240 
 wire NET_0_0, NET_0_1;
1241 
 
1242 
 not    INV_110(S_, S);
1243 
 UDP_MUX2   U594(Y, A, B, S_);
1244 
 
1245 
       specify
1246 
 
1247 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1248 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1249 
                specparam tpdLH_S_to_Y = (0.1:0.1:0.1);
1250 
                specparam tpdHL_S_to_Y = (0.1:0.1:0.1);
1251 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1252 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1253 
                specparam MacroType = "comb";
1254 
 
1255 
                //pin to pin path delay
1256 
 
1257 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1258 
                (S => Y ) = ( tpdLH_S_to_Y, tpdHL_S_to_Y );
1259 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1260 
   endspecify
1261 
 
1262 
endmodule
1263 
 
1264 
`endcelldefine
1265 
`disable_portfaults
1266 
`nosuppress_faults
1267 
 
1268 
 
1269 
 
1270 
/*--------------------------------------------------------------------
1271 
 CELL NAME : NAND2
1272 
 CELL TYPE : comb
1273 
 CELL LOGIC : Y = !(A & B)
1274 
---------------------------------------------------------------------*/
1275 
 
1276 
`suppress_faults
1277 
`enable_portfaults
1278 
`celldefine
1279 
`delay_mode_path
1280 
`timescale 1 ns / 100 ps
1281 
 
1282 
module NAND2(Y,A,B);
1283 
 input A,B;
1284 
 output Y;
1285 
 
1286 
 nand     U610(Y, A, B);
1287 
 
1288 
       specify
1289 
 
1290 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1291 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1292 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1293 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1294 
                specparam MacroType = "comb";
1295 
 
1296 
                //pin to pin path delay
1297 
 
1298 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1299 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1300 
   endspecify
1301 
 
1302 
endmodule
1303 
 
1304 
`endcelldefine
1305 
`disable_portfaults
1306 
`nosuppress_faults
1307 
 
1308 
 
1309 
 
1310 
 
1311 
 
1312 
/*--------------------------------------------------------------------
1313 
 CELL NAME : NOR2
1314 
 CELL TYPE : comb
1315 
 CELL LOGIC : Y = !(A + B)
1316 
---------------------------------------------------------------------*/
1317 
 
1318 
`suppress_faults
1319 
`enable_portfaults
1320 
`celldefine
1321 
`delay_mode_path
1322 
`timescale 1 ns / 100 ps
1323 
 
1324 
module NOR2(Y,A,B);
1325 
 input A,B;
1326 
 output Y;
1327 
 
1328 
 nor      U649(Y, A, B);
1329 
 
1330 
       specify
1331 
 
1332 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1333 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1334 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1335 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1336 
                specparam MacroType = "comb";
1337 
 
1338 
                //pin to pin path delay
1339 
 
1340 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1341 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1342 
   endspecify
1343 
 
1344 
endmodule
1345 
 
1346 
`endcelldefine
1347 
`disable_portfaults
1348 
`nosuppress_faults
1349 
 
1350 
 
1351 
 
1352 
/*--------------------------------------------------------------------
1353 
 CELL NAME : NOR2A
1354 
 CELL TYPE : comb
1355 
 CELL LOGIC : Y = !(!A + B)
1356 
---------------------------------------------------------------------*/
1357 
 
1358 
`suppress_faults
1359 
`enable_portfaults
1360 
`celldefine
1361 
`delay_mode_path
1362 
`timescale 1 ns / 100 ps
1363 
 
1364 
module NOR2A(Y,A,B);
1365 
 input A,B;
1366 
 output Y;
1367 
 
1368 
 not    INV_130(A_, A);
1369 
 nor      U652(Y, A_, B);
1370 
 
1371 
       specify
1372 
 
1373 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1374 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1375 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1376 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1377 
                specparam MacroType = "comb";
1378 
 
1379 
                //pin to pin path delay
1380 
 
1381 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1382 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1383 
   endspecify
1384 
 
1385 
endmodule
1386 
 
1387 
`endcelldefine
1388 
`disable_portfaults
1389 
`nosuppress_faults
1390 
 
1391 
 
1392 
 
1393 
/*--------------------------------------------------------------------
1394 
 CELL NAME : NOR2B
1395 
 CELL TYPE : comb
1396 
 CELL LOGIC : Y = !(!A + !B)
1397 
---------------------------------------------------------------------*/
1398 
 
1399 
`suppress_faults
1400 
`enable_portfaults
1401 
`celldefine
1402 
`delay_mode_path
1403 
`timescale 1 ns / 100 ps
1404 
 
1405 
module NOR2B(Y,A,B);
1406 
 input A,B;
1407 
 output Y;
1408 
 
1409 
 not    INV_131(A_, A);
1410 
 not    INV_132(B_, B);
1411 
 nor      U655(Y, A_, B_);
1412 
 
1413 
       specify
1414 
 
1415 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1416 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1417 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1418 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1419 
                specparam MacroType = "comb";
1420 
 
1421 
                //pin to pin path delay
1422 
 
1423 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1424 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1425 
   endspecify
1426 
 
1427 
endmodule
1428 
 
1429 
`endcelldefine
1430 
`disable_portfaults
1431 
`nosuppress_faults
1432 
 
1433 
 
1434 
 
1435 
/*--------------------------------------------------------------------
1436 
 CELL NAME : NOR3
1437 
 CELL TYPE : comb
1438 
 CELL LOGIC : Y = !(A + B + C)
1439 
---------------------------------------------------------------------*/
1440 
 
1441 
`suppress_faults
1442 
`enable_portfaults
1443 
`celldefine
1444 
`delay_mode_path
1445 
`timescale 1 ns / 100 ps
1446 
 
1447 
module NOR3(Y,A,B,C);
1448 
 input A,B,C;
1449 
 output Y;
1450 
 wire NET_0_0;
1451 
 
1452 
 or       U662(NET_0_0, A, B);
1453 
 nor      U663(Y, NET_0_0, C);
1454 
 
1455 
       specify
1456 
 
1457 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1458 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1459 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1460 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1461 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
1462 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
1463 
                specparam MacroType = "comb";
1464 
 
1465 
                //pin to pin path delay
1466 
 
1467 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1468 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1469 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
1470 
   endspecify
1471 
 
1472 
endmodule
1473 
 
1474 
`endcelldefine
1475 
`disable_portfaults
1476 
`nosuppress_faults
1477 
 
1478 
 
1479 
 
1480 
/*--------------------------------------------------------------------
1481 
 CELL NAME : NOR3A
1482 
 CELL TYPE : comb
1483 
 CELL LOGIC : Y = !(!A + B + C)
1484 
---------------------------------------------------------------------*/
1485 
 
1486 
`suppress_faults
1487 
`enable_portfaults
1488 
`celldefine
1489 
`delay_mode_path
1490 
`timescale 1 ns / 100 ps
1491 
 
1492 
module NOR3A(Y,A,B,C);
1493 
 input A,B,C;
1494 
 output Y;
1495 
 wire NET_0_0;
1496 
 
1497 
 not    INV_134(A_, A);
1498 
 or       U667(NET_0_0, A_, B);
1499 
 nor      U668(Y, NET_0_0, C);
1500 
 
1501 
       specify
1502 
 
1503 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1504 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1505 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1506 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1507 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
1508 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
1509 
                specparam MacroType = "comb";
1510 
 
1511 
                //pin to pin path delay
1512 
 
1513 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1514 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1515 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
1516 
   endspecify
1517 
 
1518 
endmodule
1519 
 
1520 
`endcelldefine
1521 
`disable_portfaults
1522 
`nosuppress_faults
1523 
 
1524 
 
1525 
 
1526 
/*--------------------------------------------------------------------
1527 
 CELL NAME : NOR3B
1528 
 CELL TYPE : comb
1529 
 CELL LOGIC : Y = !(!A + !B + C)
1530 
---------------------------------------------------------------------*/
1531 
 
1532 
`suppress_faults
1533 
`enable_portfaults
1534 
`celldefine
1535 
`delay_mode_path
1536 
`timescale 1 ns / 100 ps
1537 
 
1538 
module NOR3B(Y,A,B,C);
1539 
 input A,B,C;
1540 
 output Y;
1541 
 wire NET_0_0;
1542 
 
1543 
 not    INV_135(A_, A);
1544 
 not    INV_136(B_, B);
1545 
 or       U672(NET_0_0, A_, B_);
1546 
 nor      U673(Y, NET_0_0, C);
1547 
 
1548 
       specify
1549 
 
1550 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1551 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1552 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1553 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1554 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
1555 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
1556 
                specparam MacroType = "comb";
1557 
 
1558 
                //pin to pin path delay
1559 
 
1560 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1561 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1562 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
1563 
   endspecify
1564 
 
1565 
endmodule
1566 
 
1567 
`endcelldefine
1568 
`disable_portfaults
1569 
`nosuppress_faults
1570 
 
1571 
 
1572 
 
1573 
/*--------------------------------------------------------------------
1574 
 CELL NAME : NOR3C
1575 
 CELL TYPE : comb
1576 
 CELL LOGIC : Y = !(!A + !B + !C)
1577 
---------------------------------------------------------------------*/
1578 
 
1579 
`suppress_faults
1580 
`enable_portfaults
1581 
`celldefine
1582 
`delay_mode_path
1583 
`timescale 1 ns / 100 ps
1584 
 
1585 
module NOR3C(Y,A,B,C);
1586 
 input A,B,C;
1587 
 output Y;
1588 
 wire NET_0_0;
1589 
 
1590 
 not    INV_137(A_, A);
1591 
 not    INV_138(B_, B);
1592 
 not    INV_139(C_, C);
1593 
 or       U677(NET_0_0, A_, B_);
1594 
 nor      U678(Y, NET_0_0, C_);
1595 
 
1596 
       specify
1597 
 
1598 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1599 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1600 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1601 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1602 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
1603 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
1604 
                specparam MacroType = "comb";
1605 
 
1606 
                //pin to pin path delay
1607 
 
1608 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1609 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1610 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
1611 
   endspecify
1612 
 
1613 
endmodule
1614 
 
1615 
`endcelldefine
1616 
`disable_portfaults
1617 
`nosuppress_faults
1618 
 
1619 
 
1620 
 
1621 
/*--------------------------------------------------------------------
1622 
 CELL NAME : OA1
1623 
 CELL TYPE : comb
1624 
 CELL LOGIC : Y = (A + B) & C
1625 
---------------------------------------------------------------------*/
1626 
 
1627 
`suppress_faults
1628 
`enable_portfaults
1629 
`celldefine
1630 
`delay_mode_path
1631 
`timescale 1 ns / 100 ps
1632 
 
1633 
module OA1(Y,A,B,C);
1634 
 input A,B,C;
1635 
 output Y;
1636 
 wire NET_0_0;
1637 
 
1638 
 or       U692(NET_0_0, A, B);
1639 
 and      U693(Y, NET_0_0, C);
1640 
 
1641 
       specify
1642 
 
1643 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1644 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1645 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1646 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1647 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
1648 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
1649 
                specparam MacroType = "comb";
1650 
 
1651 
                //pin to pin path delay
1652 
 
1653 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1654 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1655 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
1656 
   endspecify
1657 
 
1658 
endmodule
1659 
 
1660 
`endcelldefine
1661 
`disable_portfaults
1662 
`nosuppress_faults
1663 
 
1664 
 
1665 
 
1666 
/*--------------------------------------------------------------------
1667 
 CELL NAME : OA1A
1668 
 CELL TYPE : comb
1669 
 CELL LOGIC : Y = (!A + B) & C
1670 
---------------------------------------------------------------------*/
1671 
 
1672 
`suppress_faults
1673 
`enable_portfaults
1674 
`celldefine
1675 
`delay_mode_path
1676 
`timescale 1 ns / 100 ps
1677 
 
1678 
module OA1A(Y,A,B,C);
1679 
 input A,B,C;
1680 
 output Y;
1681 
 wire NET_0_0;
1682 
 
1683 
 not    INV_143(A_, A);
1684 
 or       U697(NET_0_0, A_, B);
1685 
 and      U698(Y, NET_0_0, C);
1686 
 
1687 
       specify
1688 
 
1689 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1690 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1691 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1692 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1693 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
1694 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
1695 
                specparam MacroType = "comb";
1696 
 
1697 
                //pin to pin path delay
1698 
 
1699 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1700 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1701 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
1702 
   endspecify
1703 
 
1704 
endmodule
1705 
 
1706 
`endcelldefine
1707 
`disable_portfaults
1708 
`nosuppress_faults
1709 
 
1710 
 
1711 
 
1712 
/*--------------------------------------------------------------------
1713 
 CELL NAME : OA1B
1714 
 CELL TYPE : comb
1715 
 CELL LOGIC : Y = !C & (A + B)
1716 
---------------------------------------------------------------------*/
1717 
 
1718 
`suppress_faults
1719 
`enable_portfaults
1720 
`celldefine
1721 
`delay_mode_path
1722 
`timescale 1 ns / 100 ps
1723 
 
1724 
module OA1B(Y,C,A,B);
1725 
 input C,A,B;
1726 
 output Y;
1727 
 wire NET_0_0;
1728 
 
1729 
 not    INV_144(C_, C);
1730 
 and      U701(Y, C_, NET_0_0);
1731 
 or       U703(NET_0_0, A, B);
1732 
 
1733 
       specify
1734 
 
1735 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
1736 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
1737 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1738 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1739 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1740 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1741 
                specparam MacroType = "comb";
1742 
 
1743 
                //pin to pin path delay
1744 
 
1745 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
1746 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1747 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1748 
   endspecify
1749 
 
1750 
endmodule
1751 
 
1752 
`endcelldefine
1753 
`disable_portfaults
1754 
`nosuppress_faults
1755 
 
1756 
 
1757 
 
1758 
/*--------------------------------------------------------------------
1759 
 CELL NAME : OA1C
1760 
 CELL TYPE : comb
1761 
 CELL LOGIC : Y = (!A + B) & !C
1762 
---------------------------------------------------------------------*/
1763 
 
1764 
`suppress_faults
1765 
`enable_portfaults
1766 
`celldefine
1767 
`delay_mode_path
1768 
`timescale 1 ns / 100 ps
1769 
 
1770 
module OA1C(Y,A,B,C);
1771 
 input A,B,C;
1772 
 output Y;
1773 
 wire NET_0_0;
1774 
 
1775 
 not    INV_145(A_, A);
1776 
 not    INV_146(C_, C);
1777 
 or       U707(NET_0_0, A_, B);
1778 
 and      U708(Y, NET_0_0, C_);
1779 
 
1780 
       specify
1781 
 
1782 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1783 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1784 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1785 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1786 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
1787 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
1788 
                specparam MacroType = "comb";
1789 
 
1790 
                //pin to pin path delay
1791 
 
1792 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1793 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1794 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
1795 
   endspecify
1796 
 
1797 
endmodule
1798 
 
1799 
`endcelldefine
1800 
`disable_portfaults
1801 
`nosuppress_faults
1802 
 
1803 
 
1804 
 
1805 
/*--------------------------------------------------------------------
1806 
 CELL NAME : OR2
1807 
 CELL TYPE : comb
1808 
 CELL LOGIC : Y = A + B
1809 
---------------------------------------------------------------------*/
1810 
 
1811 
`suppress_faults
1812 
`enable_portfaults
1813 
`celldefine
1814 
`delay_mode_path
1815 
`timescale 1 ns / 100 ps
1816 
 
1817 
module OR2(Y,A,B);
1818 
 input A,B;
1819 
 output Y;
1820 
 
1821 
 or       U756(Y, A, B);
1822 
 
1823 
       specify
1824 
 
1825 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1826 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1827 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1828 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1829 
                specparam MacroType = "comb";
1830 
 
1831 
                //pin to pin path delay
1832 
 
1833 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1834 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1835 
   endspecify
1836 
 
1837 
endmodule
1838 
 
1839 
`endcelldefine
1840 
`disable_portfaults
1841 
`nosuppress_faults
1842 
 
1843 
 
1844 
 
1845 
/*--------------------------------------------------------------------
1846 
 CELL NAME : OR2A
1847 
 CELL TYPE : comb
1848 
 CELL LOGIC : Y = !A + B
1849 
---------------------------------------------------------------------*/
1850 
 
1851 
`suppress_faults
1852 
`enable_portfaults
1853 
`celldefine
1854 
`delay_mode_path
1855 
`timescale 1 ns / 100 ps
1856 
 
1857 
module OR2A(Y,A,B);
1858 
 input A,B;
1859 
 output Y;
1860 
 
1861 
 not    INV_156(A_, A);
1862 
 or       U759(Y, A_, B);
1863 
 
1864 
       specify
1865 
 
1866 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1867 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1868 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1869 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1870 
                specparam MacroType = "comb";
1871 
 
1872 
                //pin to pin path delay
1873 
 
1874 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1875 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1876 
   endspecify
1877 
 
1878 
endmodule
1879 
 
1880 
`endcelldefine
1881 
`disable_portfaults
1882 
`nosuppress_faults
1883 
 
1884 
 
1885 
 
1886 
/*--------------------------------------------------------------------
1887 
 CELL NAME : OR2B
1888 
 CELL TYPE : comb
1889 
 CELL LOGIC : Y = !A + !B
1890 
---------------------------------------------------------------------*/
1891 
 
1892 
`suppress_faults
1893 
`enable_portfaults
1894 
`celldefine
1895 
`delay_mode_path
1896 
`timescale 1 ns / 100 ps
1897 
 
1898 
module OR2B(Y,A,B);
1899 
 input A,B;
1900 
 output Y;
1901 
 
1902 
 not    INV_157(A_, A);
1903 
 not    INV_158(B_, B);
1904 
 or       U762(Y, A_, B_);
1905 
 
1906 
       specify
1907 
 
1908 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1909 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1910 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1911 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1912 
                specparam MacroType = "comb";
1913 
 
1914 
                //pin to pin path delay
1915 
 
1916 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1917 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1918 
   endspecify
1919 
 
1920 
endmodule
1921 
 
1922 
`endcelldefine
1923 
`disable_portfaults
1924 
`nosuppress_faults
1925 
 
1926 
 
1927 
 
1928 
/*--------------------------------------------------------------------
1929 
 CELL NAME : OR3
1930 
 CELL TYPE : comb
1931 
 CELL LOGIC : Y = A + B + C
1932 
---------------------------------------------------------------------*/
1933 
 
1934 
`suppress_faults
1935 
`enable_portfaults
1936 
`celldefine
1937 
`delay_mode_path
1938 
`timescale 1 ns / 100 ps
1939 
 
1940 
module OR3(Y,A,B,C);
1941 
 input A,B,C;
1942 
 output Y;
1943 
 wire NET_0_0;
1944 
 
1945 
 or       U769(NET_0_0, A, B);
1946 
 or       U770(Y, NET_0_0, C);
1947 
 
1948 
       specify
1949 
 
1950 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1951 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1952 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1953 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
1954 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
1955 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
1956 
                specparam MacroType = "comb";
1957 
 
1958 
                //pin to pin path delay
1959 
 
1960 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
1961 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
1962 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
1963 
   endspecify
1964 
 
1965 
endmodule
1966 
 
1967 
`endcelldefine
1968 
`disable_portfaults
1969 
`nosuppress_faults
1970 
 
1971 
 
1972 
 
1973 
/*--------------------------------------------------------------------
1974 
 CELL NAME : OR3A
1975 
 CELL TYPE : comb
1976 
 CELL LOGIC : Y = !A + B + C
1977 
---------------------------------------------------------------------*/
1978 
 
1979 
`suppress_faults
1980 
`enable_portfaults
1981 
`celldefine
1982 
`delay_mode_path
1983 
`timescale 1 ns / 100 ps
1984 
 
1985 
module OR3A(Y,A,B,C);
1986 
 input A,B,C;
1987 
 output Y;
1988 
 wire NET_0_0;
1989 
 
1990 
 not    INV_160(A_, A);
1991 
 or       U774(NET_0_0, A_, B);
1992 
 or       U775(Y, NET_0_0, C);
1993 
 
1994 
       specify
1995 
 
1996 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
1997 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
1998 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
1999 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
2000 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
2001 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
2002 
                specparam MacroType = "comb";
2003 
 
2004 
                //pin to pin path delay
2005 
 
2006 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
2007 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
2008 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
2009 
   endspecify
2010 
 
2011 
endmodule
2012 
 
2013 
`endcelldefine
2014 
`disable_portfaults
2015 
`nosuppress_faults
2016 
 
2017 
 
2018 
 
2019 
/*--------------------------------------------------------------------
2020 
 CELL NAME : OR3B
2021 
 CELL TYPE : comb
2022 
 CELL LOGIC : Y = !A + !B + C
2023 
---------------------------------------------------------------------*/
2024 
 
2025 
`suppress_faults
2026 
`enable_portfaults
2027 
`celldefine
2028 
`delay_mode_path
2029 
`timescale 1 ns / 100 ps
2030 
 
2031 
module OR3B(Y,A,B,C);
2032 
 input A,B,C;
2033 
 output Y;
2034 
 wire NET_0_0;
2035 
 
2036 
 not    INV_161(A_, A);
2037 
 not    INV_162(B_, B);
2038 
 or       U779(NET_0_0, A_, B_);
2039 
 or       U780(Y, NET_0_0, C);
2040 
 
2041 
       specify
2042 
 
2043 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
2044 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
2045 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
2046 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
2047 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
2048 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
2049 
                specparam MacroType = "comb";
2050 
 
2051 
                //pin to pin path delay
2052 
 
2053 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
2054 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
2055 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
2056 
   endspecify
2057 
 
2058 
endmodule
2059 
 
2060 
`endcelldefine
2061 
`disable_portfaults
2062 
`nosuppress_faults
2063 
 
2064 
 
2065 
 
2066 
/*--------------------------------------------------------------------
2067 
 CELL NAME : OR3C
2068 
 CELL TYPE : comb
2069 
 CELL LOGIC : Y = !A + !B + !C
2070 
---------------------------------------------------------------------*/
2071 
 
2072 
`suppress_faults
2073 
`enable_portfaults
2074 
`celldefine
2075 
`delay_mode_path
2076 
`timescale 1 ns / 100 ps
2077 
 
2078 
module OR3C(Y,A,B,C);
2079 
 input A,B,C;
2080 
 output Y;
2081 
 wire NET_0_0;
2082 
 
2083 
 not    INV_163(A_, A);
2084 
 not    INV_164(B_, B);
2085 
 not    INV_165(C_, C);
2086 
 or       U784(NET_0_0, A_, B_);
2087 
 or       U785(Y, NET_0_0, C_);
2088 
 
2089 
       specify
2090 
 
2091 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
2092 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
2093 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
2094 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
2095 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
2096 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
2097 
                specparam MacroType = "comb";
2098 
 
2099 
                //pin to pin path delay
2100 
 
2101 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
2102 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
2103 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
2104 
   endspecify
2105 
 
2106 
endmodule
2107 
 
2108 
`endcelldefine
2109 
`disable_portfaults
2110 
`nosuppress_faults
2111 
 
2112 
 
2113 
 
2114 
 
2115 
 
2116 
/*--------------------------------------------------------------------
2117 
 CELL NAME : OAI1
2118 
 CELL TYPE : comb
2119 
 CELL LOGIC : Y = !((A + B) & C)
2120 
---------------------------------------------------------------------*/
2121 
 
2122 
`suppress_faults
2123 
`enable_portfaults
2124 
`celldefine
2125 
`delay_mode_path
2126 
`timescale 1 ns / 100 ps
2127 
 
2128 
module OAI1(Y,A,B,C);
2129 
 input A,B,C;
2130 
 output Y;
2131 
 wire NET_0_0;
2132 
 
2133 
 or       U732(NET_0_0, A, B);
2134 
 nand     U733(Y, NET_0_0, C);
2135 
 
2136 
       specify
2137 
 
2138 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
2139 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
2140 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
2141 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
2142 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
2143 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
2144 
                specparam MacroType = "comb";
2145 
 
2146 
                //pin to pin path delay
2147 
 
2148 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
2149 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
2150 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
2151 
   endspecify
2152 
 
2153 
endmodule
2154 
 
2155 
`endcelldefine
2156 
`disable_portfaults
2157 
`nosuppress_faults
2158 
 
2159 
 
2160 
 
2161 
 
2162 
 
2163 
/*--------------------------------------------------------------------
2164 
 CELL NAME : VCC
2165 
 CELL TYPE : comb
2166 
 CELL LOGIC : Y=1
2167 
---------------------------------------------------------------------*/
2168 
 
2169 
`suppress_faults
2170 
`enable_portfaults
2171 
`celldefine
2172 
`delay_mode_path
2173 
`timescale 1 ns / 100 ps
2174 
 
2175 
module VCC(Y);
2176 
 output Y;
2177 
 
2178 
 supply1    Y;
2179 
 
2180 
       specify
2181 
 
2182 
                specparam MacroType = "comb";
2183 
 
2184 
                //pin to pin path delay
2185 
 
2186 
   endspecify
2187 
 
2188 
endmodule
2189 
 
2190 
`endcelldefine
2191 
`disable_portfaults
2192 
`nosuppress_faults
2193 
 
2194 
 
2195 
 
2196 
/*--------------------------------------------------------------------
2197 
 CELL NAME : XA1B
2198 
 CELL TYPE : comb
2199 
 CELL LOGIC : Y = (A ^ B) & !C
2200 
---------------------------------------------------------------------*/
2201 
 
2202 
`suppress_faults
2203 
`enable_portfaults
2204 
`celldefine
2205 
`delay_mode_path
2206 
`timescale 1 ns / 100 ps
2207 
 
2208 
module XA1B(Y,A,B,C);
2209 
 input A,B,C;
2210 
 output Y;
2211 
 wire NET_0_0;
2212 
 
2213 
 not    INV_173(A_, A);
2214 
 not    INV_174(B_, B);
2215 
 not    INV_175(C_, C);
2216 
 UDP_MUX2   U949(NET_0_0, B, B_, A_);
2217 
 and      U951(Y, NET_0_0, C_);
2218 
 
2219 
       specify
2220 
 
2221 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
2222 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
2223 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
2224 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
2225 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
2226 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
2227 
                specparam MacroType = "comb";
2228 
 
2229 
                //pin to pin path delay
2230 
 
2231 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
2232 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
2233 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
2234 
   endspecify
2235 
 
2236 
endmodule
2237 
 
2238 
`endcelldefine
2239 
`disable_portfaults
2240 
`nosuppress_faults
2241 
 
2242 
 
2243 
 
2244 
 
2245 
/*--------------------------------------------------------------------
2246 
 CELL NAME : XNOR2
2247 
 CELL TYPE : comb
2248 
 CELL LOGIC : Y = !(A ^ B)
2249 
---------------------------------------------------------------------*/
2250 
 
2251 
`suppress_faults
2252 
`enable_portfaults
2253 
`celldefine
2254 
`delay_mode_path
2255 
`timescale 1 ns / 100 ps
2256 
 
2257 
module XNOR2(Y,A,B);
2258 
 input A,B;
2259 
 output Y;
2260 
 
2261 
 not    INV_183(A_, A);
2262 
 not    INV_184(B_, B);
2263 
 UDPN_MUX2  U972(Y, B, B_, A_);
2264 
 
2265 
       specify
2266 
 
2267 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
2268 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
2269 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
2270 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
2271 
                specparam MacroType = "comb";
2272 
 
2273 
                //pin to pin path delay
2274 
 
2275 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
2276 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
2277 
   endspecify
2278 
 
2279 
endmodule
2280 
 
2281 
`endcelldefine
2282 
`disable_portfaults
2283 
`nosuppress_faults
2284 
 
2285 
 
2286 
 
2287 
/*--------------------------------------------------------------------
2288 
 CELL NAME : XNOR3
2289 
 CELL TYPE : comb
2290 
 CELL LOGIC : Y = !(A ^ B ^ C)
2291 
---------------------------------------------------------------------*/
2292 
 
2293 
`suppress_faults
2294 
`enable_portfaults
2295 
`celldefine
2296 
`delay_mode_path
2297 
`timescale 1 ns / 100 ps
2298 
 
2299 
module XNOR3(Y,A,B,C);
2300 
 input A,B,C;
2301 
 output Y;
2302 
 wire NET_0_0;
2303 
 
2304 
 not    INV_187(A_, A);
2305 
 not    INV_188(B_, B);
2306 
 UDP_MUX2   U981(NET_0_0, B, B_, A_);
2307 
 xnor     U983(Y, NET_0_0, C);
2308 
 
2309 
       specify
2310 
 
2311 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
2312 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
2313 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
2314 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
2315 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
2316 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
2317 
                specparam MacroType = "comb";
2318 
 
2319 
                //pin to pin path delay
2320 
 
2321 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
2322 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
2323 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
2324 
   endspecify
2325 
 
2326 
endmodule
2327 
 
2328 
`endcelldefine
2329 
`disable_portfaults
2330 
`nosuppress_faults
2331 
 
2332 
 
2333 
 
2334 
/*--------------------------------------------------------------------
2335 
 CELL NAME : XOR2
2336 
 CELL TYPE : comb
2337 
 CELL LOGIC : Y = A ^ B
2338 
---------------------------------------------------------------------*/
2339 
 
2340 
`suppress_faults
2341 
`enable_portfaults
2342 
`celldefine
2343 
`delay_mode_path
2344 
`timescale 1 ns / 100 ps
2345 
 
2346 
module XOR2(Y,A,B);
2347 
 input A,B;
2348 
 output Y;
2349 
 
2350 
 not    INV_193(A_, A);
2351 
 not    INV_194(B_, B);
2352 
 UDP_MUX2   U998(Y, B, B_, A_);
2353 
 
2354 
       specify
2355 
 
2356 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
2357 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
2358 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
2359 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
2360 
                specparam MacroType = "comb";
2361 
 
2362 
                //pin to pin path delay
2363 
 
2364 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
2365 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
2366 
   endspecify
2367 
 
2368 
endmodule
2369 
 
2370 
`endcelldefine
2371 
`disable_portfaults
2372 
`nosuppress_faults
2373 
 
2374 
 
2375 
 
2376 
/*--------------------------------------------------------------------
2377 
 CELL NAME : ZOR3
2378 
 CELL TYPE : comb
2379 
 CELL LOGIC : Y = A & B & C + !A & !B & !C
2380 
---------------------------------------------------------------------*/
2381 
 
2382 
`suppress_faults
2383 
`enable_portfaults
2384 
`celldefine
2385 
`delay_mode_path
2386 
`timescale 1 ns / 100 ps
2387 
 
2388 
module ZOR3(Y,A,B,C);
2389 
 input A,B,C;
2390 
 output Y;
2391 
 wire NET_0_0, NET_0_1, NET_0_2, NET_0_3;
2392 
 
2393 
 not    INV_199(A_, A);
2394 
 not    INV_200(B_, B);
2395 
 not    INV_201(C_, C);
2396 
 and      U1013(NET_0_0, A, B);
2397 
 UDP_MUX2   U1014(Y, NET_0_0, NET_0_2, C);
2398 
 and      U1017(NET_0_2, A_, B_);
2399 
 
2400 
       specify
2401 
 
2402 
                specparam tpdLH_A_to_Y = (0.1:0.1:0.1);
2403 
                specparam tpdHL_A_to_Y = (0.1:0.1:0.1);
2404 
                specparam tpdLH_B_to_Y = (0.1:0.1:0.1);
2405 
                specparam tpdHL_B_to_Y = (0.1:0.1:0.1);
2406 
                specparam tpdLH_C_to_Y = (0.1:0.1:0.1);
2407 
                specparam tpdHL_C_to_Y = (0.1:0.1:0.1);
2408 
                specparam MacroType = "comb";
2409 
 
2410 
                //pin to pin path delay
2411 
 
2412 
                (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );
2413 
                (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y );
2414 
                (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y );
2415 
   endspecify
2416 
 
2417 
endmodule
2418 
 
2419 
`endcelldefine
2420 
`disable_portfaults
2421 
`nosuppress_faults
2422 
 
2423 
 

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