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[/] [sdcard_mass_storage_controller/] [trunk/] [bench/] [sdc_dma/] [verilog/] [sdModel.v] - Blame information for rev 125

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//`include "timescale.v"
`include "SD_defines.v"
`define tTLH 10 //Clock rise time
`define tHL 10 //Clock fall time
`define tISU 6 //Input setup time
`define tIH 0 //Input hold time
`define tODL 14 //Output delay
`define DLY_TO_OUTP 47
 
`define BLOCKSIZE 512
`define MEMSIZE 2048 // 4 block
`define BLOCK_BUFFER_SIZE 1
`define TIME_BUSY 64
 
`define PRG 7
`define RCV 6
`define DATAS 5
`define TRAN 4
module sdModel(
  input sdClk,
  tri cmd,
  tri [3:0] dat
 
);
 
 
reg oeCmd;
reg oeDat;
reg cmdOut;
reg [3:0] datOut;
reg [10:0] transf_cnt;
 
 
 
reg [5:0] lastCMD;
reg cardIdentificationState;
reg CardTransferActive;
reg [2:0] BusWidth;
 
assign cmd = oeCmd ? cmdOut : 1'bz;
assign dat = oeDat ? datOut : 4'bz;
 
reg InbuffStatus;
reg [31:0] BlockAddr;
reg [7:0] Inbuff [0:511];
reg [7:0] FLASHmem [0:`MEMSIZE];
 
 
reg [46:0]inCmd;
reg [5:0]cmdRead;
reg [7:0] cmdWrite;
reg crcIn;
reg crcEn;
reg crcRst;
reg [31:0] CardStatus;
reg [15:0] RCA;
reg [31:0] OCR;
reg [120:0] CID;
reg Busy; //0 when busy
wire [6:0] crcOut;
reg [4:0] crc_c;
 
reg [3:0] CurrentState;
reg [3:0] DataCurrentState;
`define RCASTART 16'h20
`define OCRSTART 32'hff8000
`define STATUSSTART 32'h0
`define CIDSTART 128'h00ffffffddddddddaaaaaaaa99999999  //Just some random data not really usefull anyway 
 
`define outDelay 4
reg [2:0] outDelayCnt;
reg [9:0] flash_write_cnt;
reg [8:0] flash_blockwrite_cnt;
 
parameter SIZE = 10;
parameter CONTENT_SIZE = 40;
parameter
    IDLE   =  10'b0000_0000_01,
    READ_CMD   =  10'b0000_0000_10,
    ANALYZE_CMD     =  10'b0000_0001_00,
    SEND_CMD        =  10'b0000_0010_00;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
 
parameter
    DATA_IDLE   =10'b0000_0000_01,
    READ_WAITS  =10'b0000_0000_10,
    READ_DATA  = 10'b0000_0001_00,
    WRITE_FLASH =10'b0000_0010_00,
    WRITE_DATA  =10'b0000_0100_00;
parameter okcrctoken = 4'b0101;
parameter invalidcrctoken = 4'b1111;
reg [SIZE-1:0] dataState;
reg [SIZE-1:0] next_datastate;
 
reg ValidCmd;
reg inValidCmd;
 
reg [7:0] response_S;
reg [135:0] response_CMD;
integer responseType;
 
     reg [9:0] block_cnt;
     reg wptr;
     reg crc_ok;
     reg [3:0] last_din;
 
 
 
reg crcDat_rst;
reg crcDat_en;
reg [3:0] crcDat_in;
wire [15:0] crcDat_out [3:0];
 
genvar i;
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen
  SD_CRC_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);
end
endgenerate
SD_CRC_7 CRC_7(
crcIn,
crcEn,
sdClk,
crcRst,
crcOut);
 
 
reg appendCrc;
reg [5:0] startUppCnt;
 
reg q_start_bit;
//Card initinCMd
initial $readmemh("FLASH.txt",FLASHmem);
 
integer k;
initial begin
        $display("Contents of Mem after reading data file:");
        for (k=0; k<10; k=k+1) $display("%d:%h",k,FLASHmem[k]);
end
reg qCmd;
reg [2:0] crcCnt;
 
reg add_wrong_cmd_crc;
reg add_wrong_cmd_indx;
reg add_wrong_data_crc;
 
initial begin
  add_wrong_data_crc<=0;
  add_wrong_cmd_indx<=0;
  add_wrong_cmd_crc<=0;
  cardIdentificationState<=1;
  state<=IDLE;
  dataState<=DATA_IDLE;
  Busy<=0;
  oeCmd<=0;
  crcCnt<=0;
  CardTransferActive<=0;
  qCmd<=1;
  oeDat<=0;
  cmdOut<=0;
  cmdWrite<=0;
  InbuffStatus<=0;
  datOut<=0;
  inCmd<=0;
  BusWidth<=1;
  responseType=0;
  crcIn<=0;
  response_S<=0;
  crcEn<=0;
  crcRst<=0;
  cmdRead<=0;
  ValidCmd<=0;
  inValidCmd=0;
  appendCrc<=0;
  RCA<= `RCASTART;
  OCR<= `OCRSTART;
  CardStatus <= `STATUSSTART;
  CID<=`CIDSTART;
  response_CMD<=0;
  outDelayCnt<=0;
  crcDat_rst<=1;
  crcDat_en<=0;
  crcDat_in<=0;
  transf_cnt<=0;
  BlockAddr<=0;
  block_cnt <=0;
  wptr<=0;
  transf_cnt<=0;
  crcDat_rst<=1;
  crcDat_en<=0;
  crcDat_in<=0;
  flash_write_cnt<=0;
  flash_blockwrite_cnt<=0;
end
 
//CARD logic
 
always @ (state or cmd or cmdRead or ValidCmd or inValidCmd or cmdWrite or outDelayCnt)
begin : FSM_COMBO
 next_state  = 0;
case(state)
IDLE: begin
   if (!cmd)
     next_state = READ_CMD;
  else
     next_state = IDLE;
end
READ_CMD: begin
  if (cmdRead>= 47)
     next_state = ANALYZE_CMD;
  else
     next_state =  READ_CMD;
 end
 ANALYZE_CMD: begin
  if ((ValidCmd  )   && (outDelayCnt >= `outDelay ))
     next_state = SEND_CMD;
  else if (inValidCmd)
     next_state =  IDLE;
 else
    next_state =  ANALYZE_CMD;
 end
 SEND_CMD: begin
    if (cmdWrite>= response_S)
     next_state = IDLE;
  else
     next_state =  SEND_CMD;
 
 end
 
 
 endcase
end
 
always @ (dataState or CardStatus or crc_c or flash_write_cnt or dat[0] )
begin : FSM_COMBODAT
 next_datastate  = 0;
case(dataState)
 DATA_IDLE: begin
   if (CardStatus[12:9]==`RCV )
     next_datastate = READ_WAITS;
   else if (CardStatus[12:9]==`DATAS )
     next_datastate = WRITE_DATA;
   else
     next_datastate = DATA_IDLE;
 end
 
 READ_WAITS: begin
   if ( dat[0] == 1'b0 )
     next_datastate =  READ_DATA;
   else
     next_datastate =  READ_WAITS;
 end
 
 READ_DATA : begin
  if (crc_c==0  )
     next_datastate =  WRITE_FLASH;
  else
     next_datastate =  READ_DATA;
 end
  WRITE_FLASH : begin
  if (flash_write_cnt>265 )
     next_datastate =  DATA_IDLE;
  else
     next_datastate =  WRITE_FLASH;
end
  WRITE_DATA : begin
    if (transf_cnt >= `BIT_BLOCK)
       next_datastate= DATA_IDLE;
    else
       next_datastate=WRITE_DATA;
  end
 
 
 
 
 
 endcase
end
 
always @ (posedge sdClk  )
 begin
 
    q_start_bit <= dat[0];
 end
 
always @ (posedge sdClk  )
begin : FSM_SEQ
    state <= next_state;
end
 
always @ (posedge sdClk  )
begin : FSM_SEQDAT
    dataState <= next_datastate;
end
 
 
 
always @ (posedge sdClk) begin
if (CardTransferActive) begin
 if (InbuffStatus==0) //empty
   CardStatus[8]<=1;
  else
   CardStatus[8]<=0;
  end
else
  CardStatus[8]<=0;
 
 startUppCnt<=startUppCnt+1;
 OCR[31]<=Busy;
 if (startUppCnt == `TIME_BUSY)
   Busy <=1;
end
 
 
always @ (posedge sdClk) begin
   qCmd<=cmd;
end
 
//read data and cmd on rising edge
always @ (posedge sdClk) begin
 case(state)
   IDLE: begin
 
      crcIn<=0;
      crcEn<=0;
      crcRst<=1;
      oeCmd<=0;
 
      cmdRead<=0;
      appendCrc<=0;
      ValidCmd<=0;
      inValidCmd=0;
      cmdWrite<=0;
      crcCnt<=0;
      response_CMD<=0;
      response_S<=0;
      outDelayCnt<=0;
      responseType=0;
    end
   READ_CMD: begin //read cmd
      crcEn<=1;
      crcRst<=0;
      crcIn <= #`tIH qCmd;
      inCmd[47-cmdRead]  <= #`tIH qCmd;
      cmdRead <= #1 cmdRead+1;
      if (cmdRead >= 40)
         crcEn<=0;
 
      if (cmdRead == 46) begin
          oeCmd<=1;
     cmdOut<=1;
      end
   end
 
   ANALYZE_CMD: begin//check for valid cmd
   //Wrong CRC go idle
    if (inCmd[46] == 0) //start
      inValidCmd=1;
    else if (inCmd[7:1] != crcOut) begin
      inValidCmd=1;
      $fdisplay(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
      $display(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
    end
    else if  (inCmd[0] != 1)  begin//stop 
      inValidCmd=1;
      $fdisplay(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
      $display(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
    end
    else begin
      if(outDelayCnt ==0)
        CardStatus[3]<=0;
      case(inCmd[45:40])
 
        2 : response_S <= 136;
        3 : response_S <= 48;
        7 : response_S <= 48;
        8 : response_S <= 0;
        14 : response_S <= 0;
        16 : response_S <= 48;
        17 : response_S <= 48;
        24 : response_S <= 48;
        33 : response_S <= 48;
        55 : response_S <= 48;
        41 : response_S <= 48;
    endcase
         case(inCmd[45:40])
 
            response_CMD <= 0;
            cardIdentificationState<=1;
            ResetCard;
        end
        2 : begin
         if (lastCMD != 41 && outDelayCnt==0) begin
               $fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
               //$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
               CardStatus[3]<=1;
            end
        response_CMD[127:8] <= CID;
        appendCrc<=0;
        CardStatus[12:9] <=2;
        end
        3 :  begin
           if (lastCMD != 2 && outDelayCnt==0 ) begin
               $fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
               //$display(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
               CardStatus[3]<=1;
            end
        response_CMD[127:112] <= RCA[15:0] ;
        response_CMD[111:96] <= CardStatus[15:0] ;
        appendCrc<=1;
        CardStatus[12:9] <=3;
        cardIdentificationState<=0;
       end
        6 : begin
           if (lastCMD == 55 && outDelayCnt==0) begin
              if (inCmd[9:8] == 2'b10) begin
               BusWidth <=4;
                    $display(sdModel_file_desc, "**BUS WIDTH 4 ") ;
               end
              else
               BusWidth <=1;
 
              response_S<=48;
              response_CMD[127:96] <= CardStatus;
           end
           else if (outDelayCnt==0)begin
             response_CMD <= 0;
             response_S<=0;
             $fdisplay(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
           //  $display(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
            end
        end
        7: begin
         if (outDelayCnt==0) begin
          if (inCmd[39:24]== RCA[15:0]) begin
              CardTransferActive <= 1;
              response_CMD[127:96] <= CardStatus ;
              CardStatus[12:9] <=`TRAN;
          end
          else begin
               CardTransferActive <= 0;
               response_CMD[127:96] <= CardStatus ;
               CardStatus[12:9] <=3;
          end
         end
        end
        8 : response_CMD[127:96] <= 0; //V1.0 card
        16 : begin
          response_CMD[127:96] <= CardStatus ;
 
        end
        17 :  begin
          if (outDelayCnt==0) begin
            if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate                               
                CardStatus[12:9] <=`DATAS;//Put card in data state
                response_CMD[127:96] <= CardStatus ;
                BlockAddr = inCmd[39:8];
                if (BlockAddr%512 !=0)
                  $display("**Block Misalign Error");
          end
           else begin
             response_S <= 0;
             response_CMD[127:96] <= 0;
           end
         end
 
       end
 
        24 : begin
          if (outDelayCnt==0) begin
            if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
              if (CardStatus[8]) begin //If Free write buffer           
                CardStatus[12:9] <=`RCV;//Put card in Rcv state
                response_CMD[127:96] <= CardStatus ;
                BlockAddr = inCmd[39:8];
                if (BlockAddr%512 !=0)
                  $display("**Block Misalign Error");
              end
              else begin
                response_CMD[127:96] <= CardStatus;
                 $fdisplay(sdModel_file_desc, "**Error Try to blockwrite when No Free Writebuffer") ;
                 $display("**Error Try to blockwrite when No Free Writebuffer") ;
             end
           end
           else begin
             response_S <= 0;
             response_CMD[127:96] <= 0;
           end
         end
 
       end
        33 : response_CMD[127:96] <= 48;
        55 :
        begin
          response_CMD[127:96] <= CardStatus ;
          CardStatus[5] <=1;      //Next CMD is AP specific CMD
          appendCrc<=1;
        end
        41 :
        begin
         if (cardIdentificationState) begin
            if (lastCMD != 55 && outDelayCnt==0) begin
               $fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
               $display( "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
               CardStatus[3]<=1;
            end
            else begin
             responseType=3;
             response_CMD[127:96] <= OCR;
             appendCrc<=0;
             CardStatus[5] <=0;
            if (Busy==1)
              CardStatus[12:9] <=1;
           end
        end
       end
 
    endcase
     ValidCmd<=1;
     crcIn<=0;
 
     outDelayCnt<=outDelayCnt+1;
     if (outDelayCnt==`outDelay)
       crcRst<=1;
     oeCmd<=1;
     cmdOut<=1;
     response_CMD[135:134] <=0;
 
    if (responseType != 3)
       if (!add_wrong_cmd_indx)
         response_CMD[133:128] <=inCmd[45:40];
      else
         response_CMD[133:128] <=0;
 
    if (responseType == 3)
       response_CMD[133:128] <=6'b111111;
 
     lastCMD <=inCmd[45:40];
    end
   end
 
 
 
 endcase
end
 
always @ ( negedge sdClk) begin
 case(state)
 
SEND_CMD: begin
     crcRst<=0;
     crcEn<=1;
    cmdWrite<=cmdWrite+1;
    if (response_S!=0)
     cmdOut<=0;
   else
      cmdOut<=1;
 
    if ((cmdWrite>0) &&  (cmdWrite < response_S-8)) begin
      cmdOut<=response_CMD[135-cmdWrite];
      crcIn<=response_CMD[134-cmdWrite];
      if (cmdWrite >= response_S-9)
       crcEn<=0;
    end
   else if (cmdWrite!=0) begin
     crcEn<=0;
     if (add_wrong_cmd_crc) begin
        cmdOut<=0;
        crcCnt<=crcCnt+1;
     end
     else begin
     cmdOut<=crcOut[6-crcCnt];
     crcCnt<=crcCnt+1;
     if (responseType == 3)
           cmdOut<=1;
    end
   end
  if (cmdWrite == response_S-1)
    cmdOut<=1;
 
  end
 endcase
end
 
 
 
integer outdly_cnt;
 
 
 
 
 
 
 
always @ (posedge sdClk) begin
 
  case (dataState)
  DATA_IDLE: begin
 
  end
 
  READ_WAITS: begin
      oeDat<=0;
      crcDat_rst<=0;
      crcDat_en<=1;
      crcDat_in<=0;
      crc_c<=15;//
      crc_ok<=1;
  end
  READ_DATA: begin
 
 
    InbuffStatus<=1;
    if (transf_cnt<`BIT_BLOCK_REC) begin
       if (wptr)
         Inbuff[block_cnt][7:4] <= dat;
       else
          Inbuff[block_cnt][3:0] <= dat;
 
       if (!add_wrong_data_crc)
          crcDat_in<=dat;
        else
          crcDat_in<=4'b1010;
 
       crc_ok<=1;
       transf_cnt<=transf_cnt+1;
       if (wptr)
         block_cnt<=block_cnt+1;
       wptr<=~wptr;
 
 
    end
    else if  ( transf_cnt <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE-1)) begin
       transf_cnt<=transf_cnt+1;
       crcDat_en<=0;
       last_din <=dat;
 
       if (transf_cnt> `BIT_BLOCK_REC) begin
        crc_c<=crc_c-1;
 
          if (crcDat_out[0][crc_c] != last_din[0])
           crc_ok<=0;
          if  (crcDat_out[1][crc_c] != last_din[1])
           crc_ok<=0;
          if  (crcDat_out[2][crc_c] != last_din[2])
           crc_ok<=0;
          if  (crcDat_out[3][crc_c] != last_din[3])
           crc_ok<=0;
      end
    end
  end
  WRITE_FLASH: begin
     oeDat<=1;
     block_cnt <=0;
     wptr<=0;
     transf_cnt<=0;
     crcDat_rst<=1;
     crcDat_en<=0;
     crcDat_in<=0;
 
 
  end
 
  endcase
 
 
end
 
 
 
reg data_send_index;
integer write_out_index;
always @ (negedge sdClk) begin
 
  case (dataState)
  DATA_IDLE: begin
     write_out_index<=0;
     transf_cnt<=0;
     data_send_index<=0;
     outdly_cnt<=0;
 
  end
 
 
   WRITE_DATA: begin
      oeDat<=1;
      outdly_cnt<=outdly_cnt+1;
 
      if ( outdly_cnt > `DLY_TO_OUTP) begin
         transf_cnt <= transf_cnt+1;
         crcDat_en<=1;
         crcDat_rst<=0;
 
      end
      else begin
        crcDat_en<=0;
        crcDat_rst<=1;
        oeDat<=1;
        crc_c<=16;
     end
 
       if (transf_cnt==1) begin
 
          last_din <= FLASHmem[BlockAddr+(write_out_index)][7:4];
          datOut<=0;
          crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
          data_send_index<=1;
        end
        else if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) begin
          data_send_index<=~data_send_index;
          if (!data_send_index) begin
             last_din<=FLASHmem[BlockAddr+(write_out_index)][7:4];
             crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
          end
          else begin
             last_din<=FLASHmem[BlockAddr+(write_out_index)][3:0];
             if (!add_wrong_data_crc)
               crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][3:0];
             else
               crcDat_in<=4'b1010;
             write_out_index<=write_out_index+1;
 
         end
 
 
          datOut<= last_din;
 
 
          if ( transf_cnt >=`BIT_BLOCK-`CRC_OFF ) begin
             crcDat_en<=0;
         end
 
       end
       else if (transf_cnt>`BIT_BLOCK-`CRC_OFF & crc_c!=0) begin
         datOut<= last_din;
         crcDat_en<=0;
         crc_c<=crc_c-1;
         if (crc_c<= 16) begin
         datOut[0]<=crcDat_out[0][crc_c-1];
         datOut[1]<=crcDat_out[1][crc_c-1];
         datOut[2]<=crcDat_out[2][crc_c-1];
         datOut[3]<=crcDat_out[3][crc_c-1];
       end
       end
       else if (transf_cnt==`BIT_BLOCK-2) begin
          datOut<=4'b1111;
      end
       else if ((transf_cnt !=0) && (crc_c == 0 ))begin
         oeDat<=0;
         CardStatus[12:9] <= `TRAN;
         end
 
 
 
  end
 
 
 
  WRITE_FLASH: begin
    flash_write_cnt<=flash_write_cnt+1;
     CardStatus[12:9] <= `PRG;
      datOut[0]<=0;
       datOut[1]<=1;
       datOut[2]<=1;
       datOut[3]<=1;
    if (flash_write_cnt == 0)
      datOut<=1;
    else if(flash_write_cnt == 1)
     datOut[0]<=1;
    else if(flash_write_cnt == 2)
     datOut[0]<=0;
 
 
    else if ((flash_write_cnt > 2) && (flash_write_cnt < 7)) begin
      if (crc_ok)
        datOut[0] <=okcrctoken[6-flash_write_cnt];
      else
        datOut[0] <= invalidcrctoken[6-flash_write_cnt];
    end
    else if  ((flash_write_cnt >= 7) && (flash_write_cnt < 264)) begin
       datOut[0]<=0;
 
      flash_blockwrite_cnt<=flash_blockwrite_cnt+2;
       FLASHmem[BlockAddr+(flash_blockwrite_cnt)]<=Inbuff[flash_blockwrite_cnt];
       FLASHmem[BlockAddr+(flash_blockwrite_cnt+1)]<=Inbuff[flash_blockwrite_cnt+1];
    end
    else begin
      datOut<=1;
      InbuffStatus<=0;
      CardStatus[12:9] <= `TRAN;
    end
  end
endcase
end
 
integer sdModel_file_desc;
 
initial
begin
  sdModel_file_desc = $fopen("log/sd_model.log");
  if (sdModel_file_desc < 2)
  begin
    $display("*E Could not open/create testbench log file in /log/ directory!");
    $finish;
  end
end
 
task ResetCard; //  MAC registers
begin
   add_wrong_data_crc<=0;
  add_wrong_cmd_indx<=0;
  add_wrong_cmd_crc<=0;
 cardIdentificationState<=1;
  state<=IDLE;
  dataState<=DATA_IDLE;
  Busy<=0;
  oeCmd<=0;
  crcCnt<=0;
  CardTransferActive<=0;
  qCmd<=1;
  oeDat<=0;
  cmdOut<=0;
  cmdWrite<=0;
 
  InbuffStatus<=0;
  datOut<=0;
  inCmd<=0;
  BusWidth<=1;
  responseType=0;
  crcIn<=0;
  response_S<=0;
  crcEn<=0;
  crcRst<=0;
  cmdRead<=0;
  ValidCmd<=0;
  inValidCmd=0;
  appendCrc<=0;
  RCA<= `RCASTART;
  OCR<= `OCRSTART;
  CardStatus <= `STATUSSTART;
  CID<=`CIDSTART;
  response_CMD<=0;
  outDelayCnt<=0;
  crcDat_rst<=1;
  crcDat_en<=0;
  crcDat_in<=0;
  transf_cnt<=0;
  BlockAddr<=0;
  block_cnt <=0;
     wptr<=0;
     transf_cnt<=0;
     crcDat_rst<=1;
     crcDat_en<=0;
     crcDat_in<=0;
flash_write_cnt<=0;
flash_blockwrite_cnt<=0;
end
endtask
 
 
endmodule

Line No.	Rev	Author	Line
1	79	tac2	//`include "timescale.v"
2	96	tac2	`include "SD_defines.v"
3	79	tac2	`define tTLH 10 //Clock rise time
4			`define tHL 10 //Clock fall time
5			`define tISU 6 //Input setup time
6			`define tIH 0 //Input hold time
7			`define tODL 14 //Output delay
8	98	tac2	`define DLY_TO_OUTP 47
9	79	tac2
10			`define BLOCKSIZE 512
11	96	tac2	`define MEMSIZE 2048 // 4 block
12	79	tac2	`define BLOCK_BUFFER_SIZE 1
13			`define TIME_BUSY 64
14
15	96	tac2	`define PRG 7
16			`define RCV 6
17			`define DATAS 5
18			`define TRAN 4
19	79	tac2	`module sdModel(`
20			`input sdClk,`
21			`tri cmd,`
22			`tri [3:0] dat`
23
24			`);`
25
26
27			`reg oeCmd;`
28			`reg oeDat;`
29			`reg cmdOut;`
30	96	tac2	`reg [3:0] datOut;`
31			`reg [10:0] transf_cnt;`
32	79	tac2
33	96	tac2
34
35	79	tac2	`reg [5:0] lastCMD;`
36			`reg cardIdentificationState;`
37	96	tac2	`reg CardTransferActive;`
38			`reg [2:0] BusWidth;`
39	79	tac2
40			`assign cmd = oeCmd ? cmdOut : 1'bz;`
41			`assign dat = oeDat ? datOut : 4'bz;`
42
43	96	tac2	`reg InbuffStatus;`
44			`reg [31:0] BlockAddr;`
45			`reg [7:0] Inbuff [0:511];`
46			reg [7:0] FLASHmem [0:`MEMSIZE];
47	79	tac2
48
49			`reg [46:0]inCmd;`
50			`reg [5:0]cmdRead;`
51			`reg [7:0] cmdWrite;`
52			`reg crcIn;`
53			`reg crcEn;`
54			`reg crcRst;`
55			`reg [31:0] CardStatus;`
56			`reg [15:0] RCA;`
57			`reg [31:0] OCR;`
58			`reg [120:0] CID;`
59			`reg Busy; //0 when busy`
60			`wire [6:0] crcOut;`
61	102	tac2	`reg [4:0] crc_c;`
62	96	tac2
63			`reg [3:0] CurrentState;`
64			`reg [3:0] DataCurrentState;`
65	79	tac2	`define RCASTART 16'h20
66			`define OCRSTART 32'hff8000
67			`define STATUSSTART 32'h0
68			`define CIDSTART 128'h00ffffffddddddddaaaaaaaa99999999 //Just some random data not really usefull anyway
69
70			`define outDelay 4
71			`reg [2:0] outDelayCnt;`
72	96	tac2	`reg [9:0] flash_write_cnt;`
73			`reg [8:0] flash_blockwrite_cnt;`
74
75	79	tac2	`parameter SIZE = 10;`
76			`parameter CONTENT_SIZE = 40;`
77			`parameter`
78			`IDLE = 10'b0000_0000_01,`
79			`READ_CMD = 10'b0000_0000_10,`
80			`ANALYZE_CMD = 10'b0000_0001_00,`
81			`SEND_CMD = 10'b0000_0010_00;`
82			`reg [SIZE-1:0] state;`
83			`reg [SIZE-1:0] next_state;`
84
85	96	tac2	`parameter`
86			`DATA_IDLE =10'b0000_0000_01,`
87			`READ_WAITS =10'b0000_0000_10,`
88			`READ_DATA = 10'b0000_0001_00,`
89			`WRITE_FLASH =10'b0000_0010_00,`
90			`WRITE_DATA =10'b0000_0100_00;`
91			`parameter okcrctoken = 4'b0101;`
92			`parameter invalidcrctoken = 4'b1111;`
93			`reg [SIZE-1:0] dataState;`
94			`reg [SIZE-1:0] next_datastate;`
95
96	79	tac2	`reg ValidCmd;`
97			`reg inValidCmd;`
98
99			`reg [7:0] response_S;`
100			`reg [135:0] response_CMD;`
101			`integer responseType;`
102	96	tac2
103			`reg [9:0] block_cnt;`
104			`reg wptr;`
105			`reg crc_ok;`
106			`reg [3:0] last_din;`
107
108
109
110			`reg crcDat_rst;`
111			`reg crcDat_en;`
112			`reg [3:0] crcDat_in;`
113			`wire [15:0] crcDat_out [3:0];`
114
115			`genvar i;`
116			`generate`
117			`for(i=0; i<4; i=i+1) begin:CRC_16_gen`
118	97	tac2	`SD_CRC_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);`
119	96	tac2	`end`
120			`endgenerate`
121			`SD_CRC_7 CRC_7(`
122	79	tac2	`crcIn,`
123			`crcEn,`
124			`sdClk,`
125			`crcRst,`
126			`crcOut);`
127	96	tac2
128
129	79	tac2	`reg appendCrc;`
130			`reg [5:0] startUppCnt;`
131
132	96	tac2	`reg q_start_bit;`
133	79	tac2	`//Card initinCMd`
134			`initial $readmemh("FLASH.txt",FLASHmem);`
135
136			`integer k;`
137			`initial begin`
138			`$display("Contents of Mem after reading data file:");`
139			`for (k=0; k<10; k=k+1) $display("%d:%h",k,FLASHmem[k]);`
140			`end`
141			`reg qCmd;`
142			`reg [2:0] crcCnt;`
143	125	tac2
144			`reg add_wrong_cmd_crc;`
145			`reg add_wrong_cmd_indx;`
146			`reg add_wrong_data_crc;`
147
148	79	tac2	`initial begin`
149	125	tac2	`add_wrong_data_crc<=0;`
150			`add_wrong_cmd_indx<=0;`
151			`add_wrong_cmd_crc<=0;`
152	79	tac2	`cardIdentificationState<=1;`
153			`state<=IDLE;`
154	96	tac2	`dataState<=DATA_IDLE;`
155	79	tac2	`Busy<=0;`
156			`oeCmd<=0;`
157			`crcCnt<=0;`
158	96	tac2	`CardTransferActive<=0;`
159	79	tac2	`qCmd<=1;`
160			`oeDat<=0;`
161			`cmdOut<=0;`
162	98	tac2	`cmdWrite<=0;`
163	96	tac2	`InbuffStatus<=0;`
164	79	tac2	`datOut<=0;`
165			`inCmd<=0;`
166	96	tac2	`BusWidth<=1;`
167	79	tac2	`responseType=0;`
168			`crcIn<=0;`
169			`response_S<=0;`
170			`crcEn<=0;`
171			`crcRst<=0;`
172			`cmdRead<=0;`
173			`ValidCmd<=0;`
174			`inValidCmd=0;`
175			`appendCrc<=0;`
176			RCA<= `RCASTART;
177			OCR<= `OCRSTART;
178			CardStatus <= `STATUSSTART;
179			CID<=`CIDSTART;
180			`response_CMD<=0;`
181			`outDelayCnt<=0;`
182	96	tac2	`crcDat_rst<=1;`
183			`crcDat_en<=0;`
184			`crcDat_in<=0;`
185			`transf_cnt<=0;`
186			`BlockAddr<=0;`
187			`block_cnt <=0;`
188	98	tac2	`wptr<=0;`
189			`transf_cnt<=0;`
190			`crcDat_rst<=1;`
191			`crcDat_en<=0;`
192			`crcDat_in<=0;`
193			`flash_write_cnt<=0;`
194			`flash_blockwrite_cnt<=0;`
195	79	tac2	`end`
196
197			`//CARD logic`
198
199			`always @ (state or cmd or cmdRead or ValidCmd or inValidCmd or cmdWrite or outDelayCnt)`
200			`begin : FSM_COMBO`
201			`next_state = 0;`
202			`case(state)`
203			`IDLE: begin`
204			`if (!cmd)`
205			`next_state = READ_CMD;`
206			`else`
207			`next_state = IDLE;`
208			`end`
209			`READ_CMD: begin`
210			`if (cmdRead>= 47)`
211			`next_state = ANALYZE_CMD;`
212			`else`
213			`next_state = READ_CMD;`
214			`end`
215			`ANALYZE_CMD: begin`
216			if ((ValidCmd ) && (outDelayCnt >= `outDelay ))
217			`next_state = SEND_CMD;`
218			`else if (inValidCmd)`
219			`next_state = IDLE;`
220			`else`
221			`next_state = ANALYZE_CMD;`
222			`end`
223			`SEND_CMD: begin`
224			`if (cmdWrite>= response_S)`
225			`next_state = IDLE;`
226			`else`
227			`next_state = SEND_CMD;`
228
229			`end`
230
231
232			`endcase`
233			`end`
234
235	98	tac2	`always @ (dataState or CardStatus or crc_c or flash_write_cnt or dat[0] )`
236	96	tac2	`begin : FSM_COMBODAT`
237			`next_datastate = 0;`
238			`case(dataState)`
239			`DATA_IDLE: begin`
240			if (CardStatus[12:9]==`RCV )
241			`next_datastate = READ_WAITS;`
242			else if (CardStatus[12:9]==`DATAS )
243			`next_datastate = WRITE_DATA;`
244			`else`
245			`next_datastate = DATA_IDLE;`
246			`end`
247
248			`READ_WAITS: begin`
249	98	tac2	`if ( dat[0] == 1'b0 )`
250	96	tac2	`next_datastate = READ_DATA;`
251			`else`
252			`next_datastate = READ_WAITS;`
253			`end`
254
255			`READ_DATA : begin`
256			`if (crc_c==0 )`
257			`next_datastate = WRITE_FLASH;`
258			`else`
259			`next_datastate = READ_DATA;`
260			`end`
261			`WRITE_FLASH : begin`
262			`if (flash_write_cnt>265 )`
263			`next_datastate = DATA_IDLE;`
264			`else`
265			`next_datastate = WRITE_FLASH;`
266	98	tac2	`end`
267			`WRITE_DATA : begin`
268			if (transf_cnt >= `BIT_BLOCK)
269			`next_datastate= DATA_IDLE;`
270			`else`
271			`next_datastate=WRITE_DATA;`
272			`end`
273	96	tac2
274
275
276
277
278			`endcase`
279			`end`
280
281	79	tac2	`always @ (posedge sdClk )`
282	96	tac2	`begin`
283
284			`q_start_bit <= dat[0];`
285			`end`
286
287			`always @ (posedge sdClk )`
288	79	tac2	`begin : FSM_SEQ`
289	96	tac2	`state <= next_state;`
290	79	tac2	`end`
291
292	96	tac2	`always @ (posedge sdClk )`
293			`begin : FSM_SEQDAT`
294			`dataState <= next_datastate;`
295			`end`
296	79	tac2
297	96	tac2
298
299	79	tac2	`always @ (posedge sdClk) begin`
300	96	tac2	`if (CardTransferActive) begin`
301			`if (InbuffStatus==0) //empty`
302			`CardStatus[8]<=1;`
303			`else`
304			`CardStatus[8]<=0;`
305			`end`
306			`else`
307			`CardStatus[8]<=0;`
308
309	79	tac2	`startUppCnt<=startUppCnt+1;`
310			`OCR[31]<=Busy;`
311			if (startUppCnt == `TIME_BUSY)
312			`Busy <=1;`
313			`end`
314
315
316			`always @ (posedge sdClk) begin`
317			`qCmd<=cmd;`
318			`end`
319
320			`//read data and cmd on rising edge`
321			`always @ (posedge sdClk) begin`
322			`case(state)`
323			`IDLE: begin`
324
325			`crcIn<=0;`
326			`crcEn<=0;`
327			`crcRst<=1;`
328			`oeCmd<=0;`
329	98	tac2
330	79	tac2	`cmdRead<=0;`
331			`appendCrc<=0;`
332			`ValidCmd<=0;`
333			`inValidCmd=0;`
334			`cmdWrite<=0;`
335			`crcCnt<=0;`
336			`response_CMD<=0;`
337			`response_S<=0;`
338			`outDelayCnt<=0;`
339			`responseType=0;`
340			`end`
341			`READ_CMD: begin //read cmd`
342			`crcEn<=1;`
343			`crcRst<=0;`
344			crcIn <= #`tIH qCmd;
345			inCmd[47-cmdRead] <= #`tIH qCmd;
346			`cmdRead <= #1 cmdRead+1;`
347			`if (cmdRead >= 40)`
348			`crcEn<=0;`
349
350			`if (cmdRead == 46) begin`
351			`oeCmd<=1;`
352			`cmdOut<=1;`
353			`end`
354			`end`
355
356			`ANALYZE_CMD: begin//check for valid cmd`
357			`//Wrong CRC go idle`
358			`if (inCmd[46] == 0) //start`
359			`inValidCmd=1;`
360			`else if (inCmd[7:1] != crcOut) begin`
361			`inValidCmd=1;`
362			`$fdisplay(sdModel_file_desc, "**sd_Model Commando CRC Error") ;`
363			`$display(sdModel_file_desc, "**sd_Model Commando CRC Error") ;`
364			`end`
365			`else if (inCmd[0] != 1) begin//stop`
366			`inValidCmd=1;`
367			`$fdisplay(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;`
368			`$display(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;`
369			`end`
370			`else begin`
371	96	tac2	`if(outDelayCnt ==0)`
372			`CardStatus[3]<=0;`
373	79	tac2	`case(inCmd[45:40])`
374
375			`2 : response_S <= 136;`
376			`3 : response_S <= 48;`
377			`7 : response_S <= 48;`
378			`8 : response_S <= 0;`
379			`14 : response_S <= 0;`
380	96	tac2	`16 : response_S <= 48;`
381	79	tac2	`17 : response_S <= 48;`
382			`24 : response_S <= 48;`
383			`33 : response_S <= 48;`
384			`55 : response_S <= 48;`
385			`41 : response_S <= 48;`
386			`endcase`
387			`case(inCmd[45:40])`
388
389			`response_CMD <= 0;`
390			`cardIdentificationState<=1;`
391			`ResetCard;`
392			`end`
393			`2 : begin`
394			`if (lastCMD != 41 && outDelayCnt==0) begin`
395			`$fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;`
396	125	tac2	`//$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;`
397	79	tac2	`CardStatus[3]<=1;`
398			`end`
399			`response_CMD[127:8] <= CID;`
400			`appendCrc<=0;`
401			`CardStatus[12:9] <=2;`
402			`end`
403			`3 : begin`
404	96	tac2	`if (lastCMD != 2 && outDelayCnt==0 ) begin`
405	79	tac2	`$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;`
406	125	tac2	`//$display(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;`
407	79	tac2	`CardStatus[3]<=1;`
408			`end`
409			`response_CMD[127:112] <= RCA[15:0] ;`
410			`response_CMD[111:96] <= CardStatus[15:0] ;`
411			`appendCrc<=1;`
412			`CardStatus[12:9] <=3;`
413			`cardIdentificationState<=0;`
414	96	tac2	`end`
415			`6 : begin`
416			`if (lastCMD == 55 && outDelayCnt==0) begin`
417			`if (inCmd[9:8] == 2'b10) begin`
418			`BusWidth <=4;`
419			`$display(sdModel_file_desc, "**BUS WIDTH 4 ") ;`
420			`end`
421			`else`
422			`BusWidth <=1;`
423
424			`response_S<=48;`
425			`response_CMD[127:96] <= CardStatus;`
426			`end`
427			`else if (outDelayCnt==0)begin`
428			`response_CMD <= 0;`
429			`response_S<=0;`
430			`$fdisplay(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;`
431	125	tac2	`// $display(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;`
432	96	tac2	`end`
433			`end`
434			`7: begin`
435			`if (outDelayCnt==0) begin`
436			`if (inCmd[39:24]== RCA[15:0]) begin`
437			`CardTransferActive <= 1;`
438			`response_CMD[127:96] <= CardStatus ;`
439			CardStatus[12:9] <=`TRAN;
440			`end`
441			`else begin`
442			`CardTransferActive <= 0;`
443			`response_CMD[127:96] <= CardStatus ;`
444			`CardStatus[12:9] <=3;`
445			`end`
446			`end`
447			`end`
448	79	tac2	`8 : response_CMD[127:96] <= 0; //V1.0 card`
449	96	tac2	`16 : begin`
450			`response_CMD[127:96] <= CardStatus ;`
451
452			`end`
453	98	tac2	`17 : begin`
454			`if (outDelayCnt==0) begin`
455			if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
456			CardStatus[12:9] <=`DATAS;//Put card in data state
457			`response_CMD[127:96] <= CardStatus ;`
458			`BlockAddr = inCmd[39:8];`
459			`if (BlockAddr%512 !=0)`
460			`$display("**Block Misalign Error");`
461			`end`
462			`else begin`
463			`response_S <= 0;`
464			`response_CMD[127:96] <= 0;`
465			`end`
466			`end`
467
468			`end`
469
470	96	tac2	`24 : begin`
471			`if (outDelayCnt==0) begin`
472	98	tac2	if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
473	96	tac2	`if (CardStatus[8]) begin //If Free write buffer`
474			CardStatus[12:9] <=`RCV;//Put card in Rcv state
475			`response_CMD[127:96] <= CardStatus ;`
476			`BlockAddr = inCmd[39:8];`
477			`if (BlockAddr%512 !=0)`
478			`$display("**Block Misalign Error");`
479			`end`
480			`else begin`
481			`response_CMD[127:96] <= CardStatus;`
482			`$fdisplay(sdModel_file_desc, "**Error Try to blockwrite when No Free Writebuffer") ;`
483			`$display("**Error Try to blockwrite when No Free Writebuffer") ;`
484			`end`
485			`end`
486			`else begin`
487			`response_S <= 0;`
488			`response_CMD[127:96] <= 0;`
489			`end`
490			`end`
491
492			`end`
493	79	tac2	`33 : response_CMD[127:96] <= 48;`
494			`55 :`
495			`begin`
496			`response_CMD[127:96] <= CardStatus ;`
497			`CardStatus[5] <=1; //Next CMD is AP specific CMD`
498			`appendCrc<=1;`
499			`end`
500			`41 :`

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