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[/] [sdcard_mass_storage_controller/] [trunk/] [bench/] [sdc_dma/] [verilog/] [sdModel.v] - Blame information for rev 136

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 //`include "timescale.v"
`include "sd_defines.v"
`define tTLH 10 //Clock rise time
`define tHL 10 //Clock fall time
`define tISU 6 //Input setup time
`define tIH 0 //Input hold time
`define tODL 14 //Output delay
`define DLY_TO_OUTP 47
 
`define BLOCKSIZE 512
`define MEMSIZE 24643590 // 2mb block
`define BLOCK_BUFFER_SIZE 1
`define TIME_BUSY 63
 
`define PRG 7
`define RCV 6
`define DATAS 5
`define TRAN 4
module sdModel(
  input sdClk,
  tri cmd,
  tri [3:0] dat
 
);
 
 
reg oeCmd;
reg oeDat;
reg cmdOut;
reg [3:0] datOut;
reg [10:0] transf_cnt;
 
 
 
reg [5:0] lastCMD;
reg cardIdentificationState;
reg CardTransferActive;
reg [2:0] BusWidth;
 
assign cmd = oeCmd ? cmdOut : 1'bz;
assign dat = oeDat ? datOut : 4'bz;
 
reg InbuffStatus;
reg [31:0] BlockAddr;
reg [7:0] Inbuff [0:511];
reg [7:0] FLASHmem [0:`MEMSIZE];
 
 
reg [46:0]inCmd;
reg [5:0]cmdRead;
reg [7:0] cmdWrite;
reg crcIn;
reg crcEn;
reg crcRst;
reg [31:0] CardStatus;
reg [15:0] RCA;
reg [31:0] OCR;
reg [120:0] CID;
reg [120:0] CSD;
reg Busy; //0 when busy
wire [6:0] crcOut;
reg [4:0] crc_c;
 
reg [3:0] CurrentState;
reg [3:0] DataCurrentState;
`define RCASTART 16'h2000
`define OCRSTART 32'hff8000
`define STATUSSTART 32'h0
`define CIDSTART 128'hffffffddddddddaaaaaaaa99999999  //Just some random data not really usefull anyway 
`define CSDSTART 128'hadaeeeddddddddaaaaaaaa12345678
 
`define outDelay 4
reg [2:0] outDelayCnt;
reg [9:0] flash_write_cnt;
reg [8:0] flash_blockwrite_cnt;
 
parameter SIZE = 10;
parameter CONTENT_SIZE = 40;
parameter
    IDLE   =  10'b0000_0000_01,
    READ_CMD   =  10'b0000_0000_10,
    ANALYZE_CMD     =  10'b0000_0001_00,
    SEND_CMD        =  10'b0000_0010_00;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
 
parameter
    DATA_IDLE   =10'b0000_0000_01,
    READ_WAITS  =10'b0000_0000_10,
    READ_DATA  = 10'b0000_0001_00,
    WRITE_FLASH =10'b0000_0010_00,
    WRITE_DATA  =10'b0000_0100_00;
parameter okcrctoken = 4'b0101;
parameter invalidcrctoken = 4'b1111;
reg [SIZE-1:0] dataState;
reg [SIZE-1:0] next_datastate;
 
reg ValidCmd;
reg inValidCmd;
 
reg [7:0] response_S;
reg [135:0] response_CMD;
integer responseType;
 
     reg [9:0] block_cnt;
     reg wptr;
     reg crc_ok;
     reg [3:0] last_din;
 
 
 
reg crcDat_rst;
reg mult_read;
reg mult_write;
reg crcDat_en;
reg [3:0] crcDat_in;
wire [15:0] crcDat_out [3:0];
 
genvar i;
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen
  sd_crc_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);
end
endgenerate
sd_crc_7 crc_7(
crcIn,
crcEn,
sdClk,
crcRst,
crcOut);
 
reg stop;
 
reg appendCrc;
reg [5:0] startUppCnt;
 
reg q_start_bit;
//Card initinCMd
initial $readmemh("../bin/ramdisk2.hex",FLASHmem);
 
integer k;
initial begin
        $display("Contents of Mem after reading data file:");
        for (k=0; k<512; k=k+1) $display("%d:%h",k,FLASHmem[k]);
end
reg qCmd;
reg [2:0] crcCnt;
 
reg add_wrong_cmd_crc;
reg add_wrong_cmd_indx;
reg add_wrong_data_crc;
 
initial begin
  add_wrong_data_crc<=0;
  add_wrong_cmd_indx<=0;
  add_wrong_cmd_crc<=0;
   stop<=1;
  cardIdentificationState<=1;
  state<=IDLE;
  dataState<=DATA_IDLE;
  Busy<=0;
  oeCmd<=0;
  crcCnt<=0;
  CardTransferActive<=0;
  qCmd<=1;
  oeDat<=0;
  cmdOut<=0;
  cmdWrite<=0;
  InbuffStatus<=0;
  datOut<=0;
  inCmd<=0;
  BusWidth<=1;
  responseType=0;
  mult_read=0;
  mult_write=0;
  crcIn<=0;
  response_S<=0;
  crcEn<=0;
  crcRst<=0;
  cmdRead<=0;
  ValidCmd<=0;
  inValidCmd=0;
  appendCrc<=0;
  RCA<= `RCASTART;
  OCR<= `OCRSTART;
  CardStatus <= `STATUSSTART;
  CID<=`CIDSTART;
  CSD<=`CSDSTART;
  response_CMD<=0;
  outDelayCnt<=0;
  crcDat_rst<=1;
  crcDat_en<=0;
  crcDat_in<=0;
  transf_cnt<=0;
  BlockAddr<=0;
  block_cnt <=0;
  wptr<=0;
  transf_cnt<=0;
  crcDat_rst<=1;
  crcDat_en<=0;
  crcDat_in<=0;
  flash_write_cnt<=0;
  startUppCnt<=0;
  flash_blockwrite_cnt<=0;
end
 
//CARD logic
 
always @ (state or cmd or cmdRead or ValidCmd or inValidCmd or cmdWrite or outDelayCnt)
begin : FSM_COMBO
 next_state  = 0;
case(state)
IDLE: begin
   if (!cmd)
     next_state = READ_CMD;
  else
     next_state = IDLE;
end
READ_CMD: begin
  if (cmdRead>= 47)
     next_state = ANALYZE_CMD;
  else
     next_state =  READ_CMD;
 end
 ANALYZE_CMD: begin
  if ((ValidCmd  )   && (outDelayCnt >= `outDelay ))
     next_state = SEND_CMD;
  else if (inValidCmd)
     next_state =  IDLE;
 else
    next_state =  ANALYZE_CMD;
 end
 SEND_CMD: begin
    if (cmdWrite>= response_S)
     next_state = IDLE;
  else
     next_state =  SEND_CMD;
 
 end
 
 
 endcase
end
 
always @ (dataState or CardStatus or crc_c or flash_write_cnt or dat[0] )
begin : FSM_COMBODAT
 next_datastate  = 0;
case(dataState)
 DATA_IDLE: begin
   if ((CardStatus[12:9]==`RCV) ||  (mult_write == 1'b1) )
     next_datastate = READ_WAITS;
   else if ((CardStatus[12:9]==`DATAS )||  (mult_read == 1'b1) )
     next_datastate = WRITE_DATA;
   else
     next_datastate = DATA_IDLE;
 end
 
 READ_WAITS: begin
   if ( dat[0] == 1'b0 )
     next_datastate =  READ_DATA;
   else
     next_datastate =  READ_WAITS;
 end
 
 READ_DATA : begin
  if (crc_c==0  )
     next_datastate =  WRITE_FLASH;
  else begin
        if (stop == 1'b0)
     next_datastate =  READ_DATA;
    else
     next_datastate =  DATA_IDLE;
    end
 
 
 end
  WRITE_FLASH : begin
  if (flash_write_cnt>265 )
     next_datastate =  DATA_IDLE;
  else
     next_datastate =  WRITE_FLASH;
 
end
 
  WRITE_DATA : begin
    if (transf_cnt >= `BIT_BLOCK)
       next_datastate= DATA_IDLE;
    else
                 begin
                        if (stop == 1'b0)
                         next_datastate=WRITE_DATA;
                        else
                         next_datastate =  DATA_IDLE;
        end
  end
 
 
 
 
 
 endcase
end
 
always @ (posedge sdClk  )
 begin
 
    q_start_bit <= dat[0];
 end
 
always @ (posedge sdClk  )
begin : FSM_SEQ
    state <= next_state;
end
 
always @ (posedge sdClk  )
begin : FSM_SEQDAT
    dataState <= next_datastate;
end
 
 
 
always @ (posedge sdClk) begin
if (CardTransferActive) begin
 if (InbuffStatus==0) //empty
   CardStatus[8]<=1;
  else
   CardStatus[8]<=0;
  end
else
  CardStatus[8]<=1;
 
 startUppCnt<=startUppCnt+1;
 OCR[31]<=~Busy;
 if (startUppCnt == `TIME_BUSY)
   Busy <=1;
end
 
 
always @ (posedge sdClk) begin
   qCmd<=cmd;
end
 
//read data and cmd on rising edge
always @ (posedge sdClk) begin
 case(state)
   IDLE: begin
      mult_write <= 0;
      mult_read <=0;
      crcIn<=0;
      crcEn<=0;
      crcRst<=1;
      oeCmd<=0;
      stop<=0;
      cmdRead<=0;
      appendCrc<=0;
      ValidCmd<=0;
      inValidCmd=0;
      cmdWrite<=0;
      crcCnt<=0;
      response_CMD<=0;
      response_S<=0;
      outDelayCnt<=0;
      responseType=0;
    end
   READ_CMD: begin //read cmd
      crcEn<=1;
      crcRst<=0;
      crcIn <= #`tIH qCmd;
      inCmd[47-cmdRead]  <= #`tIH qCmd;
      cmdRead <= #1 cmdRead+1;
      if (cmdRead >= 40)
         crcEn<=0;
 
      if (cmdRead == 46) begin
          oeCmd<=1;
     cmdOut<=1;
      end
   end
 
   ANALYZE_CMD: begin//check for valid cmd
   //Wrong CRC go idle
    if (inCmd[46] == 0) //start
      inValidCmd=1;
    else if (inCmd[7:1] != crcOut) begin
      inValidCmd=1;
      $fdisplay(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
      $display(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
    end
    else if  (inCmd[0] != 1)  begin//stop 
      inValidCmd=1;
      $fdisplay(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
      $display(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
    end
    else begin
      if(outDelayCnt ==0)
        CardStatus[3]<=0;
      case(inCmd[45:40])
 
        2 : response_S <= 136;
        3 : response_S <= 48;
        7 : response_S <= 48;
        8 : response_S <= 0;
        9 : response_S <= 136;
        14 : response_S <= 0;
        16 : response_S <= 48;
        17 : response_S <= 48;
                18 : response_S <= 48;
        24 : response_S <= 48;
                25 : response_S <= 48;
        33 : response_S <= 48;
        55 : response_S <= 48;
        41 : response_S <= 48;
    endcase
         case(inCmd[45:40])
 
            response_CMD <= 0;
            cardIdentificationState<=1;
            ResetCard;
        end
        2 : begin
         if (lastCMD != 41 && outDelayCnt==0) begin
               $fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
               //$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
               CardStatus[3]<=1;
            end
        response_CMD[127:8] <= CID;
        appendCrc<=0;
        CardStatus[12:9] <=2;
        end
        3 :  begin
           if (lastCMD != 2 && outDelayCnt==0 ) begin
               $fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
               //$display(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
               CardStatus[3]<=1;
            end
        response_CMD[127:112] <= RCA[15:0] ;
        response_CMD[111:96] <= CardStatus[15:0] ;
        appendCrc<=1;
        CardStatus[12:9] <=3;
        cardIdentificationState<=0;
       end
        6 : begin
           if (lastCMD == 55 && outDelayCnt==0) begin
              if (inCmd[9:8] == 2'b10) begin
               BusWidth <=4;
                    $display(sdModel_file_desc, "**BUS WIDTH 4 ") ;
               end
              else
               BusWidth <=1;
 
              response_S<=48;
              response_CMD[127:96] <= CardStatus;
           end
           else if (outDelayCnt==0)begin
             response_CMD <= 0;
             response_S<=0;
             $fdisplay(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
           //  $display(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
            end
        end
        7: begin
         if (outDelayCnt==0) begin
          if (inCmd[39:24]== RCA[15:0]) begin
              CardTransferActive <= 1;
              response_CMD[127:96] <= CardStatus ;
              CardStatus[12:9] <=`TRAN;
          end
          else begin
               CardTransferActive <= 0;
               response_CMD[127:96] <= CardStatus ;
               CardStatus[12:9] <=3;
          end
         end
        end
        8 : response_CMD[127:96] <= 0; //V1.0 card
 
                9 : begin
         if (lastCMD != 41 && outDelayCnt==0) begin
               $fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
               //$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
               CardStatus[3]<=1;
            end
        response_CMD[127:8] <= CSD;
        appendCrc<=0;
        CardStatus[12:9] <=2;
        end
 
                  12: begin
          response_CMD[127:96] <= CardStatus ;
          stop<=1;
                  mult_write <= 0;
          mult_read <=0;
         CardStatus[12:9] <= `TRAN;
        end
 
 
        16 : begin
          response_CMD[127:96] <= CardStatus ;
 
        end
 
 
 
 
 
        17 :  begin
          if (outDelayCnt==0) begin
            if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate                               
                CardStatus[12:9] <=`DATAS;//Put card in data state
                response_CMD[127:96] <= CardStatus ;
                BlockAddr = inCmd[39:8];
                if (BlockAddr%512 !=0)
                  $display("**Block Misalign Error");
          end
           else begin
             response_S <= 0;
             response_CMD[127:96] <= 0;
           end
         end
 
       end
 
     18 :  begin
          if (outDelayCnt==0) begin
            if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate                               
                CardStatus[12:9] <=`DATAS;//Put card in data state
                response_CMD[127:96] <= CardStatus ;
                            mult_read <= 1;
                BlockAddr = inCmd[39:8];
                if (BlockAddr%512 !=0)
                  $display("**Block Misalign Error");
          end
           else begin
             response_S <= 0;
             response_CMD[127:96] <= 0;
 
           end
         end
 
       end
 
        24 : begin
          if (outDelayCnt==0) begin
            if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
              if (CardStatus[8]) begin //If Free write buffer           
                CardStatus[12:9] <=`RCV;//Put card in Rcv state
                response_CMD[127:96] <= CardStatus ;
                BlockAddr = inCmd[39:8];
                if (BlockAddr%512 !=0)
                  $display("**Block Misalign Error");
              end
              else begin
                response_CMD[127:96] <= CardStatus;
                 $fdisplay(sdModel_file_desc, "**Error Try to blockwrite when No Free Writebuffer") ;
                 $display("**Error Try to blockwrite when No Free Writebuffer") ;
             end
           end
           else begin
             response_S <= 0;
             response_CMD[127:96] <= 0;
           end
         end
       end
        25 : begin
          if (outDelayCnt==0) begin
            if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
              if (CardStatus[8]) begin //If Free write buffer           
                CardStatus[12:9] <=`RCV;//Put card in Rcv state
                response_CMD[127:96] <= CardStatus ;
                BlockAddr = inCmd[39:8];
                                mult_write <= 1;
                if (BlockAddr%512 !=0)
                  $display("**Block Misalign Error");
              end
              else begin
                response_CMD[127:96] <= CardStatus;
                 $fdisplay(sdModel_file_desc, "**Error Try to blockwrite when No Free Writebuffer") ;
                 $display("**Error Try to blockwrite when No Free Writebuffer") ;
             end
           end
           else begin
             response_S <= 0;
             response_CMD[127:96] <= 0;
           end
         end
       end
 
        33 : response_CMD[127:96] <= 48;
        55 :
        begin
          response_CMD[127:96] <= CardStatus ;
          CardStatus[5] <=1;      //Next CMD is AP specific CMD
          appendCrc<=1;
        end
        41 :
        begin
         if (cardIdentificationState) begin
            if (lastCMD != 55 && outDelayCnt==0) begin
               $fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
               $display( "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
               CardStatus[3]<=1;
            end
            else begin
             responseType=3;
             response_CMD[127:96] <= OCR;
             appendCrc<=0;
             CardStatus[5] <=0;
            if (Busy==1)
              CardStatus[12:9] <=1;
           end
        end
       end
 
    endcase
     ValidCmd<=1;
     crcIn<=0;
 
     outDelayCnt<=outDelayCnt+1;
     if (outDelayCnt==`outDelay)
       crcRst<=1;
     oeCmd<=1;
     cmdOut<=1;
     response_CMD[135:134] <=0;
 
    if (responseType != 3)
       if (!add_wrong_cmd_indx)
         response_CMD[133:128] <=inCmd[45:40];
      else
         response_CMD[133:128] <=0;
 
    if (responseType == 3)
       response_CMD[133:128] <=6'b111111;
 
     lastCMD <=inCmd[45:40];
    end
   end
 
 
 
 endcase
end
 
always @ ( negedge sdClk) begin
 case(state)
 
SEND_CMD: begin
     crcRst<=0;
     crcEn<=1;
    cmdWrite<=cmdWrite+1;
    if (response_S!=0)
     cmdOut<=0;
   else
      cmdOut<=1;
 
    if ((cmdWrite>0) &&  (cmdWrite < response_S-8)) begin
      cmdOut<=response_CMD[135-cmdWrite];
      crcIn<=response_CMD[134-cmdWrite];
      if (cmdWrite >= response_S-9)
       crcEn<=0;
    end
   else if (cmdWrite!=0) begin
     crcEn<=0;
     if (add_wrong_cmd_crc) begin
        cmdOut<=0;
        crcCnt<=crcCnt+1;
     end
     else begin
     cmdOut<=crcOut[6-crcCnt];
     crcCnt<=crcCnt+1;
     if (responseType == 3)
           cmdOut<=1;
    end
   end
  if (cmdWrite == response_S-1)
    cmdOut<=1;
 
  end
 endcase
end
 
 
 
integer outdly_cnt;
 
 
 
 
 
 
 
always @ (posedge sdClk) begin
 
  case (dataState)
  DATA_IDLE: begin
 
     crcDat_rst<=1;
     crcDat_en<=0;
     crcDat_in<=0;
 
  end
 
  READ_WAITS: begin
      oeDat<=0;
      crcDat_rst<=0;
      crcDat_en<=1;
      crcDat_in<=0;
      crc_c<=15;//
      crc_ok<=1;
  end
  READ_DATA: begin
 
 
    InbuffStatus<=1;
    if (transf_cnt<`BIT_BLOCK_REC) begin
       if (wptr)
         Inbuff[block_cnt][3:0] <= dat;
       else
          Inbuff[block_cnt][7:4] <= dat;
 
       if (!add_wrong_data_crc)
          crcDat_in<=dat;
        else
          crcDat_in<=4'b1010;
 
       crc_ok<=1;
       transf_cnt<=transf_cnt+1;
       if (wptr)
         block_cnt<=block_cnt+1;
       wptr<=~wptr;
 
 
    end
    else if  ( transf_cnt <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE-1)) begin
       transf_cnt<=transf_cnt+1;
       crcDat_en<=0;
       last_din <=dat;
 
       if (transf_cnt> `BIT_BLOCK_REC) begin
        crc_c<=crc_c-1;
 
          if (crcDat_out[0][crc_c] != last_din[0])
           crc_ok<=0;
          if  (crcDat_out[1][crc_c] != last_din[1])
           crc_ok<=0;
          if  (crcDat_out[2][crc_c] != last_din[2])
           crc_ok<=0;
          if  (crcDat_out[3][crc_c] != last_din[3])
           crc_ok<=0;
      end
    end
  end
  WRITE_FLASH: begin
     oeDat<=1;
     block_cnt <=0;
     wptr<=0;
     transf_cnt<=0;
     crcDat_rst<=1;
     crcDat_en<=0;
     crcDat_in<=0;
 
 
  end
 
  endcase
 
 
end
 
 
 
reg data_send_index;
integer write_out_index;
always @ (negedge sdClk) begin
 
  case (dataState)
  DATA_IDLE: begin
     write_out_index<=0;
     transf_cnt<=0;
     data_send_index<=0;
     outdly_cnt<=0;
     flash_write_cnt<=0;
  end
 
 
   WRITE_DATA: begin
      oeDat<=1;
      outdly_cnt<=outdly_cnt+1;
 
      if ( outdly_cnt > `DLY_TO_OUTP) begin
         transf_cnt <= transf_cnt+1;
         crcDat_en<=1;
         crcDat_rst<=0;
 
      end
      else begin
        crcDat_en<=0;
        crcDat_rst<=1;
        oeDat<=1;
        crc_c<=16;
     end
 
       if (transf_cnt==1) begin
 
          last_din <= FLASHmem[BlockAddr+(write_out_index)][7:4];
          datOut<=0;
          crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
          data_send_index<=1;
        end
        else if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) begin
          data_send_index<=~data_send_index;
          if (!data_send_index) begin
             last_din<=FLASHmem[BlockAddr+(write_out_index)][7:4];
             crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
          end
          else begin
             last_din<=FLASHmem[BlockAddr+(write_out_index)][3:0];
             if (!add_wrong_data_crc)
               crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][3:0];
             else
               crcDat_in<=4'b1010;
             write_out_index<=write_out_index+1;
 
         end
 
 
          datOut<= last_din;
 
 
          if ( transf_cnt >=`BIT_BLOCK-`CRC_OFF ) begin
             crcDat_en<=0;
         end
 
       end
       else if (transf_cnt>`BIT_BLOCK-`CRC_OFF & crc_c!=0) begin
         datOut<= last_din;
         crcDat_en<=0;
         crc_c<=crc_c-1;
         if (crc_c<= 16) begin
         datOut[0]<=crcDat_out[0][crc_c-1];
         datOut[1]<=crcDat_out[1][crc_c-1];
         datOut[2]<=crcDat_out[2][crc_c-1];
         datOut[3]<=crcDat_out[3][crc_c-1];
       end
       end
       else if (transf_cnt==`BIT_BLOCK-2) begin
          datOut<=4'b1111;
      end
       else if ((transf_cnt !=0) && (crc_c == 0 ))begin
         oeDat<=0;
         CardStatus[12:9] <= `TRAN;
         end
 
 
 
  end
 
 
 
  WRITE_FLASH: begin
    flash_write_cnt<=flash_write_cnt+1;
     CardStatus[12:9] <= `PRG;
      datOut[0]<=0;
       datOut[1]<=1;
       datOut[2]<=1;
       datOut[3]<=1;
    if (flash_write_cnt == 0)
      datOut<=1;
    else if(flash_write_cnt == 1)
     datOut[0]<=1;
    else if(flash_write_cnt == 2)
     datOut[0]<=0;
 
 
    else if ((flash_write_cnt > 2) && (flash_write_cnt < 7)) begin
      if (crc_ok)
        datOut[0] <=okcrctoken[6-flash_write_cnt];
      else
        datOut[0] <= invalidcrctoken[6-flash_write_cnt];
    end
    else if  ((flash_write_cnt >= 7) && (flash_write_cnt < 264)) begin
       datOut[0]<=0;
 
      flash_blockwrite_cnt<=flash_blockwrite_cnt+2;
       FLASHmem[BlockAddr+(flash_blockwrite_cnt)]<=Inbuff[flash_blockwrite_cnt];
       FLASHmem[BlockAddr+(flash_blockwrite_cnt+1)]<=Inbuff[flash_blockwrite_cnt+1];
 
    end
    else begin
      datOut<=1;
      InbuffStatus<=0;
      CardStatus[12:9] <= `TRAN;
    end
  end
endcase
end
 
integer sdModel_file_desc;
 
initial
begin
  sdModel_file_desc = $fopen("../log/sd_model.log");
  if (sdModel_file_desc < 2)
  begin
    $display("*E Could not open/create testbench log file in /log/ directory!");
    $finish;
  end
end
 
task ResetCard; //  MAC registers
begin
   add_wrong_data_crc<=0;
  add_wrong_cmd_indx<=0;
  add_wrong_cmd_crc<=0;
 cardIdentificationState<=1;
  state<=IDLE;
  dataState<=DATA_IDLE;
  Busy<=0;
  oeCmd<=0;
  crcCnt<=0;
  CardTransferActive<=0;
  qCmd<=1;
  oeDat<=0;
  cmdOut<=0;
  cmdWrite<=0;
  startUppCnt<=0;
  InbuffStatus<=0;
  datOut<=0;
  inCmd<=0;
  BusWidth<=1;
  responseType=0;
  crcIn<=0;
  response_S<=0;
  crcEn<=0;
  crcRst<=0;
  cmdRead<=0;
  ValidCmd<=0;
  inValidCmd=0;
  appendCrc<=0;
  RCA<= `RCASTART;
  OCR<= `OCRSTART;
  CardStatus <= `STATUSSTART;
  CID<=`CIDSTART;
  CSD<=`CSDSTART;
  response_CMD<=0;
  outDelayCnt<=0;
  crcDat_rst<=1;
  crcDat_en<=0;
  crcDat_in<=0;
  transf_cnt<=0;
  BlockAddr<=0;
  block_cnt <=0;
     wptr<=0;
     transf_cnt<=0;
     crcDat_rst<=1;
     crcDat_en<=0;
     crcDat_in<=0;
flash_write_cnt<=0;
flash_blockwrite_cnt<=0;
end
endtask
 
 
endmodule

Line No.	Rev	Author	Line
1	127	tac2	//`include "timescale.v"
2	135	tac2	`include "sd_defines.v"
3	79	tac2	`define tTLH 10 //Clock rise time
4			`define tHL 10 //Clock fall time
5			`define tISU 6 //Input setup time
6			`define tIH 0 //Input hold time
7			`define tODL 14 //Output delay
8	98	tac2	`define DLY_TO_OUTP 47
9	79	tac2
10			`define BLOCKSIZE 512
11	135	tac2	`define MEMSIZE 24643590 // 2mb block
12	79	tac2	`define BLOCK_BUFFER_SIZE 1
13	135	tac2	`define TIME_BUSY 63
14	79	tac2
15	96	tac2	`define PRG 7
16			`define RCV 6
17			`define DATAS 5
18			`define TRAN 4
19	79	tac2	`module sdModel(`
20			`input sdClk,`
21			`tri cmd,`
22			`tri [3:0] dat`
23
24			`);`
25
26
27			`reg oeCmd;`
28			`reg oeDat;`
29			`reg cmdOut;`
30	96	tac2	`reg [3:0] datOut;`
31			`reg [10:0] transf_cnt;`
32	79	tac2
33	96	tac2
34
35	79	tac2	`reg [5:0] lastCMD;`
36			`reg cardIdentificationState;`
37	96	tac2	`reg CardTransferActive;`
38			`reg [2:0] BusWidth;`
39	79	tac2
40			`assign cmd = oeCmd ? cmdOut : 1'bz;`
41			`assign dat = oeDat ? datOut : 4'bz;`
42
43	96	tac2	`reg InbuffStatus;`
44			`reg [31:0] BlockAddr;`
45			`reg [7:0] Inbuff [0:511];`
46			reg [7:0] FLASHmem [0:`MEMSIZE];
47	79	tac2
48
49			`reg [46:0]inCmd;`
50			`reg [5:0]cmdRead;`
51			`reg [7:0] cmdWrite;`
52			`reg crcIn;`
53			`reg crcEn;`
54			`reg crcRst;`
55			`reg [31:0] CardStatus;`
56			`reg [15:0] RCA;`
57			`reg [31:0] OCR;`
58			`reg [120:0] CID;`
59	135	tac2	`reg [120:0] CSD;`
60	79	tac2	`reg Busy; //0 when busy`
61			`wire [6:0] crcOut;`
62	102	tac2	`reg [4:0] crc_c;`
63	96	tac2
64			`reg [3:0] CurrentState;`
65			`reg [3:0] DataCurrentState;`
66	135	tac2	`define RCASTART 16'h2000
67	79	tac2	`define OCRSTART 32'hff8000
68			`define STATUSSTART 32'h0
69	135	tac2	`define CIDSTART 128'hffffffddddddddaaaaaaaa99999999 //Just some random data not really usefull anyway
70			`define CSDSTART 128'hadaeeeddddddddaaaaaaaa12345678
71	79	tac2
72			`define outDelay 4
73			`reg [2:0] outDelayCnt;`
74	96	tac2	`reg [9:0] flash_write_cnt;`
75			`reg [8:0] flash_blockwrite_cnt;`
76
77	79	tac2	`parameter SIZE = 10;`
78			`parameter CONTENT_SIZE = 40;`
79			`parameter`
80			`IDLE = 10'b0000_0000_01,`
81			`READ_CMD = 10'b0000_0000_10,`
82			`ANALYZE_CMD = 10'b0000_0001_00,`
83			`SEND_CMD = 10'b0000_0010_00;`
84			`reg [SIZE-1:0] state;`
85			`reg [SIZE-1:0] next_state;`
86
87	96	tac2	`parameter`
88			`DATA_IDLE =10'b0000_0000_01,`
89			`READ_WAITS =10'b0000_0000_10,`
90			`READ_DATA = 10'b0000_0001_00,`
91			`WRITE_FLASH =10'b0000_0010_00,`
92			`WRITE_DATA =10'b0000_0100_00;`
93			`parameter okcrctoken = 4'b0101;`
94			`parameter invalidcrctoken = 4'b1111;`
95			`reg [SIZE-1:0] dataState;`
96			`reg [SIZE-1:0] next_datastate;`
97
98	79	tac2	`reg ValidCmd;`
99			`reg inValidCmd;`
100
101			`reg [7:0] response_S;`
102			`reg [135:0] response_CMD;`
103			`integer responseType;`
104	96	tac2
105			`reg [9:0] block_cnt;`
106			`reg wptr;`
107			`reg crc_ok;`
108			`reg [3:0] last_din;`
109
110
111
112			`reg crcDat_rst;`
113	135	tac2	`reg mult_read;`
114			`reg mult_write;`
115	96	tac2	`reg crcDat_en;`
116			`reg [3:0] crcDat_in;`
117			`wire [15:0] crcDat_out [3:0];`
118
119			`genvar i;`
120			`generate`
121			`for(i=0; i<4; i=i+1) begin:CRC_16_gen`
122	135	tac2	`sd_crc_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);`
123	96	tac2	`end`
124			`endgenerate`
125	135	tac2	`sd_crc_7 crc_7(`
126	79	tac2	`crcIn,`
127			`crcEn,`
128			`sdClk,`
129			`crcRst,`
130			`crcOut);`
131	96	tac2
132	135	tac2	`reg stop;`
133	96	tac2
134	79	tac2	`reg appendCrc;`
135			`reg [5:0] startUppCnt;`
136
137	96	tac2	`reg q_start_bit;`
138	79	tac2	`//Card initinCMd`
139	135	tac2	`initial $readmemh("../bin/ramdisk2.hex",FLASHmem);`
140	79	tac2
141			`integer k;`
142			`initial begin`
143			`$display("Contents of Mem after reading data file:");`
144	135	tac2	`for (k=0; k<512; k=k+1) $display("%d:%h",k,FLASHmem[k]);`
145	79	tac2	`end`
146			`reg qCmd;`
147			`reg [2:0] crcCnt;`
148	125	tac2
149			`reg add_wrong_cmd_crc;`
150			`reg add_wrong_cmd_indx;`
151			`reg add_wrong_data_crc;`
152
153	79	tac2	`initial begin`
154	125	tac2	`add_wrong_data_crc<=0;`
155			`add_wrong_cmd_indx<=0;`
156			`add_wrong_cmd_crc<=0;`
157	135	tac2	`stop<=1;`
158	79	tac2	`cardIdentificationState<=1;`
159			`state<=IDLE;`
160	96	tac2	`dataState<=DATA_IDLE;`
161	79	tac2	`Busy<=0;`
162			`oeCmd<=0;`
163			`crcCnt<=0;`
164	96	tac2	`CardTransferActive<=0;`
165	79	tac2	`qCmd<=1;`
166			`oeDat<=0;`
167			`cmdOut<=0;`
168	98	tac2	`cmdWrite<=0;`
169	96	tac2	`InbuffStatus<=0;`
170	79	tac2	`datOut<=0;`
171			`inCmd<=0;`
172	96	tac2	`BusWidth<=1;`
173	79	tac2	`responseType=0;`
174	135	tac2	`mult_read=0;`
175			`mult_write=0;`
176	79	tac2	`crcIn<=0;`
177			`response_S<=0;`
178			`crcEn<=0;`
179			`crcRst<=0;`
180			`cmdRead<=0;`
181			`ValidCmd<=0;`
182			`inValidCmd=0;`
183			`appendCrc<=0;`
184			RCA<= `RCASTART;
185			OCR<= `OCRSTART;
186			CardStatus <= `STATUSSTART;
187			CID<=`CIDSTART;
188	135	tac2	CSD<=`CSDSTART;
189	79	tac2	`response_CMD<=0;`
190			`outDelayCnt<=0;`
191	96	tac2	`crcDat_rst<=1;`
192			`crcDat_en<=0;`
193			`crcDat_in<=0;`
194			`transf_cnt<=0;`
195			`BlockAddr<=0;`
196			`block_cnt <=0;`
197	98	tac2	`wptr<=0;`
198			`transf_cnt<=0;`
199			`crcDat_rst<=1;`
200			`crcDat_en<=0;`
201			`crcDat_in<=0;`
202			`flash_write_cnt<=0;`
203	135	tac2	`startUppCnt<=0;`
204	98	tac2	`flash_blockwrite_cnt<=0;`
205	79	tac2	`end`
206
207			`//CARD logic`
208
209			`always @ (state or cmd or cmdRead or ValidCmd or inValidCmd or cmdWrite or outDelayCnt)`
210			`begin : FSM_COMBO`
211			`next_state = 0;`
212			`case(state)`
213			`IDLE: begin`
214			`if (!cmd)`
215			`next_state = READ_CMD;`
216			`else`
217			`next_state = IDLE;`
218			`end`
219			`READ_CMD: begin`
220			`if (cmdRead>= 47)`
221			`next_state = ANALYZE_CMD;`
222			`else`
223			`next_state = READ_CMD;`
224			`end`
225			`ANALYZE_CMD: begin`
226			if ((ValidCmd ) && (outDelayCnt >= `outDelay ))
227			`next_state = SEND_CMD;`
228			`else if (inValidCmd)`
229			`next_state = IDLE;`
230			`else`
231			`next_state = ANALYZE_CMD;`
232			`end`
233			`SEND_CMD: begin`
234			`if (cmdWrite>= response_S)`
235			`next_state = IDLE;`
236			`else`
237			`next_state = SEND_CMD;`
238
239			`end`
240
241
242			`endcase`
243			`end`
244
245	98	tac2	`always @ (dataState or CardStatus or crc_c or flash_write_cnt or dat[0] )`
246	96	tac2	`begin : FSM_COMBODAT`
247			`next_datastate = 0;`
248			`case(dataState)`
249			`DATA_IDLE: begin`
250	135	tac2	if ((CardStatus[12:9]==`RCV) \|\| (mult_write == 1'b1) )
251	96	tac2	`next_datastate = READ_WAITS;`
252	135	tac2	else if ((CardStatus[12:9]==`DATAS )\|\| (mult_read == 1'b1) )
253	96	tac2	`next_datastate = WRITE_DATA;`
254			`else`
255			`next_datastate = DATA_IDLE;`
256			`end`
257
258			`READ_WAITS: begin`
259	98	tac2	`if ( dat[0] == 1'b0 )`
260	96	tac2	`next_datastate = READ_DATA;`
261			`else`
262			`next_datastate = READ_WAITS;`
263			`end`
264
265			`READ_DATA : begin`
266			`if (crc_c==0 )`
267			`next_datastate = WRITE_FLASH;`
268	135	tac2	`else begin`
269			`if (stop == 1'b0)`
270	96	tac2	`next_datastate = READ_DATA;`
271	135	tac2	`else`
272			`next_datastate = DATA_IDLE;`
273			`end`
274
275
276	96	tac2	`end`
277			`WRITE_FLASH : begin`
278	135	tac2	`if (flash_write_cnt>265 )`
279	96	tac2	`next_datastate = DATA_IDLE;`
280	135	tac2	`else`
281	96	tac2	`next_datastate = WRITE_FLASH;`
282	135	tac2
283	98	tac2	`end`
284	135	tac2
285	98	tac2	`WRITE_DATA : begin`
286			if (transf_cnt >= `BIT_BLOCK)
287			`next_datastate= DATA_IDLE;`
288			`else`
289	135	tac2	`begin`
290			`if (stop == 1'b0)`
291			`next_datastate=WRITE_DATA;`
292			`else`
293			`next_datastate = DATA_IDLE;`
294			`end`
295	98	tac2	`end`
296	96	tac2
297
298
299
300
301			`endcase`
302			`end`
303
304	79	tac2	`always @ (posedge sdClk )`
305	96	tac2	`begin`
306
307			`q_start_bit <= dat[0];`
308			`end`
309
310			`always @ (posedge sdClk )`
311	79	tac2	`begin : FSM_SEQ`
312	96	tac2	`state <= next_state;`
313	79	tac2	`end`
314
315	96	tac2	`always @ (posedge sdClk )`
316			`begin : FSM_SEQDAT`
317			`dataState <= next_datastate;`
318			`end`
319	79	tac2
320	96	tac2
321
322	79	tac2	`always @ (posedge sdClk) begin`
323	96	tac2	`if (CardTransferActive) begin`
324			`if (InbuffStatus==0) //empty`
325			`CardStatus[8]<=1;`
326			`else`
327			`CardStatus[8]<=0;`
328			`end`
329			`else`
330	135	tac2	`CardStatus[8]<=1;`
331	96	tac2
332	79	tac2	`startUppCnt<=startUppCnt+1;`
333	136	tac2	`OCR[31]<=~Busy;`
334	79	tac2	if (startUppCnt == `TIME_BUSY)
335			`Busy <=1;`
336			`end`
337
338
339			`always @ (posedge sdClk) begin`
340			`qCmd<=cmd;`
341			`end`
342
343			`//read data and cmd on rising edge`
344			`always @ (posedge sdClk) begin`
345			`case(state)`
346			`IDLE: begin`
347	135	tac2	`mult_write <= 0;`
348			`mult_read <=0;`
349	79	tac2	`crcIn<=0;`
350			`crcEn<=0;`
351			`crcRst<=1;`
352			`oeCmd<=0;`
353	135	tac2	`stop<=0;`
354	79	tac2	`cmdRead<=0;`
355			`appendCrc<=0;`
356			`ValidCmd<=0;`
357			`inValidCmd=0;`
358			`cmdWrite<=0;`
359			`crcCnt<=0;`
360			`response_CMD<=0;`
361			`response_S<=0;`
362			`outDelayCnt<=0;`
363			`responseType=0;`
364			`end`
365			`READ_CMD: begin //read cmd`
366			`crcEn<=1;`
367			`crcRst<=0;`
368			crcIn <= #`tIH qCmd;
369			inCmd[47-cmdRead] <= #`tIH qCmd;
370			`cmdRead <= #1 cmdRead+1;`
371			`if (cmdRead >= 40)`
372			`crcEn<=0;`
373
374			`if (cmdRead == 46) begin`
375			`oeCmd<=1;`
376			`cmdOut<=1;`
377			`end`
378			`end`
379
380			`ANALYZE_CMD: begin//check for valid cmd`
381			`//Wrong CRC go idle`
382			`if (inCmd[46] == 0) //start`
383			`inValidCmd=1;`
384			`else if (inCmd[7:1] != crcOut) begin`
385			`inValidCmd=1;`
386			`$fdisplay(sdModel_file_desc, "**sd_Model Commando CRC Error") ;`
387			`$display(sdModel_file_desc, "**sd_Model Commando CRC Error") ;`
388			`end`
389			`else if (inCmd[0] != 1) begin//stop`
390			`inValidCmd=1;`
391			`$fdisplay(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;`
392			`$display(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;`
393			`end`
394			`else begin`
395	96	tac2	`if(outDelayCnt ==0)`
396			`CardStatus[3]<=0;`
397	79	tac2	`case(inCmd[45:40])`
398
399			`2 : response_S <= 136;`
400			`3 : response_S <= 48;`
401			`7 : response_S <= 48;`
402			`8 : response_S <= 0;`
403	135	tac2	`9 : response_S <= 136;`
404	79	tac2	`14 : response_S <= 0;`
405	96	tac2	`16 : response_S <= 48;`
406	79	tac2	`17 : response_S <= 48;`
407	135	tac2	`18 : response_S <= 48;`
408	79	tac2	`24 : response_S <= 48;`
409	135	tac2	`25 : response_S <= 48;`
410	79	tac2	`33 : response_S <= 48;`
411			`55 : response_S <= 48;`
412			`41 : response_S <= 48;`
413			`endcase`
414			`case(inCmd[45:40])`
415
416			`response_CMD <= 0;`
417			`cardIdentificationState<=1;`
418			`ResetCard;`
419			`end`
420			`2 : begin`
421			`if (lastCMD != 41 && outDelayCnt==0) begin`
422			`$fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;`
423	125	tac2	`//$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;`
424	79	tac2	`CardStatus[3]<=1;`
425			`end`
426			`response_CMD[127:8] <= CID;`
427			`appendCrc<=0;`
428			`CardStatus[12:9] <=2;`
429			`end`
430			`3 : begin`
431	96	tac2	`if (lastCMD != 2 && outDelayCnt==0 ) begin`
432	79	tac2	`$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;`
433	125	tac2	`//$display(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;`
434	79	tac2	`CardStatus[3]<=1;`
435			`end`
436			`response_CMD[127:112] <= RCA[15:0] ;`
437			`response_CMD[111:96] <= CardStatus[15:0] ;`
438			`appendCrc<=1;`
439			`CardStatus[12:9] <=3;`
440			`cardIdentificationState<=0;`
441	96	tac2	`end`
442			`6 : begin`
443			`if (lastCMD == 55 && outDelayCnt==0) begin`
444			`if (inCmd[9:8] == 2'b10) begin`
445			`BusWidth <=4;`
446			`$display(sdModel_file_desc, "**BUS WIDTH 4 ") ;`
447			`end`
448			`else`
449			`BusWidth <=1;`
450
451			`response_S<=48;`
452			`response_CMD[127:96] <= CardStatus;`
453			`end`
454			`else if (outDelayCnt==0)begin`
455			`response_CMD <= 0;`
456			`response_S<=0;`
457			`$fdisplay(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;`
458	125	tac2	`// $display(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;`
459	96	tac2	`end`
460			`end`
461			`7: begin`
462			`if (outDelayCnt==0) begin`
463			`if (inCmd[39:24]== RCA[15:0]) begin`
464			`CardTransferActive <= 1;`
465			`response_CMD[127:96] <= CardStatus ;`
466			CardStatus[12:9] <=`TRAN;
467			`end`
468			`else begin`
469			`CardTransferActive <= 0;`
470			`response_CMD[127:96] <= CardStatus ;`
471			`CardStatus[12:9] <=3;`
472			`end`
473			`end`
474			`end`
475	79	tac2	`8 : response_CMD[127:96] <= 0; //V1.0 card`
476	135	tac2
477			`9 : begin`
478			`if (lastCMD != 41 && outDelayCnt==0) begin`
479			`$fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;`
480			`//$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;`
481			`CardStatus[3]<=1;`
482			`end`
483			`response_CMD[127:8] <= CSD;`
484			`appendCrc<=0;`
485			`CardStatus[12:9] <=2;`
486			`end`
487
488			`12: begin`
489			`response_CMD[127:96] <= CardStatus ;`
490			`stop<=1;`
491			`mult_write <= 0;`
492			`mult_read <=0;`
493			CardStatus[12:9] <= `TRAN;
494			`end`
495
496
497	96	tac2	`16 : begin`
498			`response_CMD[127:96] <= CardStatus ;`
499
500			`end`

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[/] [sdcard_mass_storage_controller/] [trunk/] [bench/] [sdc_dma/] [verilog/] [sdModel.v] - Blame information for rev 136