Subversion Repositories sdcard_mass_storage_controller

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  sd_controller_top_tb.v                                      ////

////                                                              ////

////  This file is part of the SD IP core project                 ////

//// http://www.opencores.org/?do=project&who=sdcard_mass_storage_controller                   ////

////                                                              ////

////  Author(s):                                                  ////

////      - Adam Edvardsson, adam@opencores.org                   ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//// WB Model, ideas and task borrowed from:                    ////

//// http://www.opencores.org/projects/ethmac/                    ////

////  Author(s):                                                  ////

////      - Tadej Markovic, tadej@opencores.org                   ////

////      - Igor Mohor,     igorM@opencores.org                   ////

//////////////////////////////////////////////////////////////////////

////                  

                                            ////

//// Copyright (C) 2001, 2002 Authors                             ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//`define TX_ERROR_TEST

`include "wb_model_defines.v"

`include "sd_defines.v"

`define TIME $display("  Time: %0t", $time)

`define BD_RX 8'h60

`define BD_TX 8'h80

`define argument 8'h00

`define command 8'h04

`define status 8'h08

`define resp1 8'h0c

`define controller 8'h1c

`define block 8'h20

`define power 8'h24

`define software 8'h28

`define timeout 8'h2c

`define normal_isr 8'h30

`define error_isr 8'h34

`define normal_iser 8'h38

`define error_iser 8'h3c

`define capa 8'h48

`define clock_d 8'h4c

`define bd_status 8'h50

`define bd_isr 8'h54

`define bd_iser 8'h58

`define bd_rx 8'h60

`define bd_tx 8'h80

`define  BD_ISR  8'h54

`define SD_BASE              32'hd0000000

`define CMD2 16'h200

`define CMD3 16'h300

`define ACMD6 16'h600

`define CMD7 16'h700

`define CMD8 16'h800

`define CMD55 16'h3700

`define ACMD41 16'h2900

`define CMD8 16'h800

`define RSP_48 16'h2

`define RSP_136 16'h1

`define CICE 16'h10

`define CRCE 16'h08

module sd_controller_top_tb(

);

// WISHBONE common

reg           wb_clk;     // WISHBONE clock

reg           wb_rst;     // WISHBONE reset

wire   [31:0]  wbs_sds_dat_i;     // WISHBONE data input

wire [31:0]   wbs_sds_dat_o;     // WISHBONE data output

     // WISHBONE error output

// WISHBONE slave

wire   [9:0]  wbs_sds_adr_i;     // WISHBONE address input

wire    [3:0]  wbs_sds_sel_i;     // WISHBONE byte select input

wire           wbs_sds_we_i;      // WISHBONE write enable input

wire           wbs_sds_cyc_i;     // WISHBONE cycle input

wire           wbs_sds_stb_i;     // WISHBONE strobe input

wire          wbs_sds_ack_o;     // WISHBONE acknowledge output

// WISHBONE master

wire  [31:0]  wbm_sdm_adr_o;

wire   [3:0]  wbm_sdm_sel_o;

wire          wbm_sdm_we_o;

wire   [31:0]  wbm_sdm_dat_i;

wire  [31:0]  wbm_sdm_dat_o;

wire          wbm_sdm_cyc_o;

wire          wbm_sdm_stb_o;

wire           wbm_sdm_ack_i;

wire    [2:0]  wbm_sdm_cti_o;

wire    [1:0]       wbm_sdm_bte_o;

//Global variables

reg          wbm_working; // tasks wbm_write and wbm_read set signal when working and reset it when stop working

integer      tests_successfull;

integer      tests_failed;

reg   [3:0]  wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master

reg   [3:0]  wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master

reg   [3:0]  wbs_waits; // wait cycles befor WB Slave responds

reg   [7:0]  wbs_retries; // if RTY response, then this is the number of retries before ACK

reg [799:0]  test_name; // used for tb_log_file

//SD Card interface

wire sd_cmd_oe;

wire sd_dat_oe;

wire cmdIn;

wire [3:0] datIn;

trireg sd_cmd;

tri [3:0] sd_dat;

assign sd_cmd = sd_cmd_oe ? cmdIn: 1'bz;

assign sd_dat =  sd_dat_oe  ? datIn : 4'bz;

reg succes;

sdModel sdModelTB0

(

.sdClk (sd_clk_pad_o),

.cmd (sd_cmd),

.dat (sd_dat)

);

//Instaciate SD-Card controller

sdc_controller sd_controller_top_0

        (

         .wb_clk_i(wb_clk),

         .wb_rst_i(wb_rst),

         .wb_dat_i(wbs_sds_dat_i),

         .wb_dat_o(wbs_sds_dat_o),

         .wb_adr_i(wbs_sds_adr_i[7:0]),

         .wb_sel_i(wbs_sds_sel_i),

         .wb_we_i(wbs_sds_we_i),

         .wb_stb_i(wbs_sds_stb_i),

         .wb_cyc_i(wbs_sds_cyc_i),

         .wb_ack_o(wbs_sds_ack_o),

         .m_wb_adr_o(wbm_sdm_adr_o),

         .m_wb_sel_o(wbm_sdm_sel_o),

         .m_wb_we_o(wbm_sdm_we_o),

         .m_wb_dat_o(wbm_sdm_dat_o),

         .m_wb_dat_i(wbm_sdm_dat_i),

         .m_wb_cyc_o(wbm_sdm_cyc_o),

         .m_wb_stb_o(wbm_sdm_stb_o),

         .m_wb_ack_i(wbm_sdm_ack_i),

         .m_wb_cti_o(wbm_sdm_cti_o),

         .m_wb_bte_o(wbm_sdm_bte_o),

         .sd_cmd_dat_i(sd_cmd),

   .sd_cmd_out_o (cmdIn ),

         .sd_cmd_oe_o (sd_cmd_oe),

         .sd_dat_dat_i ( sd_dat  ),  //sd_dat_pad_io),

         .sd_dat_out_o (datIn  ) ,

   .sd_dat_oe_o ( sd_dat_oe  ),

         .sd_clk_o_pad  (sd_clk_pad_o)

          `ifdef SD_CLK_SEP

   ,sd_clk_i_pad

  `endif

  `ifdef IRQ_ENABLE

   ,.int_a (int_a),

    .int_b (int_b),

    .int_c (int_c)

  `endif

         );

integer host_log_file_desc;

WB_MASTER_BEHAVIORAL wb_master

(

    .CLK_I(wb_clk),

    .RST_I(wb_rst),

    .TAG_I(0), //Not in use

    .TAG_O(), //Not in use

    .ACK_I(wbs_sds_ack_o),

    .ADR_O(wbs_sds_adr_i), // only eth_sl_wb_adr_i[11:2] used

    .CYC_O(wbs_sds_cyc_i),

    .DAT_I(wbs_sds_dat_o),

    .DAT_O(wbs_sds_dat_i),

    .ERR_I(0),  //Not in use

    .RTY_I(1'b0),  // inactive (1'b0)

    .SEL_O(wbs_sds_sel_i),

    .STB_O(wbs_sds_stb_i),

    .WE_O (wbs_sds_we_i),

    .CAB_O()       // NOT USED for now!

);

integer memory_log_file_desc;

WB_SLAVE_BEHAVIORAL wb_slave

(

    .CLK_I(wb_clk),

    .RST_I(wb_rst),

    .ACK_O(wbm_sdm_ack_i),

    .ADR_I(wbm_sdm_adr_o),

    .CYC_I(wbm_sdm_cyc_o),

    .DAT_O(wbm_sdm_dat_i),

    .DAT_I(wbm_sdm_dat_o),

    .ERR_O(),

    .RTY_O(),      // NOT USED for now!

    .SEL_I(wbm_sdm_sel_o),

    .STB_I(wbm_sdm_stb_o),

    .WE_I (wbm_sdm_we_o),

    .CAB_I(1'b0)

);

 integer phy_log_file_desc;

integer wb_s_mon_log_file_desc ;

integer wb_m_mon_log_file_desc ;

/*WB_BUS_MON wb_eth_slave_bus_mon

(

  // WISHBONE common

  .CLK_I(wb_clk),

  .RST_I(wb_rst),

  // WISHBONE slave

  .ACK_I(wbs_sds_ack_o),

  .ADDR_O({24'h0,wbs_sds_adr_i[7:0]}),

  .CYC_O(wbs_sds_cyc_i),

  .DAT_I(wbs_sds_dat_o),

  .DAT_O(wbs_sds_dat_i),

  .ERR_I(0),

  .RTY_I(1'b0),

  .SEL_O(wbs_sds_sel_i),

  .STB_O(wbs_sds_stb_i),

  .WE_O (wbs_sds_we_i),

  .TAG_I(0),

`ifdef ETH_WISHBONE_B3

  .TAG_O(),

`else

  .TAG_O(5'h0),

`endif

  .CAB_O(1'b0),

`ifdef ETH_WISHBONE_B3

  .check_CTI          (1'b1),

`else

  .check_CTI          (1'b0),

`endif

  .log_file_desc (wb_s_mon_log_file_desc)

); */

WB_BUS_MON wb_eth_master_bus_mon

(

  // WISHBONE common

  .CLK_I(wb_clk),

  .RST_I(wb_rst),

  // WISHBONE master

  .ACK_I(wbm_sdm_ack_i),

  .ADDR_O(wbm_sdm_adr_o),

  .CYC_O(wbm_sdm_cyc_o),

  .DAT_I(wbm_sdm_dat_i),

  .DAT_O(wbm_sdm_dat_o),

  .ERR_I(0),

  .RTY_I(1'b0),

  .SEL_O(wbm_sdm_sel_o),

  .STB_O(wbm_sdm_stb_o),

  .WE_O (wbm_sdm_we_o),

  .TAG_I(0),

  .TAG_O(5'h0),

  .CAB_O(1'b0),

  .check_CTI(1'b0), // NO need

  .log_file_desc(wb_m_mon_log_file_desc)

);

reg StartTB;

integer card_rca;

initial

begin

  wait(StartTB);

  succes = 1'b0;

  // Initial global values

  tests_successfull = 0;

  tests_failed = 0;

  wbm_working = 0;

  card_rca=0;

  wbm_init_waits = 4'h1;

  wbm_subseq_waits = 4'h3;

  wbs_waits = 4'h1;

  wbs_retries = 8'h2;

  wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);

  // set DIFFERENT mrx_clk to mtx_clk!

//  eth_phy.set_mrx_equal_mtx = 1'b0;

  //  Call tests

  //  ----------

  //note test T5 only valid when SD is in Testmode (sd_tb_defines.v file)

   $display("T0 Start");

  test_access_to_reg(0, 1);           // 0 - 1 //Test RW registers  

  $display("");

  $display("===========================================================================");

  $display("T0 test_access_to_reg Completed");

  $display("===========================================================================");

  $display("T1 Start");

  test_send_cmd(0, 3);

  //   0:  Send CMD0, No Response                               ////

   //  1:  Send CMD3, 48-Bit Response, No error check

    //2:  Send CMD3, 48-Bit Response, All Error check   

  //   3:  Send CMD2, 136-Bit Response 

  $display("");

  $display("===========================================================================");

  $display("T1 test_send_cmd Completed");

  $display("===========================================================================");

 $display("T2 Start");

 test_init_sequnce(0, 1);

 $display("");

 $display("===========================================================================");

 $display("T2 test_init_sequence Completed");

 $display("===========================================================================");

  $display("T3 Start");

  test_send_data(0, 1);

  $display("");

  $display("===========================================================================");

  $display("T3 test_send_data Completed");

  $display("===========================================================================");

 // test_send_rec_data

  $display("T4 Start");

  test_send_rec_data(0, 1);

  $display("");

  $display("===========================================================================");

  $display("T4 test_send_rec_data Completed");

  $display("===========================================================================");

  //test_send_rec_data

   $display("T5 Start");

  test_send_cmd_error_rsp(0, 3);

 $display("");

 $display("===========================================================================");

 $display("T5 test_send_cmd_error_rsp Complete");

 $display("===========================================================================");

   //  test_send_rec_data_error_rsp

 //test_send_rec_data_error_rsp(0, 1);

// $display("");

//  $display("===========================================================================");

 // $display("T6 test_send_cmd_error_rsp Complete");

 // $display("===========================================================================");

 $display("All Tests past");

  succes = 1'b1;

end

integer     tb_log_file;

initial

begin

  tb_log_file = $fopen("../log/sdc_tb.log");

  if (tb_log_file < 2)

  begin

    $display("*E Could not open/create testbench log file in ../log/ directory!");

    $finish;

  end

  $fdisplay(tb_log_file, "========================== SD IP Core Testbench results ===========================");

  $fdisplay(tb_log_file, " ");

  phy_log_file_desc = $fopen("../log/eth_tb_phy.log");

  if (phy_log_file_desc < 2)

  begin

    $fdisplay(tb_log_file, "*E Could not open/create sd_tb_phy.log file in ../log/ directory!");

    $finish;

  end

  $fdisplay(phy_log_file_desc, "================ PHY Module  Testbench access log ================");

  $fdisplay(phy_log_file_desc, " ");

  memory_log_file_desc = $fopen("../log/sd_tb_memory.log");

  if (memory_log_file_desc < 2)

  begin

    $fdisplay(tb_log_file, "*E Could not open/create sd_tb_memory.log file in ../log/ directory!");

    $finish;

  end

  $fdisplay(memory_log_file_desc, "=============== MEMORY Module Testbench access log ===============");

  $fdisplay(memory_log_file_desc, " ");

  host_log_file_desc = $fopen("../log/eth_tb_host.log");

  if (host_log_file_desc < 2)

  begin

    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_host.log file in ../log/ directory!");

    $finish;

  end

  $fdisplay(host_log_file_desc, "================ HOST Module Testbench access log ================");

  $fdisplay(host_log_file_desc, " ");

  wb_s_mon_log_file_desc = $fopen("../log/eth_tb_wb_s_mon.log");

  if (wb_s_mon_log_file_desc < 2)

  begin

    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_s_mon.log file in ../log/ directory!");

    $finish;

  end

  $fdisplay(wb_s_mon_log_file_desc, "============== WISHBONE Slave Bus Monitor error log ==============");

  $fdisplay(wb_s_mon_log_file_desc, " ");

  $fdisplay(wb_s_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");

  $fdisplay(wb_s_mon_log_file_desc, " ");

  wb_m_mon_log_file_desc = $fopen("../log/eth_tb_wb_m_mon.log");

  if (wb_m_mon_log_file_desc < 2)

  begin

    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_m_mon.log file in ../log/ directory!");

    $finish;

  end

  $fdisplay(wb_m_mon_log_file_desc, "============= WISHBONE Master Bus Monitor  error log =============");

  $fdisplay(wb_m_mon_log_file_desc, " ");

  $fdisplay(wb_m_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");

  $fdisplay(wb_m_mon_log_file_desc, " ");

  // Reset pulse

  wb_rst =  1'b1;

  #423 wb_rst =  1'b0;

  // Clear memories

  //clear_memories;  

  #423 StartTB  =  1'b1;

end

// Generating WB_CLK_I clock

always

begin

  wb_clk=0;

//  forever #2.5 WB_CLK_I = ~WB_CLK_I;  // 2*2.5 ns -> 200.0 MHz    

//  forever #5 WB_CLK_I = ~WB_CLK_I;  // 2*5 ns -> 100.0 MHz    

//  forever #10 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 50.0 MHz    

  forever #12.5 wb_clk = ~wb_clk;  // 2*12.5 ns -> 40 MHz    

//  forever #15 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 33.3 MHz    

//  forever #20 WB_CLK_I = ~WB_CLK_I;  // 2*20 ns -> 25 MHz    

//  forever #25 WB_CLK_I = ~WB_CLK_I;  // 2*25 ns -> 20.0 MHz

//  forever #31.25 WB_CLK_I = ~WB_CLK_I;  // 2*31.25 ns -> 16.0 MHz    

//  forever #50 WB_CLK_I = ~WB_CLK_I;  // 2*50 ns -> 10.0 MHz

//  forever #55 WB_CLK_I = ~WB_CLK_I;  // 2*55 ns ->  9.1 MHz    

end

//TEST Cases

//

//

//

task test_send_cmd;

  input  [31:0]  start_task;

  input  [31:0]  end_task;

  integer        bit_start_1;

  integer        bit_end_1;

  integer        bit_start_2;

  integer        bit_end_2;

  integer        num_of_reg;

  integer        i_addr;

  integer        i_data;

  integer        i_length;

  integer        tmp_data;

  reg    [31:0]  tx_bd_num;

  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;

  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;

  integer        i;

  integer        i1;

  integer        i2;

  integer        i3;

  integer        fail;

  integer        test_num;

  reg    [31:0]  addr;

  reg    [31:0]  data;

  reg     [3:0]  sel;

  reg     [3:0]  rand_sel;

  reg    [31:0]  data_max;

  reg [31:0] rsp;

begin

// test_send_cmd

test_heading("Send CMD");

$display(" ");

$display("test_send_cmd TEST");

fail = 0;

// reset MAC registers

hard_reset;

//////////////////////////////////////////////////////////////////////

////                                                          ////

////  test_send_cmd:                                          ////

////                                                          ////

////                                ////

///   

///   0:  Send CMD3, 48-Bit Response, All Error check   

///                         ////

///   

//////////////////////////////////////////////////////////////////////

for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)

begin

  //////////////////////////////////////////////////////////////////////

  ////                                                          //// 

  //Test 0:  Send CMD, No Response                               ////

  //////////////////////////////////////////////////////////////////////

  if (test_num == 0) //

  begin

    test_name   = "0:  Send CMD, No Response  ";

    `TIME; $display("  TEST 0: 0:  Send CMD, No Response  ");

      wbm_init_waits = 0;

      wbm_subseq_waits = {$random} % 5;

     data = 0;

     rand_sel = 0;

     sel = 4'hF;

      //Reset Core

       addr = `SD_BASE + `software ;

       data = 1;

       wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

      //Setup timeout reg 

       addr = `SD_BASE + `timeout  ;

       data = 16'hff;

       wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

      //Clock divider /2 

        addr = `SD_BASE + `clock_d   ;

       data = 16'h0;

       wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

      //Start Core

       addr = `SD_BASE + `software ;

       data = 0;

       wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

      //Setup settings 

       addr = `SD_BASE + `command ;

       data = 0; //CMD index 0, Erro check =0, rsp = 0;

       wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

      //Argument settings 

       addr = `SD_BASE + `argument  ;

       data = 0; //CMD index 0, Erro check =0, rsp = 0;

       wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

      //wait for send finnish

       addr = `SD_BASE + `normal_isr   ;

       data = 0; //CMD index 0, Erro check =0, rsp = 0;

       wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);

       while (tmp_data != 1)

         wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);

       if (tmp_data[15]) begin

         fail = fail + 1;

         test_fail_num("Error occured when sending CMD0 in TEST0", i_addr);

         `TIME;

        $display("Normal status register is not 0x1: %h", tmp_data);

       end

    end

  end

   if(fail == 0)

      test_ok;

    else

      fail = 0;

  end

endtask

task test_send_rec_data_error_rsp;

input  [31:0]  start_task;

  input  [31:0]  end_task;

  integer        bit_start_1;

  integer        bit_end_1;

  integer        bit_start_2;

  integer        bit_end_2;

  integer        num_of_reg;

  integer        i_addr;

  integer        i_data;

  integer        i_length;

  integer        tmp_data;

    integer        resp_data;

  reg    [31:0]  tx_bd_num;

  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;

  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;

  integer        i;

  integer        i1;

  integer        i2;

  integer        i3;

  integer        fail;

  integer        test_num;

  reg    [31:0]  addr;

  reg    [31:0]  data;

  reg     [3:0]  sel;

  reg     [3:0]  rand_sel;

  reg    [31:0]  data_max;

  reg [31:0] rsp;

begin

// access_to_reg

test_heading("access_to_reg");

$display(" ");

$display("access_to_reg TEST");

fail = 0;

resp_data = 0;

// reset MAC registers

hard_reset;

for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)

begin

  //////////////////////////////////////////////////////////////////////

  ////                                                          //// 

  //Test 3.0:  Init sequence, With response check  

  //CMD 0. Reset Card

  //CMD 8. Get voltage (Only 2.0 Card response to this)            ////

  //CMD55. Indicate Next Command are Application specific

  //ACMD44. Get Voltage windows

  //CMD2. CID reg

  //CMD3. Get RCA.

  //////////////////////////////////////////////////////////////////////

  if (test_num == 0) //

  begin

    test_name   = "4.0:  Send data ";

    `TIME; $display("  TEST 4.0:   Send data  ");

      wbm_init_waits = 0;

      wbm_subseq_waits = {$random} % 5;

     data = 0;

     rand_sel = 0;

     sel = 4'hF;

      //Reset Core