URL https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk

Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_dma/] [verilog/] [sd_clock_divider.v] - Blame information for rev 134

Details | Compare with Previous | View Log


`include "sd_defines.v"//nononw
module sd_clock_divider (
  input wire CLK,
  input  [7:0] DIVIDER,
  input wire RST,
  output  SD_CLK
  );
 
  reg [7:0] ClockDiv;
  reg SD_CLK_O;
`ifdef SYN
  `ifdef ACTEL
  CLKINT CLKA
  (.A (SD_CLK_O),
   .Y (SD_CLK)
   );
   `endif
 `endif
 
 `ifdef SIM
   assign SD_CLK = SD_CLK_O;
`endif
 
always @ (posedge CLK or posedge RST)
begin
 if (RST) begin
    ClockDiv <=8'b0000_0000;
    SD_CLK_O  <= 0;
 end
 else if (ClockDiv == DIVIDER )begin
    ClockDiv  <= 0;
    SD_CLK_O <=  ~SD_CLK_O;
 end else begin
    ClockDiv  <= ClockDiv + 1;
    SD_CLK_O <=  SD_CLK_O;
end
 
end
 endmodule
 
 

Line No.	Rev	Author	Line
1	134	tac2	`include "sd_defines.v"//nononw
2			`module sd_clock_divider (`
3			`input wire CLK,`
4			`input [7:0] DIVIDER,`
5			`input wire RST,`
6			`output SD_CLK`
7			`);`
8
9			`reg [7:0] ClockDiv;`
10			`reg SD_CLK_O;`
11			`ifdef SYN
12			`ifdef ACTEL
13			`CLKINT CLKA`
14			`(.A (SD_CLK_O),`
15			`.Y (SD_CLK)`
16			`);`
17			`endif
18			`endif
19
20			`ifdef SIM
21			`assign SD_CLK = SD_CLK_O;`
22			`endif
23
24			`always @ (posedge CLK or posedge RST)`
25			`begin`
26			`if (RST) begin`
27			`ClockDiv <=8'b0000_0000;`
28			`SD_CLK_O <= 0;`
29			`end`
30			`else if (ClockDiv == DIVIDER )begin`
31			`ClockDiv <= 0;`
32			`SD_CLK_O <= ~SD_CLK_O;`
33			`end else begin`
34			`ClockDiv <= ClockDiv + 1;`
35			`SD_CLK_O <= SD_CLK_O;`
36			`end`
37
38			`end`
39			`endmodule`
40
41

Browse

Tools

Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_dma/] [verilog/] [sd_clock_divider.v] - Blame information for rev 134