OpenCores
URL https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk

Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_dma/] [verilog/] [sd_cmd_master.v] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 134 tac2 
`include "sd_defines.v"
2 
module sd_cmd_master(
3 
input CLK_PAD_IO,
4 
 
5 
input RST_PAD_I,
6 
input New_CMD,
7 
input data_write,
8 
input data_read,
9 
 
10 
 
11 
 
12 
input [31:0]ARG_REG,
13 
input [13:0]CMD_SET_REG,
14 
input [15:0] TIMEOUT_REG,
15 
output reg [15:0] STATUS_REG,
16 
output reg [31:0] RESP_1_REG,
17 
 
18 
output reg [4:0] ERR_INT_REG,
19 
output reg [15:0] NORMAL_INT_REG,
20 
input ERR_INT_RST,
21 
input NORMAL_INT_RST,
22 
 
23 
output reg [15:0] settings,
24 
output reg go_idle_o,
25 
output reg  [39:0] cmd_out,
26 
output reg req_out,
27 
output reg ack_out,
28 
input req_in,
29 
input ack_in,
30 
input [39:0] cmd_in,
31 
input [15:0] serial_status,
32 
input card_detect
33 
);
34 
 
35 
 
36 
 
37 
 
38 
 
39 
 
40 
 
41 
 
42 
 
43 
`define dat_ava status[6]
44 
`define crc_valid status[5]
45 
`define small_rsp 7'b0101000
46 
`define big_rsp 7'b1111111
47 
 
48 
`define CMDI CMD_SET_REG[13:8]
49 
`define WORD_SELECT CMD_SET_REG[7:6]
50 
`define CICE CMD_SET_REG[4]
51 
`define CRCE CMD_SET_REG[3]
52 
`define RTS CMD_SET_REG[1:0]
53 
`define CTE ERR_INT_REG[0]
54 
`define CCRCE ERR_INT_REG[1]
55 
`define CIE  ERR_INT_REG[3]
56 
`define EI NORMAL_INT_REG[15]
57 
`define CC  NORMAL_INT_REG[0]
58 
`define CICMD STATUS_REG[0]
59 
 
60 
 
61 
//-----------Types--------------------------------------------------------
62 
 
63 
reg CRC_check_enable;
64 
reg index_check_enable;
65 
reg [6:0]response_size;
66 
 
67 
 
68 
reg card_present;
69 
 
70 
 
71 
reg [3:0]debounce;
72 
 
73 
reg [15:0]status;
74 
reg [15:0]  Watchdog_Cnt;
75 
reg complete;
76 
 
77 
 
78 
 
79 
parameter SIZE = 3;
80 
reg [SIZE-1:0] state;
81 
reg [SIZE-1:0] next_state;
82 
 
83 
parameter IDLE   =  3'b001;
84 
parameter SETUP   =  3'b010;
85 
parameter EXECUTE  =  3'b100;
86 
reg ack_in_int;
87 
reg ack_q;
88 
reg req_q;
89 
reg req_in_int;
90 
 
91 
always @ (posedge CLK_PAD_IO or posedge RST_PAD_I   )
92 
begin
93 
  if (RST_PAD_I) begin
94 
    req_q<=0;
95 
    req_in_int<=0;
96 
 end
97 
else begin
98 
  req_q<=req_in;
99 
  req_in_int<=req_q;
100 
end
101 
end
102 
 
103 
//---------------Input ports---------------
104 
 
105 
/*
106 
always @ (posedge CLK_PAD_IO or posedge RST_PAD_I   )
107 
begin
108 
  if (RST_PAD_I) begin
109 
    debounce<=0;
110 
    card_present<=0;
111 
 end
112 
else begin
113 
        if (!card_detect) begin//Card present
114 
                if (debounce!=4'b1111)
115 
                        debounce<=debounce+1'b1;
116 
        end
117 
        else
118 
                 debounce<=0;
119 
 
120 
        if (debounce==4'b1111)
121 
       card_present<=1'b1;
122 
        else
123 
           card_present<=1'b0;
124 
end
125 
end
126 
*/
127 
 
128 
 
129 
always @ (posedge CLK_PAD_IO or posedge RST_PAD_I   )
130 
begin
131 
  if (RST_PAD_I) begin
132 
    ack_q<=0;
133 
    ack_in_int<=0;
134 
 end
135 
else begin
136 
  ack_q<=ack_in;
137 
  ack_in_int<=ack_q;
138 
end
139 
 
140 
 
141 
end
142 
 
143 
 
144 
 
145 
always @ ( state or New_CMD or complete or ack_in_int )
146 
begin : FSM_COMBO
147 
    next_state = 0;
148 
 
149 
 case(state)
150 
 IDLE:   begin
151 
      if (New_CMD) begin
152 
          next_state = SETUP;
153 
      end
154 
      else begin
155 
         next_state = IDLE;
156 
      end
157 
 end
158 
 SETUP:begin
159 
    if (ack_in_int)
160 
       next_state = EXECUTE;
161 
     else
162 
       next_state = SETUP;
163 
   end
164 
 EXECUTE:    begin
165 
       if (complete) begin
166 
          next_state = IDLE;
167 
      end
168 
      else begin
169 
         next_state = EXECUTE;
170 
      end
171 
 end
172 
 
173 
 
174 
 default : next_state  = IDLE;
175 
 
176 
 endcase
177 
 
178 
end
179 
 
180 
 
181 
 
182 
 
183 
always @ (posedge CLK_PAD_IO or posedge RST_PAD_I   )
184 
begin : FSM_SEQ
185 
  if (RST_PAD_I ) begin
186 
    state <= #1 IDLE;
187 
 end
188 
 else begin
189 
    state <= #1 next_state;
190 
 end
191 
end
192 
 
193 
 
194 
 
195 
always @ (posedge CLK_PAD_IO or posedge RST_PAD_I   )
196 
begin
197 
 if (RST_PAD_I ) begin
198 
    CRC_check_enable=0;
199 
    complete =0;
200 
    RESP_1_REG = 0;
201 
 
202 
    ERR_INT_REG =0;
203 
    NORMAL_INT_REG=0;
204 
    STATUS_REG=0;
205 
    status=0;
206 
    cmd_out =0 ;
207 
    settings=0;
208 
    response_size=0;
209 
    req_out=0;
210 
    index_check_enable=0;
211 
    ack_out=0;
212 
    Watchdog_Cnt=0;
213 
 
214 
    `CCRCE=0;
215 
    `EI = 0;
216 
    `CC = 0;
217 
     go_idle_o=0;
218 
 end
219 
 else begin
220 
 NORMAL_INT_REG[1] = card_present;
221 
 NORMAL_INT_REG[2] = ~card_present;
222 
 complete=0;
223 
 case(state)
224 
 IDLE: begin
225 
    go_idle_o=0;
226 
    req_out=0;
227 
                ack_out =0;
228 
                `CICMD =0;
229 
    if ( req_in_int == 1) begin     //Status change
230 
        status=serial_status;
231 
        ack_out = 1;
232 
 
233 
 
234 
    end
235 
 end
236 
 SETUP:  begin
237 
 
238 
     NORMAL_INT_REG=0;
239 
     ERR_INT_REG =0;
240 
 
241 
     index_check_enable = `CICE;
242 
     CRC_check_enable = `CRCE;
243 
 
244 
    if ( (`RTS  == 2'b10 ) || ( `RTS == 2'b11)) begin
245 
      response_size =  7'b0101000;
246 
    end
247 
    else if (`RTS == 2'b01) begin
248 
      response_size = 7'b1111111;
249 
    end
250 
    else begin
251 
       response_size=0;
252 
    end
253 
 
254 
    cmd_out[39:38]=2'b01;
255 
    cmd_out[37:32]=`CMDI;  //CMD_INDEX
256 
    cmd_out[31:0]= ARG_REG;           //CMD_Argument
257 
    settings[14:13]=`WORD_SELECT;             //Reserved
258 
    settings[12] = data_read; //Type of command
259 
    settings[11] = data_write;
260 
    settings[10:8]=3'b111;            //Delay
261 
    settings[7]=`CRCE;         //CRC-check
262 
    settings[6:0]=response_size;   //response size
263 
    Watchdog_Cnt = 0;
264 
 
265 
    `CICMD =1;
266 
 end
267 
 
268 
 EXECUTE: begin
269 
    Watchdog_Cnt = Watchdog_Cnt +1;
270 
    if (Watchdog_Cnt>TIMEOUT_REG) begin
271 
      `CTE=1;
272 
      `EI = 1;
273 
      if (ack_in == 1) begin
274 
         complete=1;
275 
      end
276 
      go_idle_o=1;
277 
    end
278 
 
279 
    //Default
280 
    req_out=0;
281 
                ack_out =0;
282 
 
283 
    //Start sending when serial module is ready
284 
        if (ack_in_int == 1) begin
285 
                        req_out =1;
286 
          end
287 
           //Incoming New Status
288 
          else if ( req_in_int == 1) begin
289 
        status=serial_status;
290 
 
291 
        ack_out = 1;
292 
        if ( `dat_ava ) begin //Data avaible
293 
           complete=1;
294 
            `EI = 0;
295 
 
296 
           if (CRC_check_enable & ~`crc_valid) begin
297 
            `CCRCE=1;
298 
            `EI = 1;
299 
 
300 
           end
301 
           if (index_check_enable &  (cmd_out[37:32] != cmd_in [37:32]) ) begin
302 
            `CIE=1;
303 
            `EI = 1;
304 
 
305 
           end
306 
 
307 
 
308 
             `CC = 1;
309 
 
310 
             if (response_size !=0)
311 
              RESP_1_REG=cmd_in[31:0];
312 
 
313 
          // end
314 
         end ////Data avaible
315 
       end //Status change
316 
     end //EXECUTE state
317 
   endcase
318 
   if (ERR_INT_RST)
319 
     ERR_INT_REG=0;
320 
   if (NORMAL_INT_RST)
321 
     NORMAL_INT_REG=0;
322 
  end
323 
end
324 
 
325 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.