OpenCores
URL https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk

Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_dma/] [verilog/] [sd_defines.v] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 134 tac2
//Read the documentation before changing values
2
 
3
`define BIG_ENDIAN
4
//`define LITLE_ENDIAN
5
 
6
//`define SIM
7
`define SYN
8
 
9
`define SDC_IRQ_ENABLE
10
 
11
`define ACTEL
12
 
13
//`define CUSTOM
14
//`define ALTERA
15
//`define XLINX
16
//`define SIMULATOR
17
 
18
`define RESEND_MAX_CNT 3
19
 
20
//MAX 255 BD
21
//BD size/4 
22
 
23
`ifdef ACTEL
24
        `define BD_WIDTH 5
25
        `define BD_SIZE 32
26
        `define RAM_MEM_WIDTH_16
27
        `define RAM_MEM_WIDTH 16
28
 
29
`endif
30
 
31
//`ifdef CUSTOM
32
 //  `define NR_O_BD_4 
33
//   `define BD_WIDTH 5
34
//   `define BD_SIZE 32      
35
//   `define RAM_MEM_WIDTH_32
36
//   `define RAM_MEM_WIDTH 32
37
//`endif
38
 
39
 
40
 
41
`ifdef SYN
42
  `define RESET_CLK_DIV 0
43
  `define MEM_OFFSET 4
44
`endif
45
 
46
`ifdef SIM
47
  `define RESET_CLK_DIV 0
48
  `define MEM_OFFSET 4
49
`endif
50
 
51
//SD-Clock Defines ---------
52
//Use bus clock or a seperate clock
53
`define SDC_CLK_BUS_CLK
54
//`define SDC_CLK_SEP
55
 
56
// Use of internal clock divider
57
//`define SDC_CLK_STATIC
58
`define SDC_CLK_DYNAMIC
59
 
60
 
61
//SD DATA-transfer defines---
62
`define BLOCK_SIZE 512
63
`define SD_BUS_WIDTH_4
64
`define SD_BUS_W 4
65
 
66
//at 512 bytes per block, equal 1024 4 bytes writings with a bus width of 4, add 2 for startbit and Z bit.
67
//Add 18 for crc, endbit and z.
68
`define BIT_BLOCK 1044
69
`define CRC_OFF 19
70
`define BIT_BLOCK_REC 1024
71
`define BIT_CRC_CYCLE 16
72
 
73
 
74
//FIFO defines---------------
75
`define FIFO_RX_MEM_DEPTH 8
76
`define FIFO_RX_MEM_ADR_SIZE 4
77
 
78
`define FIFO_TX_MEM_DEPTH 8
79
`define FIFO_TX_MEM_ADR_SIZE 4
80
//---------------------------
81
 
82
 
83
 
84
 
85
 
86
 
87
 
88
 
89
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.