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[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_dma/] [verilog/] [sd_tx_fifo.v] - Blame information for rev 134

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`include "timescale.v"
`include "sd_defines.v"
module sd_tx_fifo
  (
   input [32-1:0] d,
   input wr,
   input wclk,
   output [32-1:0] q,
   input rd,
   output full,
   output empty,
   output [5:0] mem_empt,
   input rclk,
   input rst
   );
 
   reg [32-1:0] ram [0:`FIFO_TX_MEM_DEPTH-1]; //synthesis syn_ramstyle = "no_rw_check"
   reg [`FIFO_TX_MEM_ADR_SIZE-1:0] adr_i, adr_o;
   wire ram_we;
   wire [32-1:0] ram_din;
 
 
 
   assign ram_we = wr & ~full;
   assign ram_din = d;
 
   always @ (posedge wclk)
     if (ram_we)
       ram[adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0]] <= ram_din;
 
   always @ (posedge wclk or posedge rst)
     if (rst)
       adr_i <= `FIFO_TX_MEM_ADR_SIZE'h0;
     else
       if (ram_we)
         if (adr_i == `FIFO_TX_MEM_DEPTH-1) begin
                adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;
                adr_i[`FIFO_TX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_TX_MEM_ADR_SIZE-1];
            end
             else
              adr_i <= adr_i + `FIFO_TX_MEM_ADR_SIZE'h1;
 
 
   always @ (posedge rclk or posedge rst)
     if (rst)
       adr_o <= `FIFO_TX_MEM_ADR_SIZE'h0;
     else
       if (!empty & rd) begin
 
         if (adr_o == `FIFO_TX_MEM_DEPTH-1) begin
            adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;
            adr_o[`FIFO_TX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_TX_MEM_ADR_SIZE-1];
         end
         else
           adr_o <= adr_o + `FIFO_TX_MEM_ADR_SIZE'h1;
         end
//------------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//------------------------------------------------------------------
 
 
   assign full=  ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) &  (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;
   assign empty = (adr_i == adr_o) ;
 
   assign mem_empt = ( adr_i-adr_o);
   assign q = ram[adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0]];
endmodule
 

Line No.	Rev	Author	Line
1	134	tac2
2			`include "timescale.v"
3			`include "sd_defines.v"
4			`module sd_tx_fifo`
5			`(`
6			`input [32-1:0] d,`
7			`input wr,`
8			`input wclk,`
9			`output [32-1:0] q,`
10			`input rd,`
11			`output full,`
12			`output empty,`
13			`output [5:0] mem_empt,`
14			`input rclk,`
15			`input rst`
16			`);`
17
18			reg [32-1:0] ram [0:`FIFO_TX_MEM_DEPTH-1]; //synthesis syn_ramstyle = "no_rw_check"
19			reg [`FIFO_TX_MEM_ADR_SIZE-1:0] adr_i, adr_o;
20			`wire ram_we;`
21			`wire [32-1:0] ram_din;`
22
23
24
25			`assign ram_we = wr & ~full;`
26			`assign ram_din = d;`
27
28			`always @ (posedge wclk)`
29			`if (ram_we)`
30			ram[adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0]] <= ram_din;
31
32			`always @ (posedge wclk or posedge rst)`
33			`if (rst)`
34			adr_i <= `FIFO_TX_MEM_ADR_SIZE'h0;
35			`else`
36			`if (ram_we)`
37			if (adr_i == `FIFO_TX_MEM_DEPTH-1) begin
38			adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;
39			adr_i[`FIFO_TX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_TX_MEM_ADR_SIZE-1];
40			`end`
41			`else`
42			adr_i <= adr_i + `FIFO_TX_MEM_ADR_SIZE'h1;
43
44
45			`always @ (posedge rclk or posedge rst)`
46			`if (rst)`
47			adr_o <= `FIFO_TX_MEM_ADR_SIZE'h0;
48			`else`
49			`if (!empty & rd) begin`
50
51			if (adr_o == `FIFO_TX_MEM_DEPTH-1) begin
52			adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;
53			adr_o[`FIFO_TX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_TX_MEM_ADR_SIZE-1];
54			`end`
55			`else`
56			adr_o <= adr_o + `FIFO_TX_MEM_ADR_SIZE'h1;
57			`end`
58			`//------------------------------------------------------------------`
59			`// Simplified version of the three necessary full-tests:`
60			`// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&`
61			`// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&`
62			`// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));`
63			`//------------------------------------------------------------------`
64
65
66			assign full= ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;
67			`assign empty = (adr_i == adr_o) ;`
68
69			`assign mem_empt = ( adr_i-adr_o);`
70			assign q = ram[adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0]];
71			`endmodule`
72

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[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_dma/] [verilog/] [sd_tx_fifo.v] - Blame information for rev 134