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tac2 |
--Require Modelsim
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--Tested on Modelsim 6.5b Revison 2009.05
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puts {
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ModelSimSE SD_HOST_CONTROLLER compile script version 1.1
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Copyright (c) Doulos June 2004, SD
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}
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# Simply change the project settings in this section
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# for each new project. There should be no need to
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# modify the rest of the script.
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set library_file_list {
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design_library {
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../../../rtl/sdc_dma/verilog/SD_defines.v
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../../../rtl/sdc_dma/verilog/SD_Bd.v
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../../../rtl/sdc_dma/verilog/SD_clock_divider.v
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../../../rtl/sdc_dma/verilog/SD_cmd_master.v
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../../../rtl/sdc_dma/verilog/SD_cmd_serial_host.v
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../../../rtl/sdc_dma/verilog/SD_controller_top.v
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../../../rtl/sdc_dma/verilog/SD_controller_wb.v
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../../../rtl/sdc_dma/verilog/SD_crc_7.v
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../../../rtl/sdc_dma/verilog/SD_crc_16.v
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../../../rtl/sdc_dma/verilog/SD_data_host.v
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../../../rtl/sdc_dma/verilog/SD_data_master.v
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../../../rtl/sdc_dma/verilog/SD_FIFO_RX_Filler.v
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../../../rtl/sdc_dma/verilog/SD_FIFO_TX_Filler.v
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}
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test_library { ../../../bench/sdc_dma/verilog/wb_model_defines.v
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../../../bench/sdc_dma/verilog/SD_controller_top_tb.v
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../../../bench/sdc_dma/verilog/sdModel.v
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../../../bench/sdc_dma/verilog/timescale.v
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../../../bench/sdc_dma/verilog/wb_bus_mon.v
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../../../bench/sdc_dma/verilog/wb_master32.v
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../../../bench/sdc_dma/verilog/wb_master_behavioral.v
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../../../bench/sdc_dma/verilog/wb_slave_behavioral.v
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../../../rtl/sdc_dma/verilog/SD_defines.v
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../../../rtl/sdc_dma/verilog/SD_Bd.v
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../../../rtl/sdc_dma/verilog/SD_clock_divider.v
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../../../rtl/sdc_dma/verilog/SD_cmd_master.v
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../../../rtl/sdc_dma/verilog/SD_cmd_serial_host.v
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../../../rtl/sdc_dma/verilog/SD_controller_top.v
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../../../rtl/sdc_dma/verilog/SD_controller_wb.v
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../../../rtl/sdc_dma/verilog/SD_crc_7.v
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../../../rtl/sdc_dma/verilog/SD_crc_16.v
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../../../rtl/sdc_dma/verilog/SD_data_host.v
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../../../rtl/sdc_dma/verilog/SD_data_master.v
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../../../rtl/sdc_dma/verilog/SD_FIFO_RX_Filler.v
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../../../rtl/sdc_dma/verilog/SD_FIFO_TX_Filler.v
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../../../rtl/sdc_dma/verilog/fifo/smii_rx_fifo.v
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../../../rtl/sdc_dma/verilog/fifo/smii_tx_fifo.v
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}
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}
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set top_level test_library.SD_controller_top_tb
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set wave_patterns {
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/*
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}
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set wave_radices {
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hexadecimal {data q}
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}
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puts {
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Script commands are:
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r = Recompile changed and dependent files
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rr = Recompile everything
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q = Quit without confirmation
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}
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# After sourcing the script from ModelSim for the
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# first time use these commands to recompile.
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proc r {} {uplevel #0 source compile.tcl}
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proc rr {} {global last_compile_time
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set last_compile_time 0
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r }
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proc q {} {quit -force }
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#Does this installation support Tk?
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set tk_ok 1
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if [catch {package require Tk}] {set tk_ok 0}
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# Prefer a fixed point font for the transcript
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set PrefMain(font) {Courier 10 roman normal}
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# Compile out of date files
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set time_now [clock seconds]
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if [catch {set last_compile_time}] {
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set last_compile_time 0
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}
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foreach {library file_list} $library_file_list {
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vlib $library
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vmap work $library
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foreach file $file_list {
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if { $last_compile_time < [file mtime $file] } {
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if [regexp {.vhdl?$} $file] {
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vcom -93 $file
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} else {
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vlog +incdir+../../../rtl/sdc_dma/verilog/ +incdir+../../../bench/sdc_dma/verilog/ $file
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}
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set last_compile_time 0
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}
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}
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}
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set last_compile_time $time_now
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# Load the simulation
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eval vsim $top_level
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# If waves are required
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if [llength $wave_patterns] {
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noview wave
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foreach pattern $wave_patterns {
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add wave $pattern
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}
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configure wave -signalnamewidth 1
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foreach {radix signals} $wave_radices {
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foreach signal $signals {
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catch {property wave -radix $radix $signal}
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}
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}
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if $tk_ok {wm geometry .wave [winfo screenwidth .]x330+0-20}
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}
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# Run the simulation
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# run -all
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# If waves are required
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if [llength $wave_patterns] {
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if $tk_ok {.wave.tree zoomfull}
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}
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# How long since project began?
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if {[file isfile start_time.txt] == 0} {
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set f [open start_time.txt w]
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puts $f "Start time was [clock seconds]"
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close $f
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} else {
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set f [open start_time.txt r]
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set line [gets $f]
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close $f
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regexp {\d+} $line start_time
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set total_time [expr ([clock seconds]-$start_time)/60]
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puts "Project time is $total_time minutes"
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}
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