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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bs_convert.v] - Blame information for rev 44

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1 3 dinesha
/*********************************************************************
2
 
3
  SDRAM Controller buswidth converter
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5
  This file is part of the sdram controller project
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  http://www.opencores.org/cores/sdr_ctrl/
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8
  Description: SDRAM Controller Buswidth converter
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10
  This module does write/read data transalation between
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     application data to SDRAM bus width
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  To Do:
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    nothing
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16
  Author(s):
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      - Dinesh Annayya, dinesha@opencores.org
18 44 dinesha
  Version  :  0.0  - 8th Jan 2012 - Initial structure
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              0.2 - 2nd Feb 2012
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                 Improved the command pipe structure to accept up-to 4 command of different bank.
21 3 dinesha
 
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24
 Copyright (C) 2000 Authors and OPENCORES.ORG
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26
 This source file may be used and distributed without
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 restriction provided that this copyright statement is not
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 removed from the file and that any derivative work contains
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 the original copyright notice and the associated disclaimer.
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 This source file is free software; you can redistribute it
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 and/or modify it under the terms of the GNU Lesser General
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 Public License as published by the Free Software Foundation;
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 either version 2.1 of the License, or (at your option) any
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later version.
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 This source is distributed in the hope that it will be
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 useful, but WITHOUT ANY WARRANTY; without even the implied
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 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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 PURPOSE.  See the GNU Lesser General Public License for more
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 details.
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 You should have received a copy of the GNU Lesser General
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 Public License along with this source; if not, download it
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 from http://www.opencores.org/lgpl.shtml
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47
*******************************************************************/
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49 37 dinesha
`include "sdrc_define.v"
50 3 dinesha
module sdrc_bs_convert (
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                    clk,
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                    reset_n,
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                    sdr_width,
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55 44 dinesha
        /* Control Signal from xfr ctrl */
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                    x2a_rdstart,
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                    x2a_wrstart,
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                    x2a_rdlast,
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                    x2a_wrlast,
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                    app_rd_data_int,
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                    app_rd_valid_int,
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                    app_wr_data_int,
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                    app_wr_en_n_int,
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                    app_wr_next_int,
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       /* Control Signal from request ctrl */
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                    app_req_addr_int,
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                    app_req_len_int,
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                    app_req_ack_int,
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                    app_sdr_req_int,
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   /* Control Signal from Bank Ctrl  */
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                    app_req_dma_last_int,
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   /*  Control Signal from/to to application i/f  */
76 3 dinesha
                    app_req_addr,
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                    app_req_len,
78 4 dinesha
                    app_sdr_req,
79 3 dinesha
                    app_req_dma_last,
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                    app_req_wr_n,
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                    app_req_ack,
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                    app_wr_data,
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                    app_wr_en_n,
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                    app_wr_next,
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                    app_rd_data,
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                    app_rd_valid
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                );
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parameter  APP_AW   = 30;  // Application Address Width
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parameter  APP_DW   = 32;  // Application Data Width 
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parameter  APP_BW   = 4;   // Application Byte Width
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parameter  APP_RW   = 9;   // Application Request Width
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parameter  SDR_DW   = 16;  // SDR Data Width 
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parameter  SDR_BW   = 2;   // SDR Byte Width
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input                    clk;
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input                    reset_n ;
98 16 dinesha
input [1:0]             sdr_width           ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
99 3 dinesha
 
100 44 dinesha
/* Control Signal from xfr ctrl */
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input                    x2a_rdstart; // read start indication
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input                    x2a_wrstart; // writ start indication
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input                    x2a_rdlast; //  read last burst access
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input                    x2a_wrlast; // write last transfer
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input [SDR_DW-1:0]       app_rd_data_int;
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input                    app_rd_valid_int;
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output [SDR_DW-1:0]      app_wr_data_int;
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output [SDR_BW-1:0]      app_wr_en_n_int;
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input                    app_wr_next_int;
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/* Control Signal from request ctrl */
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output [APP_AW:0]        app_req_addr_int;
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output [APP_RW-1:0]      app_req_len_int;
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input                    app_req_ack_int;
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output                   app_sdr_req_int;
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/* Control Signal from Bank Ctrl  */
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output                   app_req_dma_last_int;
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120
 
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/*  Control Signal from/to to application i/f  */
122 3 dinesha
input [APP_AW-1:0]       app_req_addr;
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input  [APP_RW-1:0]      app_req_len ;
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input                    app_req_wr_n;
125 4 dinesha
input                    app_sdr_req;
126 3 dinesha
input                    app_req_dma_last;
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output                   app_req_dma_last_int;
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output                   app_req_ack;
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input  [APP_DW-1:0]      app_wr_data;
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input  [APP_BW-1:0]      app_wr_en_n;
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output                   app_wr_next;
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output [APP_DW-1:0]      app_rd_data;
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output                   app_rd_valid;
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reg [APP_AW:0]           app_req_addr_int;
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reg [APP_RW-1:0]         app_req_len_int;
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reg                      app_req_dma_last_int;
141 4 dinesha
reg                      app_sdr_req_int;
142 3 dinesha
reg                      app_req_ack;
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reg [APP_DW-1:0]         app_rd_data;
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reg                      app_rd_valid;
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reg [SDR_DW-1:0]         app_wr_data_int;
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reg [SDR_BW-1:0]         app_wr_en_n_int;
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reg                      app_wr_next;
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150 16 dinesha
reg [23:0]               saved_rd_data;
151 44 dinesha
reg [1:0]                rd_xfr_count;
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reg [1:0]                wr_xfr_count;
153 3 dinesha
 
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wire                  ok_to_req;
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157 16 dinesha
assign ok_to_req = ((wr_xfr_count == 0) && (rd_xfr_count == 0));
158 3 dinesha
 
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always @(*) begin
160 16 dinesha
        if(sdr_width == 2'b00) // 32 Bit SDR Mode
161 3 dinesha
          begin
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            app_req_addr_int = {1'b0,app_req_addr};
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            app_req_len_int = app_req_len;
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            app_wr_data_int = app_wr_data;
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            app_wr_en_n_int = app_wr_en_n;
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            app_req_dma_last_int = app_req_dma_last;
167 4 dinesha
            app_sdr_req_int = app_sdr_req;
168 3 dinesha
            app_wr_next = app_wr_next_int;
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            app_rd_data = app_rd_data_int;
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            app_rd_valid = app_rd_valid_int;
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            app_req_ack = app_req_ack_int;
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          end
173 16 dinesha
        else if(sdr_width == 2'b01) // 16 Bit SDR Mode
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        begin
175 3 dinesha
           // Changed the address and length to match the 16 bit SDR Mode
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            app_req_addr_int = {app_req_addr,1'b0};
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            app_req_len_int = {app_req_len,1'b0};
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            app_req_dma_last_int = app_req_dma_last;
179 44 dinesha
            //app_sdr_req_int = app_sdr_req && ok_to_req;
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            app_sdr_req_int = app_sdr_req ;
181 3 dinesha
            app_req_ack = app_req_ack_int;
182 16 dinesha
            app_wr_next = (app_wr_next_int & wr_xfr_count[0]);
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            app_rd_valid = (rd_xfr_count & rd_xfr_count[0]);
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            if(wr_xfr_count[0] == 1'b1)
185 3 dinesha
              begin
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                app_wr_en_n_int = app_wr_en_n[3:2];
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                app_wr_data_int = app_wr_data[31:16];
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              end
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            else
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              begin
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                app_wr_en_n_int = app_wr_en_n[1:0];
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                app_wr_data_int = app_wr_data[15:0];
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              end
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195 16 dinesha
            app_rd_data = {app_rd_data_int,saved_rd_data[15:0]};
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        end else  // 8 Bit SDR Mode
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        begin
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           // Changed the address and length to match the 16 bit SDR Mode
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            app_req_addr_int = {app_req_addr,2'b0};
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            app_req_len_int = {app_req_len,2'b0};
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            app_req_dma_last_int = app_req_dma_last;
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            app_sdr_req_int = app_sdr_req && ok_to_req;
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            app_req_ack = app_req_ack_int;
204 44 dinesha
            app_wr_next = (app_wr_next_int & (wr_xfr_count[1:0]== 2'b11));
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            app_rd_valid = (rd_xfr_count &   (rd_xfr_count[1:0]== 2'b11));
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            if(wr_xfr_count[1:0] == 2'b11)
207 3 dinesha
            begin
208 16 dinesha
                app_wr_en_n_int = app_wr_en_n[3];
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                app_wr_data_int = app_wr_data[31:24];
210 3 dinesha
            end
211 16 dinesha
            else if(wr_xfr_count[1:0] == 2'b10)
212 3 dinesha
            begin
213 16 dinesha
                app_wr_en_n_int = app_wr_en_n[2];
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                app_wr_data_int = app_wr_data[23:16];
215 3 dinesha
            end
216 44 dinesha
            else if(wr_xfr_count[1:0] == 2'b01)
217 3 dinesha
            begin
218 16 dinesha
                app_wr_en_n_int = app_wr_en_n[1];
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                app_wr_data_int = app_wr_data[15:8];
220 3 dinesha
            end
221 16 dinesha
            else begin
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                app_wr_en_n_int = app_wr_en_n[0];
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                app_wr_data_int = app_wr_data[7:0];
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            end
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            app_rd_data = {app_rd_data_int,saved_rd_data[23:0]};
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          end
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     end
229 3 dinesha
 
230
 
231
 
232
always @(posedge clk)
233
  begin
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    if(!reset_n)
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      begin
236 16 dinesha
        rd_xfr_count    <= 8'b0;
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        wr_xfr_count    <= 8'b0;
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        saved_rd_data   <= 24'h0;
239 3 dinesha
      end
240 16 dinesha
    else begin
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        // During Write Phase
243 44 dinesha
        if(x2a_wrlast) begin
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           wr_xfr_count    <= 0;
245 3 dinesha
        end
246 44 dinesha
        else if(app_wr_next_int) begin
247
           wr_xfr_count <= wr_xfr_count + 1'b1;
248 3 dinesha
        end
249 16 dinesha
 
250
        // During Read Phase
251 44 dinesha
        if(x2a_rdlast) begin
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           rd_xfr_count    <= 0;
253 16 dinesha
        end
254 44 dinesha
        else if(app_rd_valid_int) begin
255
           rd_xfr_count   <= rd_xfr_count + 1'b1;
256
        end
257
 
258
        // Save Previous Data
259
        if(app_rd_valid_int) begin
260 16 dinesha
           if(sdr_width == 2'b01) // 16 Bit SDR Mode
261
              saved_rd_data[15:0]  <= app_rd_data_int;
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            else begin// 8 bit SDR Mode - 
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               if(rd_xfr_count[1:0] == 2'b00)      saved_rd_data[7:0]   <= app_rd_data_int[7:0];
264 44 dinesha
               else if(rd_xfr_count[1:0] == 2'b01) saved_rd_data[15:8]  <= app_rd_data_int[7:0];
265 16 dinesha
               else if(rd_xfr_count[1:0] == 2'b10) saved_rd_data[23:16] <= app_rd_data_int[7:0];
266
            end
267
        end
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    end
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end
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271 3 dinesha
endmodule // sdr_bs_convert

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