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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Blame information for rev 44

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1 3 dinesha
/*********************************************************************
2
 
3
  SDRAM Controller Core File
4
 
5
  This file is part of the sdram controller project
6
  http://www.opencores.org/cores/sdr_ctrl/
7
 
8
  Description: SDRAM Controller Core Module
9
    2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank.
10
    This block integrate following sub modules
11
 
12
    sdrc_bs_convert
13 33 dinesha
        convert the system side 32 bit into equvailent 8/16/32 SDR format
14 3 dinesha
    sdrc_req_gen
15
        This module takes requests from the app, chops them to burst booundaries
16
        if wrap=0, decodes the bank and passe the request to bank_ctl
17
   sdrc_xfr_ctl
18
      This module takes requests from sdr_bank_ctl, runs the transfer and
19
      controls data flow to/from the app. At the end of the transfer it issues a
20
      burst terminate if not at the end of a burst and another command to this
21
      bank is not available.
22
 
23
   sdrc_bank_ctl
24
      This module takes requests from sdr_req_gen, checks for page hit/miss and
25
      issues precharge/activate commands and then passes the request to
26
      sdr_xfr_ctl.
27
 
28
 
29
  Assumption: SDRAM Pads should be placed near to this module. else
30
  user should add a FF near the pads
31
 
32
  To Do:
33
    nothing
34
 
35
  Author(s):
36
      - Dinesh Annayya, dinesha@opencores.org
37 44 dinesha
  Version  : 0.0 - 8th Jan 2012
38 16 dinesha
                Initial version with 16/32 Bit SDRAM Support
39 44 dinesha
           : 0.1 - 24th Jan 2012
40 16 dinesha
                 8 Bit SDRAM Support is added
41 44 dinesha
             0.2 - 2nd Feb 2012
42
                 Improved the command pipe structure to accept up-to 4 command of different bank.
43 3 dinesha
 
44
 
45
 Copyright (C) 2000 Authors and OPENCORES.ORG
46
 
47
 This source file may be used and distributed without
48
 restriction provided that this copyright statement is not
49
 removed from the file and that any derivative work contains
50
 the original copyright notice and the associated disclaimer.
51
 
52
 This source file is free software; you can redistribute it
53
 and/or modify it under the terms of the GNU Lesser General
54
 Public License as published by the Free Software Foundation;
55
 either version 2.1 of the License, or (at your option) any
56
later version.
57
 
58
 This source is distributed in the hope that it will be
59
 useful, but WITHOUT ANY WARRANTY; without even the implied
60
 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
61
 PURPOSE.  See the GNU Lesser General Public License for more
62
 details.
63
 
64
 You should have received a copy of the GNU Lesser General
65
 Public License along with this source; if not, download it
66
 from http://www.opencores.org/lgpl.shtml
67
 
68
*******************************************************************/
69
 
70
 
71 37 dinesha
`include "sdrc_define.v"
72 3 dinesha
module sdrc_core
73
           (
74 4 dinesha
                clk,
75
                pad_clk,
76 3 dinesha
                reset_n,
77
                sdr_width,
78 13 dinesha
                cfg_colbits,
79 3 dinesha
 
80
                /* Request from app */
81
                app_req,                // Transfer Request
82
                app_req_addr,           // SDRAM Address
83
                app_req_addr_mask,      // Address mask for queue wrap
84
                app_req_len,            // Burst Length (in 16 bit words)
85
                app_req_wrap,           // Wrap mode request (xfr_len = 4)
86
                app_req_wr_n,           // 0 => Write request, 1 => read req
87
                app_req_ack,            // Request has been accepted
88
                sdr_core_busy_n,                // OK to arbitrate next request
89
                cfg_req_depth,          //how many req. buffer should hold
90
 
91
                app_wr_data,
92
                app_wr_en_n,
93
                app_rd_data,
94
                app_rd_valid,
95 31 dinesha
                app_last_rd,
96 3 dinesha
                app_wr_next_req,
97
                sdr_init_done,
98
                app_req_dma_last,
99
 
100
                /* Interface to SDRAMs */
101
                sdr_cs_n,
102
                sdr_cke,
103
                sdr_ras_n,
104
                sdr_cas_n,
105
                sdr_we_n,
106
                sdr_dqm,
107
                sdr_ba,
108
                sdr_addr,
109
                pad_sdr_din,
110
                sdr_dout,
111
                sdr_den_n,
112
 
113
                /* Parameters */
114
                cfg_sdr_en,
115
                cfg_sdr_mode_reg,
116
                cfg_sdr_tras_d,
117
                cfg_sdr_trp_d,
118
                cfg_sdr_trcd_d,
119
                cfg_sdr_cas,
120
                cfg_sdr_trcar_d,
121
                cfg_sdr_twr_d,
122
                cfg_sdr_rfsh,
123
                cfg_sdr_rfmax);
124
 
125
parameter  APP_AW   = 30;  // Application Address Width
126
parameter  APP_DW   = 32;  // Application Data Width 
127
parameter  APP_BW   = 4;   // Application Byte Width
128
parameter  APP_RW   = 9;   // Application Request Width
129
 
130
parameter  SDR_DW   = 16;  // SDR Data Width 
131
parameter  SDR_BW   = 2;   // SDR Byte Width
132
 
133
 
134
//-----------------------------------------------
135
// Global Variable
136
// ----------------------------------------------
137 4 dinesha
input                   clk                 ; // SDRAM Clock 
138
input                   pad_clk             ; // SDRAM Clock from Pad, used for registering Read Data
139 3 dinesha
input                   reset_n             ; // Reset Signal
140 16 dinesha
input [1:0]             sdr_width           ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
141 13 dinesha
input [1:0]             cfg_colbits         ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
142 3 dinesha
 
143 13 dinesha
 
144 3 dinesha
//------------------------------------------------
145
// Request from app
146
//------------------------------------------------
147
input                   app_req             ; // Application Request
148
input [APP_AW-1:0]       app_req_addr        ; // Address 
149
input [APP_AW-2:0]      app_req_addr_mask   ; // Address Mask
150
input                   app_req_wr_n        ; // 0 - Write, 1 - Read
151
input                   app_req_wrap        ; // Address Wrap
152
output                  app_req_ack         ; // Application Request Ack
153
output                  sdr_core_busy_n     ; // 0 - busy, 1 - free
154
 
155
input [APP_DW-1:0]       app_wr_data         ; // Write Data
156
output                  app_wr_next_req     ; // Next Write Data Request
157
input [APP_BW-1:0]       app_wr_en_n         ; // Byte wise Write Enable
158
output [APP_DW-1:0]      app_rd_data         ; // Read Data
159
output                  app_rd_valid        ; // Read Valid
160 31 dinesha
output                  app_last_rd         ; // Last Read Transfer of a given Burst
161 3 dinesha
 
162
//------------------------------------------------
163
// Interface to SDRAMs
164
//------------------------------------------------
165
output                  sdr_cke             ; // SDRAM CKE
166
output                  sdr_cs_n            ; // SDRAM Chip Select
167
output                  sdr_ras_n           ; // SDRAM ras
168
output                  sdr_cas_n           ; // SDRAM cas
169
output                  sdr_we_n            ; // SDRAM write enable
170
output [SDR_BW-1:0]      sdr_dqm             ; // SDRAM Data Mask
171
output [1:0]             sdr_ba              ; // SDRAM Bank Enable
172
output [11:0]            sdr_addr            ; // SDRAM Address
173
input [SDR_DW-1:0]       pad_sdr_din         ; // SDRA Data Input
174
output [SDR_DW-1:0]      sdr_dout            ; // SDRAM Data Output
175
output [SDR_BW-1:0]      sdr_den_n           ; // SDRAM Data Output enable
176
 
177
//------------------------------------------------
178
// Configuration Parameter
179
//------------------------------------------------
180 13 dinesha
output                  sdr_init_done       ; // Indicate SDRAM Initialisation Done
181
input [3:0]              cfg_sdr_tras_d      ; // Active to precharge delay
182
input [3:0]             cfg_sdr_trp_d       ; // Precharge to active delay
183
input [3:0]             cfg_sdr_trcd_d      ; // Active to R/W delay
184
input                   cfg_sdr_en          ; // Enable SDRAM controller
185
input [1:0]              cfg_req_depth       ; // Maximum Request accepted by SDRAM controller
186
input [APP_RW-1:0]       app_req_len         ; // Application Burst Request length in 32 bit 
187 3 dinesha
input [11:0]             cfg_sdr_mode_reg    ;
188 13 dinesha
input [2:0]              cfg_sdr_cas         ; // SDRAM CAS Latency
189
input [3:0]              cfg_sdr_trcar_d     ; // Auto-refresh period
190
input [3:0]             cfg_sdr_twr_d       ; // Write recovery delay
191 3 dinesha
input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
192
input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
193
input                   app_req_dma_last;    // this signal should close the bank
194
 
195
/****************************************************************************/
196
// Internal Nets
197
 
198
// SDR_REQ_GEN
199
wire                    r2x_idle, app_req_ack,app_req_ack_int;
200
wire                    app_req_dma_last_int;
201
wire                    r2b_req, r2b_start, r2b_last, r2b_write;
202
wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
203
wire [1:0]               r2b_ba;
204
wire [11:0]              r2b_raddr;
205
wire [11:0]              r2b_caddr;
206
wire [APP_RW-1:0]        r2b_len;
207
 
208
// SDR BANK CTL
209
wire                    b2r_ack, b2x_idle;
210
wire                    b2x_req, b2x_start, b2x_last, b2x_tras_ok;
211
wire [`SDR_REQ_ID_W-1:0]b2x_id;
212
wire [1:0]               b2x_ba;
213
wire                    b2x_ba_last;
214
wire [11:0]              b2x_addr;
215
wire [APP_RW-1:0]        b2x_len;
216
wire [1:0]               b2x_cmd;
217
 
218
// SDR_XFR_CTL
219
wire                    x2b_ack;
220
wire [3:0]               x2b_pre_ok;
221
wire                    x2b_refresh, x2b_act_ok, x2b_rdok, x2b_wrok;
222 31 dinesha
wire                    xfr_rdstart, app_last_rd;
223 3 dinesha
wire                    xfr_wrstart, xfr_wrlast;
224
wire [`SDR_REQ_ID_W-1:0]xfr_id;
225
wire [APP_DW-1:0]        app_rd_data;
226
wire                    app_wr_next_req, app_rd_valid;
227
wire                    sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n;
228
wire [SDR_BW-1:0]        sdr_dqm;
229
wire [1:0]               sdr_ba;
230
wire [11:0]              sdr_addr;
231
wire [SDR_DW-1:0]        sdr_dout;
232
wire [SDR_DW-1:0]        sdr_dout_int;
233
wire [SDR_BW-1:0]        sdr_den_n;
234
wire [SDR_BW-1:0]        sdr_den_n_int;
235
 
236
wire [1:0]               xfr_bank_sel;
237
 
238
wire [APP_AW:0]          app_req_addr_int;
239
wire [APP_AW-1:0]        app_req_addr;
240
wire [APP_RW-1:0]        app_req_len_int;
241
wire [APP_RW-1:0]        app_req_len;
242
 
243
wire [APP_DW-1:0]        app_wr_data;
244
wire [SDR_DW-1:0]        add_wr_data_int;
245
wire [APP_BW-1:0]        app_wr_en_n;
246
wire [SDR_BW-1:0]        app_wr_en_n_int;
247
 
248
//wire [31:0] app_rd_data;
249
wire [SDR_DW-1:0]        app_rd_data_int;
250
 
251
//
252
wire                     app_req_int;
253
wire                     r2b_wrap;
254
wire                     b2r_arb_ok;
255
wire                     b2x_wrap;
256
wire                     app_wr_next_int;
257
wire                     app_rd_valid_int;
258 44 dinesha
wire                     x2a_rdlast;
259 3 dinesha
 
260 44 dinesha
 
261 3 dinesha
// synopsys translate_off 
262
   wire [3:0]           sdr_cmd;
263
   assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n};
264
// synopsys translate_on 
265
 
266 16 dinesha
   assign sdr_den_n = sdr_den_n_int ;
267
   assign sdr_dout  = sdr_dout_int ;
268 3 dinesha
 
269 44 dinesha
assign  app_last_rd = x2a_rdlast;
270 3 dinesha
 
271 23 dinesha
// To meet the timing at read path, read data is registered w.r.t pad_sdram_clock and register back to sdram_clk
272
// assumption, pad_sdram_clk is synhronous and delayed clock of sdram_clk.
273
// register w.r.t pad sdram clk
274
reg [SDR_DW-1:0] pad_sdr_din1;
275
reg [SDR_DW-1:0] pad_sdr_din2;
276
always@(posedge pad_clk) begin
277
   pad_sdr_din1 <= pad_sdr_din;
278
end
279
 
280
always@(posedge clk) begin
281
   pad_sdr_din2 <= pad_sdr_din1;
282
end
283
 
284 3 dinesha
   /****************************************************************************/
285
   // Instantiate sdr_req_gen
286
   // This module takes requests from the app, chops them to burst booundaries
287
   // if wrap=0, decodes the bank and passe the request to bank_ctl
288
 
289 9 dinesha
sdrc_req_gen #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_req_gen (
290 4 dinesha
          .clk                (clk          ),
291 3 dinesha
          .reset_n            (reset_n            ),
292 13 dinesha
          .cfg_colbits        (cfg_colbits        ),
293 3 dinesha
 
294
        /* Request from app */
295
          .r2x_idle           (r2x_idle           ),
296
          .req                (app_req_int        ),
297
          .req_id             (4'b0               ),
298
          .req_addr           (app_req_addr_int   ),
299
          .req_addr_mask      (app_req_addr_mask  ),
300
          .req_len            (app_req_len_int    ),
301
          .req_wrap           (app_req_wrap       ),
302
          .req_wr_n           (app_req_wr_n       ),
303
          .req_ack            (app_req_ack_int      ),
304
          .sdr_core_busy_n    (sdr_core_busy_n    ),
305
 
306
       /* Req to bank_ctl */
307
          .r2b_req            (r2b_req            ),
308
          .r2b_req_id         (r2b_req_id         ),
309
          .r2b_start          (r2b_start          ),
310
          .r2b_last           (r2b_last           ),
311
          .r2b_wrap           (r2b_wrap           ),
312
          .r2b_ba             (r2b_ba             ),
313
          .r2b_raddr          (r2b_raddr          ),
314
          .r2b_caddr          (r2b_caddr          ),
315
          .r2b_len            (r2b_len            ),
316
          .r2b_write          (r2b_write          ),
317
          .b2r_ack            (b2r_ack            ),
318
          .b2r_arb_ok         (b2r_arb_ok         ),
319
          .sdr_width          (sdr_width          ),
320
          .sdr_init_done      (sdr_init_done      )
321
     );
322
 
323
   /****************************************************************************/
324
   // Instantiate sdr_bank_ctl
325
   // This module takes requests from sdr_req_gen, checks for page hit/miss and
326
   // issues precharge/activate commands and then passes the request to
327
   // sdr_xfr_ctl. 
328
 
329 9 dinesha
sdrc_bank_ctl #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_bank_ctl (
330 4 dinesha
          .clk                (clk          ),
331 3 dinesha
          .reset_n            (reset_n            ),
332
          .a2b_req_depth      (cfg_req_depth      ),
333
 
334
      /* Req from req_gen */
335
          .r2b_req            (r2b_req            ),
336
          .r2b_req_id         (r2b_req_id         ),
337
          .r2b_start          (r2b_start          ),
338
          .r2b_last           (r2b_last           ),
339
          .r2b_wrap           (r2b_wrap           ),
340
          .r2b_ba             (r2b_ba             ),
341
          .r2b_raddr          (r2b_raddr          ),
342
          .r2b_caddr          (r2b_caddr          ),
343
          .r2b_len            (r2b_len            ),
344
          .r2b_write          (r2b_write          ),
345
          .b2r_arb_ok         (b2r_arb_ok         ),
346
          .b2r_ack            (b2r_ack            ),
347
 
348
      /* Transfer request to xfr_ctl */
349
          .b2x_idle           (b2x_idle           ),
350
          .b2x_req            (b2x_req            ),
351
          .b2x_start          (b2x_start          ),
352
          .b2x_last           (b2x_last           ),
353
          .b2x_wrap           (b2x_wrap           ),
354
          .b2x_id             (b2x_id             ),
355
          .b2x_ba             (b2x_ba             ),
356
          .b2x_addr           (b2x_addr           ),
357
          .b2x_len            (b2x_len            ),
358
          .b2x_cmd            (b2x_cmd            ),
359
          .x2b_ack            (x2b_ack            ),
360
 
361
      /* Status from xfr_ctl */
362
          .b2x_tras_ok        (b2x_tras_ok        ),
363
          .x2b_refresh        (x2b_refresh        ),
364
          .x2b_pre_ok         (x2b_pre_ok         ),
365
          .x2b_act_ok         (x2b_act_ok         ),
366
          .x2b_rdok           (x2b_rdok           ),
367
          .x2b_wrok           (x2b_wrok           ),
368
 
369
      /* for generate cuurent xfr address msb */
370
          .sdr_req_norm_dma_last(app_req_dma_last_int),
371
          .xfr_bank_sel       (xfr_bank_sel       ),
372
 
373
       /* SDRAM Timing */
374
          .tras_delay         (cfg_sdr_tras_d     ),
375
          .trp_delay          (cfg_sdr_trp_d      ),
376
          .trcd_delay         (cfg_sdr_trcd_d     )
377
      );
378
 
379
   /****************************************************************************/
380
   // Instantiate sdr_xfr_ctl
381
   // This module takes requests from sdr_bank_ctl, runs the transfer and
382
   // controls data flow to/from the app. At the end of the transfer it issues a
383
   // burst terminate if not at the end of a burst and another command to this
384
   // bank is not available.
385
 
386 9 dinesha
sdrc_xfr_ctl #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_xfr_ctl (
387 4 dinesha
          .clk                (clk          ),
388 3 dinesha
          .reset_n            (reset_n            ),
389
 
390
      /* Transfer request from bank_ctl */
391
          .r2x_idle           (r2x_idle           ),
392
          .b2x_idle           (b2x_idle           ),
393
          .b2x_req            (b2x_req            ),
394
          .b2x_start          (b2x_start          ),
395
          .b2x_last           (b2x_last           ),
396
          .b2x_wrap           (b2x_wrap           ),
397
          .b2x_id             (b2x_id             ),
398
          .b2x_ba             (b2x_ba             ),
399
          .b2x_addr           (b2x_addr           ),
400
          .b2x_len            (b2x_len            ),
401
          .b2x_cmd            (b2x_cmd            ),
402
          .x2b_ack            (x2b_ack            ),
403
 
404
       /* Status to bank_ctl, req_gen */
405
          .b2x_tras_ok        (b2x_tras_ok        ),
406
          .x2b_refresh        (x2b_refresh        ),
407
          .x2b_pre_ok         (x2b_pre_ok         ),
408
          .x2b_act_ok         (x2b_act_ok         ),
409
          .x2b_rdok           (x2b_rdok           ),
410
          .x2b_wrok           (x2b_wrok           ),
411
 
412
       /* SDRAM I/O */
413
          .sdr_cs_n           (sdr_cs_n           ),
414
          .sdr_cke            (sdr_cke            ),
415
          .sdr_ras_n          (sdr_ras_n          ),
416
          .sdr_cas_n          (sdr_cas_n          ),
417
          .sdr_we_n           (sdr_we_n           ),
418
          .sdr_dqm            (sdr_dqm            ),
419
          .sdr_ba             (sdr_ba             ),
420
          .sdr_addr           (sdr_addr           ),
421 23 dinesha
          .sdr_din            (pad_sdr_din2       ),
422 3 dinesha
          .sdr_dout           (sdr_dout_int       ),
423
          .sdr_den_n          (sdr_den_n_int      ),
424
      /* Data Flow to the app */
425
          .x2a_rdstart        (xfr_rdstart        ),
426
          .x2a_wrstart        (xfr_wrstart        ),
427
          .x2a_id             (xfr_id             ),
428 44 dinesha
          .x2a_rdlast         (x2a_rdlast         ),
429 3 dinesha
          .x2a_wrlast         (xfr_wrlast         ),
430
          .app_wrdt           (add_wr_data_int    ),
431 4 dinesha
          .app_wren_n         (app_wr_en_n_int    ),
432 3 dinesha
          .x2a_wrnext         (app_wr_next_int    ),
433
          .x2a_rddt           (app_rd_data_int    ),
434
          .x2a_rdok           (app_rd_valid_int   ),
435
          .sdr_init_done      (sdr_init_done      ),
436
 
437
      /* SDRAM Parameters */
438
          .sdram_enable       (cfg_sdr_en         ),
439
          .sdram_mode_reg     (cfg_sdr_mode_reg   ),
440
 
441
      /* current xfr bank */
442
          .xfr_bank_sel       (xfr_bank_sel       ),
443
 
444
      /* SDRAM Timing */
445
          .cas_latency        (cfg_sdr_cas        ),
446
          .trp_delay          (cfg_sdr_trp_d      ),
447
          .trcar_delay        (cfg_sdr_trcar_d    ),
448
          .twr_delay          (cfg_sdr_twr_d      ),
449
          .rfsh_time          (cfg_sdr_rfsh       ),
450
          .rfsh_rmax          (cfg_sdr_rfmax      )
451
    );
452
 
453 33 dinesha
   /****************************************************************************/
454
   // Instantiate sdr_bs_convert
455
   //    This model handle the bus with transaltion from application layer to
456
   //       8/16/32 SDRAM Memory format
457
   //     During Write Phase, this block split the data as per SDRAM Width
458
   //     During Read Phase, This block does the re-packing based on SDRAM
459
   //     Width
460
   //---------------------------------------------------------------------------
461 9 dinesha
sdrc_bs_convert #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_bs_convert (
462 4 dinesha
          .clk                (clk          ),
463 3 dinesha
          .reset_n            (reset_n            ),
464
          .sdr_width          (sdr_width          ),
465
 
466 44 dinesha
   /* Control Signal from xfr ctrl */
467
          .x2a_rdstart        (xfr_rdstart        ),
468
          .x2a_wrstart        (xfr_wrstart        ),
469
          .x2a_rdlast         (x2a_rdlast         ),
470
          .x2a_wrlast         (xfr_wrlast         ),
471
          .app_rd_data_int    (app_rd_data_int    ),
472
          .app_rd_valid_int   (app_rd_valid_int   ),
473
          .app_wr_data_int    (add_wr_data_int    ),
474
          .app_wr_en_n_int    (app_wr_en_n_int    ),
475
          .app_wr_next_int    (app_wr_next_int    ),
476
 
477
   /* Control Signal from request ctrl */
478
          .app_req_addr_int   (app_req_addr_int   ),
479
          .app_req_len_int    (app_req_len_int    ),
480
          .app_req_ack_int    (app_req_ack_int    ),
481
          .app_sdr_req_int    (app_req_int        ),
482
 
483
   /* Control Signal from Bank Ctrl  */
484
          .app_req_dma_last_int(app_req_dma_last_int),
485
 
486
   /*  Control Signal from/to to application i/f  */
487 3 dinesha
          .app_req_addr       (app_req_addr       ),
488
          .app_req_len        (app_req_len        ),
489
          .app_sdr_req        (app_req            ),
490
          .app_req_dma_last   (app_req_dma_last   ),
491
          .app_req_wr_n       (app_req_wr_n       ),
492
          .app_req_ack        (app_req_ack        ),
493
          .app_wr_data        (app_wr_data        ),
494
          .app_wr_en_n        (app_wr_en_n        ),
495
          .app_wr_next        (app_wr_next_req    ),
496
          .app_rd_data        (app_rd_data        ),
497
          .app_rd_valid       (app_rd_valid       )
498 44 dinesha
 
499 3 dinesha
       );
500
 
501
endmodule // sdrc_core

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