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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Blame information for rev 51

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1 3 dinesha
/*********************************************************************
2
 
3
  SDRAM Controller Core File
4
 
5
  This file is part of the sdram controller project
6
  http://www.opencores.org/cores/sdr_ctrl/
7
 
8
  Description: SDRAM Controller Core Module
9
    2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank.
10
    This block integrate following sub modules
11
 
12
    sdrc_bs_convert
13 33 dinesha
        convert the system side 32 bit into equvailent 8/16/32 SDR format
14 3 dinesha
    sdrc_req_gen
15
        This module takes requests from the app, chops them to burst booundaries
16
        if wrap=0, decodes the bank and passe the request to bank_ctl
17
   sdrc_xfr_ctl
18
      This module takes requests from sdr_bank_ctl, runs the transfer and
19
      controls data flow to/from the app. At the end of the transfer it issues a
20
      burst terminate if not at the end of a burst and another command to this
21
      bank is not available.
22
 
23
   sdrc_bank_ctl
24
      This module takes requests from sdr_req_gen, checks for page hit/miss and
25
      issues precharge/activate commands and then passes the request to
26
      sdr_xfr_ctl.
27
 
28
 
29
  Assumption: SDRAM Pads should be placed near to this module. else
30
  user should add a FF near the pads
31
 
32
  To Do:
33
    nothing
34
 
35
  Author(s):
36
      - Dinesh Annayya, dinesha@opencores.org
37 44 dinesha
  Version  : 0.0 - 8th Jan 2012
38 16 dinesha
                Initial version with 16/32 Bit SDRAM Support
39 44 dinesha
           : 0.1 - 24th Jan 2012
40 16 dinesha
                 8 Bit SDRAM Support is added
41 44 dinesha
             0.2 - 2nd Feb 2012
42 50 dinesha
                   Improved the command pipe structure to accept up-to
43
                   4 command of different bank.
44
             0.3 - 7th Feb 2012
45
                   Bug fix for parameter defination for request length has changed from 9 to 12
46 3 dinesha
 
47
 
48
 Copyright (C) 2000 Authors and OPENCORES.ORG
49
 
50
 This source file may be used and distributed without
51
 restriction provided that this copyright statement is not
52
 removed from the file and that any derivative work contains
53
 the original copyright notice and the associated disclaimer.
54
 
55
 This source file is free software; you can redistribute it
56
 and/or modify it under the terms of the GNU Lesser General
57
 Public License as published by the Free Software Foundation;
58
 either version 2.1 of the License, or (at your option) any
59
later version.
60
 
61
 This source is distributed in the hope that it will be
62
 useful, but WITHOUT ANY WARRANTY; without even the implied
63
 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
64
 PURPOSE.  See the GNU Lesser General Public License for more
65
 details.
66
 
67
 You should have received a copy of the GNU Lesser General
68
 Public License along with this source; if not, download it
69
 from http://www.opencores.org/lgpl.shtml
70
 
71
*******************************************************************/
72
 
73
 
74 37 dinesha
`include "sdrc_define.v"
75 3 dinesha
module sdrc_core
76
           (
77 4 dinesha
                clk,
78
                pad_clk,
79 3 dinesha
                reset_n,
80
                sdr_width,
81 13 dinesha
                cfg_colbits,
82 3 dinesha
 
83
                /* Request from app */
84
                app_req,                // Transfer Request
85
                app_req_addr,           // SDRAM Address
86
                app_req_len,            // Burst Length (in 16 bit words)
87
                app_req_wrap,           // Wrap mode request (xfr_len = 4)
88
                app_req_wr_n,           // 0 => Write request, 1 => read req
89
                app_req_ack,            // Request has been accepted
90
                cfg_req_depth,          //how many req. buffer should hold
91
 
92
                app_wr_data,
93
                app_wr_en_n,
94 45 dinesha
                app_last_wr,
95
 
96 3 dinesha
                app_rd_data,
97
                app_rd_valid,
98 31 dinesha
                app_last_rd,
99 3 dinesha
                app_wr_next_req,
100
                sdr_init_done,
101
                app_req_dma_last,
102
 
103
                /* Interface to SDRAMs */
104
                sdr_cs_n,
105
                sdr_cke,
106
                sdr_ras_n,
107
                sdr_cas_n,
108
                sdr_we_n,
109
                sdr_dqm,
110
                sdr_ba,
111
                sdr_addr,
112
                pad_sdr_din,
113
                sdr_dout,
114
                sdr_den_n,
115
 
116
                /* Parameters */
117
                cfg_sdr_en,
118
                cfg_sdr_mode_reg,
119
                cfg_sdr_tras_d,
120
                cfg_sdr_trp_d,
121
                cfg_sdr_trcd_d,
122
                cfg_sdr_cas,
123
                cfg_sdr_trcar_d,
124
                cfg_sdr_twr_d,
125
                cfg_sdr_rfsh,
126
                cfg_sdr_rfmax);
127
 
128
parameter  APP_AW   = 30;  // Application Address Width
129
parameter  APP_DW   = 32;  // Application Data Width 
130
parameter  APP_BW   = 4;   // Application Byte Width
131
parameter  APP_RW   = 9;   // Application Request Width
132
 
133
parameter  SDR_DW   = 16;  // SDR Data Width 
134
parameter  SDR_BW   = 2;   // SDR Byte Width
135
 
136 51 dinesha
// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
137
parameter  REQ_BW   = (`TARGET_DESIGN == `FPGA) ? 8 : 12;   //  Request Width
138 3 dinesha
 
139
//-----------------------------------------------
140
// Global Variable
141
// ----------------------------------------------
142 4 dinesha
input                   clk                 ; // SDRAM Clock 
143
input                   pad_clk             ; // SDRAM Clock from Pad, used for registering Read Data
144 3 dinesha
input                   reset_n             ; // Reset Signal
145 16 dinesha
input [1:0]             sdr_width           ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
146 13 dinesha
input [1:0]             cfg_colbits         ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
147 3 dinesha
 
148 13 dinesha
 
149 3 dinesha
//------------------------------------------------
150
// Request from app
151
//------------------------------------------------
152
input                   app_req             ; // Application Request
153
input [APP_AW-1:0]       app_req_addr        ; // Address 
154
input                   app_req_wr_n        ; // 0 - Write, 1 - Read
155
input                   app_req_wrap        ; // Address Wrap
156
output                  app_req_ack         ; // Application Request Ack
157
 
158
input [APP_DW-1:0]       app_wr_data         ; // Write Data
159
output                  app_wr_next_req     ; // Next Write Data Request
160
input [APP_BW-1:0]       app_wr_en_n         ; // Byte wise Write Enable
161 45 dinesha
output                  app_last_wr         ; // Last Write trannsfer of a given Burst
162 3 dinesha
output [APP_DW-1:0]      app_rd_data         ; // Read Data
163
output                  app_rd_valid        ; // Read Valid
164 31 dinesha
output                  app_last_rd         ; // Last Read Transfer of a given Burst
165 3 dinesha
 
166
//------------------------------------------------
167
// Interface to SDRAMs
168
//------------------------------------------------
169
output                  sdr_cke             ; // SDRAM CKE
170
output                  sdr_cs_n            ; // SDRAM Chip Select
171
output                  sdr_ras_n           ; // SDRAM ras
172
output                  sdr_cas_n           ; // SDRAM cas
173
output                  sdr_we_n            ; // SDRAM write enable
174
output [SDR_BW-1:0]      sdr_dqm             ; // SDRAM Data Mask
175
output [1:0]             sdr_ba              ; // SDRAM Bank Enable
176
output [11:0]            sdr_addr            ; // SDRAM Address
177
input [SDR_DW-1:0]       pad_sdr_din         ; // SDRA Data Input
178
output [SDR_DW-1:0]      sdr_dout            ; // SDRAM Data Output
179
output [SDR_BW-1:0]      sdr_den_n           ; // SDRAM Data Output enable
180
 
181
//------------------------------------------------
182
// Configuration Parameter
183
//------------------------------------------------
184 13 dinesha
output                  sdr_init_done       ; // Indicate SDRAM Initialisation Done
185
input [3:0]              cfg_sdr_tras_d      ; // Active to precharge delay
186
input [3:0]             cfg_sdr_trp_d       ; // Precharge to active delay
187
input [3:0]             cfg_sdr_trcd_d      ; // Active to R/W delay
188
input                   cfg_sdr_en          ; // Enable SDRAM controller
189
input [1:0]              cfg_req_depth       ; // Maximum Request accepted by SDRAM controller
190
input [APP_RW-1:0]       app_req_len         ; // Application Burst Request length in 32 bit 
191 3 dinesha
input [11:0]             cfg_sdr_mode_reg    ;
192 13 dinesha
input [2:0]              cfg_sdr_cas         ; // SDRAM CAS Latency
193
input [3:0]              cfg_sdr_trcar_d     ; // Auto-refresh period
194
input [3:0]             cfg_sdr_twr_d       ; // Write recovery delay
195 3 dinesha
input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
196
input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
197
input                   app_req_dma_last;    // this signal should close the bank
198
 
199
/****************************************************************************/
200
// Internal Nets
201
 
202
// SDR_REQ_GEN
203
wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
204
wire [1:0]               r2b_ba;
205
wire [11:0]              r2b_raddr;
206
wire [11:0]              r2b_caddr;
207 50 dinesha
wire [REQ_BW-1:0]        r2b_len;
208 3 dinesha
 
209
// SDR BANK CTL
210
wire [`SDR_REQ_ID_W-1:0]b2x_id;
211
wire [1:0]               b2x_ba;
212
wire [11:0]              b2x_addr;
213 50 dinesha
wire [REQ_BW-1:0]        b2x_len;
214 3 dinesha
wire [1:0]               b2x_cmd;
215
 
216
// SDR_XFR_CTL
217
wire [3:0]               x2b_pre_ok;
218
wire [`SDR_REQ_ID_W-1:0]xfr_id;
219
wire [APP_DW-1:0]        app_rd_data;
220
wire                    sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n;
221
wire [SDR_BW-1:0]        sdr_dqm;
222
wire [1:0]               sdr_ba;
223
wire [11:0]              sdr_addr;
224
wire [SDR_DW-1:0]        sdr_dout;
225
wire [SDR_DW-1:0]        sdr_dout_int;
226
wire [SDR_BW-1:0]        sdr_den_n;
227
wire [SDR_BW-1:0]        sdr_den_n_int;
228
 
229
wire [1:0]               xfr_bank_sel;
230
 
231
wire [APP_AW-1:0]        app_req_addr;
232
wire [APP_RW-1:0]        app_req_len;
233
 
234
wire [APP_DW-1:0]        app_wr_data;
235 45 dinesha
wire [SDR_DW-1:0]        a2x_wrdt       ;
236 3 dinesha
wire [APP_BW-1:0]        app_wr_en_n;
237 45 dinesha
wire [SDR_BW-1:0]        a2x_wren_n;
238 3 dinesha
 
239
//wire [31:0] app_rd_data;
240 45 dinesha
wire [SDR_DW-1:0]        x2a_rddt;
241 3 dinesha
 
242
 
243
// synopsys translate_off 
244
   wire [3:0]           sdr_cmd;
245
   assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n};
246
// synopsys translate_on 
247
 
248 45 dinesha
assign sdr_den_n = sdr_den_n_int ;
249
assign sdr_dout  = sdr_dout_int ;
250 3 dinesha
 
251
 
252 23 dinesha
// To meet the timing at read path, read data is registered w.r.t pad_sdram_clock and register back to sdram_clk
253
// assumption, pad_sdram_clk is synhronous and delayed clock of sdram_clk.
254
// register w.r.t pad sdram clk
255
reg [SDR_DW-1:0] pad_sdr_din1;
256
reg [SDR_DW-1:0] pad_sdr_din2;
257
always@(posedge pad_clk) begin
258
   pad_sdr_din1 <= pad_sdr_din;
259
end
260
 
261
always@(posedge clk) begin
262
   pad_sdr_din2 <= pad_sdr_din1;
263
end
264
 
265 45 dinesha
 
266 3 dinesha
   /****************************************************************************/
267
   // Instantiate sdr_req_gen
268
   // This module takes requests from the app, chops them to burst booundaries
269
   // if wrap=0, decodes the bank and passe the request to bank_ctl
270
 
271 9 dinesha
sdrc_req_gen #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_req_gen (
272 4 dinesha
          .clk                (clk          ),
273 3 dinesha
          .reset_n            (reset_n            ),
274 13 dinesha
          .cfg_colbits        (cfg_colbits        ),
275 47 dinesha
          .sdr_width          (sdr_width          ),
276 3 dinesha
 
277 47 dinesha
        /* Req to xfr_ctl */
278
          .r2x_idle           (r2x_idle           ),
279
 
280 3 dinesha
        /* Request from app */
281 45 dinesha
          .req                (app_req            ),
282 3 dinesha
          .req_id             (4'b0               ),
283 45 dinesha
          .req_addr           (app_req_addr       ),
284
          .req_len            (app_req_len        ),
285 3 dinesha
          .req_wrap           (app_req_wrap       ),
286
          .req_wr_n           (app_req_wr_n       ),
287 45 dinesha
          .req_ack            (app_req_ack        ),
288 3 dinesha
 
289
       /* Req to bank_ctl */
290
          .r2b_req            (r2b_req            ),
291
          .r2b_req_id         (r2b_req_id         ),
292
          .r2b_start          (r2b_start          ),
293
          .r2b_last           (r2b_last           ),
294
          .r2b_wrap           (r2b_wrap           ),
295
          .r2b_ba             (r2b_ba             ),
296
          .r2b_raddr          (r2b_raddr          ),
297
          .r2b_caddr          (r2b_caddr          ),
298
          .r2b_len            (r2b_len            ),
299
          .r2b_write          (r2b_write          ),
300
          .b2r_ack            (b2r_ack            ),
301 47 dinesha
          .b2r_arb_ok         (b2r_arb_ok         )
302 3 dinesha
     );
303
 
304
   /****************************************************************************/
305
   // Instantiate sdr_bank_ctl
306
   // This module takes requests from sdr_req_gen, checks for page hit/miss and
307
   // issues precharge/activate commands and then passes the request to
308
   // sdr_xfr_ctl. 
309
 
310 9 dinesha
sdrc_bank_ctl #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_bank_ctl (
311 4 dinesha
          .clk                (clk          ),
312 3 dinesha
          .reset_n            (reset_n            ),
313
          .a2b_req_depth      (cfg_req_depth      ),
314
 
315
      /* Req from req_gen */
316
          .r2b_req            (r2b_req            ),
317
          .r2b_req_id         (r2b_req_id         ),
318
          .r2b_start          (r2b_start          ),
319
          .r2b_last           (r2b_last           ),
320
          .r2b_wrap           (r2b_wrap           ),
321
          .r2b_ba             (r2b_ba             ),
322
          .r2b_raddr          (r2b_raddr          ),
323
          .r2b_caddr          (r2b_caddr          ),
324
          .r2b_len            (r2b_len            ),
325
          .r2b_write          (r2b_write          ),
326
          .b2r_arb_ok         (b2r_arb_ok         ),
327
          .b2r_ack            (b2r_ack            ),
328
 
329
      /* Transfer request to xfr_ctl */
330
          .b2x_idle           (b2x_idle           ),
331
          .b2x_req            (b2x_req            ),
332
          .b2x_start          (b2x_start          ),
333
          .b2x_last           (b2x_last           ),
334
          .b2x_wrap           (b2x_wrap           ),
335
          .b2x_id             (b2x_id             ),
336
          .b2x_ba             (b2x_ba             ),
337
          .b2x_addr           (b2x_addr           ),
338
          .b2x_len            (b2x_len            ),
339
          .b2x_cmd            (b2x_cmd            ),
340
          .x2b_ack            (x2b_ack            ),
341
 
342
      /* Status from xfr_ctl */
343
          .b2x_tras_ok        (b2x_tras_ok        ),
344
          .x2b_refresh        (x2b_refresh        ),
345
          .x2b_pre_ok         (x2b_pre_ok         ),
346
          .x2b_act_ok         (x2b_act_ok         ),
347
          .x2b_rdok           (x2b_rdok           ),
348
          .x2b_wrok           (x2b_wrok           ),
349
 
350
      /* for generate cuurent xfr address msb */
351 45 dinesha
          .sdr_req_norm_dma_last(app_req_dma_last),
352 3 dinesha
          .xfr_bank_sel       (xfr_bank_sel       ),
353
 
354
       /* SDRAM Timing */
355
          .tras_delay         (cfg_sdr_tras_d     ),
356
          .trp_delay          (cfg_sdr_trp_d      ),
357
          .trcd_delay         (cfg_sdr_trcd_d     )
358
      );
359
 
360
   /****************************************************************************/
361
   // Instantiate sdr_xfr_ctl
362
   // This module takes requests from sdr_bank_ctl, runs the transfer and
363
   // controls data flow to/from the app. At the end of the transfer it issues a
364
   // burst terminate if not at the end of a burst and another command to this
365
   // bank is not available.
366
 
367 9 dinesha
sdrc_xfr_ctl #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_xfr_ctl (
368 4 dinesha
          .clk                (clk          ),
369 3 dinesha
          .reset_n            (reset_n            ),
370
 
371
      /* Transfer request from bank_ctl */
372
          .r2x_idle           (r2x_idle           ),
373
          .b2x_idle           (b2x_idle           ),
374
          .b2x_req            (b2x_req            ),
375
          .b2x_start          (b2x_start          ),
376
          .b2x_last           (b2x_last           ),
377
          .b2x_wrap           (b2x_wrap           ),
378
          .b2x_id             (b2x_id             ),
379
          .b2x_ba             (b2x_ba             ),
380
          .b2x_addr           (b2x_addr           ),
381
          .b2x_len            (b2x_len            ),
382
          .b2x_cmd            (b2x_cmd            ),
383
          .x2b_ack            (x2b_ack            ),
384
 
385
       /* Status to bank_ctl, req_gen */
386
          .b2x_tras_ok        (b2x_tras_ok        ),
387
          .x2b_refresh        (x2b_refresh        ),
388
          .x2b_pre_ok         (x2b_pre_ok         ),
389
          .x2b_act_ok         (x2b_act_ok         ),
390
          .x2b_rdok           (x2b_rdok           ),
391
          .x2b_wrok           (x2b_wrok           ),
392
 
393
       /* SDRAM I/O */
394
          .sdr_cs_n           (sdr_cs_n           ),
395
          .sdr_cke            (sdr_cke            ),
396
          .sdr_ras_n          (sdr_ras_n          ),
397
          .sdr_cas_n          (sdr_cas_n          ),
398
          .sdr_we_n           (sdr_we_n           ),
399
          .sdr_dqm            (sdr_dqm            ),
400
          .sdr_ba             (sdr_ba             ),
401
          .sdr_addr           (sdr_addr           ),
402 23 dinesha
          .sdr_din            (pad_sdr_din2       ),
403 3 dinesha
          .sdr_dout           (sdr_dout_int       ),
404
          .sdr_den_n          (sdr_den_n_int      ),
405
      /* Data Flow to the app */
406 45 dinesha
          .x2a_rdstart        (x2a_rdstart        ),
407
          .x2a_wrstart        (x2a_wrstart        ),
408 3 dinesha
          .x2a_id             (xfr_id             ),
409 44 dinesha
          .x2a_rdlast         (x2a_rdlast         ),
410 45 dinesha
          .x2a_wrlast         (x2a_wrlast         ),
411
          .a2x_wrdt           (a2x_wrdt           ),
412
          .a2x_wren_n         (a2x_wren_n         ),
413
          .x2a_wrnext         (x2a_wrnext         ),
414
          .x2a_rddt           (x2a_rddt           ),
415
          .x2a_rdok           (x2a_rdok           ),
416 3 dinesha
          .sdr_init_done      (sdr_init_done      ),
417
 
418
      /* SDRAM Parameters */
419
          .sdram_enable       (cfg_sdr_en         ),
420
          .sdram_mode_reg     (cfg_sdr_mode_reg   ),
421
 
422
      /* current xfr bank */
423
          .xfr_bank_sel       (xfr_bank_sel       ),
424
 
425
      /* SDRAM Timing */
426
          .cas_latency        (cfg_sdr_cas        ),
427
          .trp_delay          (cfg_sdr_trp_d      ),
428
          .trcar_delay        (cfg_sdr_trcar_d    ),
429
          .twr_delay          (cfg_sdr_twr_d      ),
430
          .rfsh_time          (cfg_sdr_rfsh       ),
431
          .rfsh_rmax          (cfg_sdr_rfmax      )
432
    );
433
 
434 33 dinesha
   /****************************************************************************/
435
   // Instantiate sdr_bs_convert
436
   //    This model handle the bus with transaltion from application layer to
437
   //       8/16/32 SDRAM Memory format
438
   //     During Write Phase, this block split the data as per SDRAM Width
439
   //     During Read Phase, This block does the re-packing based on SDRAM
440
   //     Width
441
   //---------------------------------------------------------------------------
442 9 dinesha
sdrc_bs_convert #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_bs_convert (
443 4 dinesha
          .clk                (clk          ),
444 3 dinesha
          .reset_n            (reset_n            ),
445
          .sdr_width          (sdr_width          ),
446
 
447 44 dinesha
   /* Control Signal from xfr ctrl */
448 45 dinesha
          // Read Interface Inputs
449
          .x2a_rdstart        (x2a_rdstart        ),
450 44 dinesha
          .x2a_rdlast         (x2a_rdlast         ),
451 45 dinesha
          .x2a_rdok           (x2a_rdok           ),
452
          // Read Interface outputs
453
          .x2a_rddt           (x2a_rddt           ),
454 44 dinesha
 
455 45 dinesha
          // Write Interface, Inputs
456
          .x2a_wrstart        (x2a_wrstart        ),
457
          .x2a_wrlast         (x2a_wrlast         ),
458
          .x2a_wrnext         (x2a_wrnext         ),
459 44 dinesha
 
460 45 dinesha
          // Write Interface, Outputs
461
          .a2x_wrdt           (a2x_wrdt           ),
462
          .a2x_wren_n         (a2x_wren_n         ),
463 44 dinesha
 
464 45 dinesha
   /* Control Signal from sdrc_bank_ctl  */
465
 
466 44 dinesha
   /*  Control Signal from/to to application i/f  */
467 3 dinesha
          .app_wr_data        (app_wr_data        ),
468
          .app_wr_en_n        (app_wr_en_n        ),
469
          .app_wr_next        (app_wr_next_req    ),
470 45 dinesha
          .app_last_wr        (app_last_wr        ),
471 3 dinesha
          .app_rd_data        (app_rd_data        ),
472 45 dinesha
          .app_rd_valid       (app_rd_valid       ),
473
          .app_last_rd        (app_last_rd        )
474 44 dinesha
 
475 3 dinesha
       );
476
 
477
endmodule // sdrc_core

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