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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Blame information for rev 9

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1 3 dinesha
/*********************************************************************
2
 
3
  SDRAM Controller Core File
4
 
5
  This file is part of the sdram controller project
6
  http://www.opencores.org/cores/sdr_ctrl/
7
 
8
  Description: SDRAM Controller Core Module
9
    2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank.
10
    This block integrate following sub modules
11
 
12
    sdrc_bs_convert
13
        convert the system side 32 bit into equvailent 16/32 SDR format
14
    sdrc_req_gen
15
        This module takes requests from the app, chops them to burst booundaries
16
        if wrap=0, decodes the bank and passe the request to bank_ctl
17
   sdrc_xfr_ctl
18
      This module takes requests from sdr_bank_ctl, runs the transfer and
19
      controls data flow to/from the app. At the end of the transfer it issues a
20
      burst terminate if not at the end of a burst and another command to this
21
      bank is not available.
22
 
23
   sdrc_bank_ctl
24
      This module takes requests from sdr_req_gen, checks for page hit/miss and
25
      issues precharge/activate commands and then passes the request to
26
      sdr_xfr_ctl.
27
 
28
 
29
  Assumption: SDRAM Pads should be placed near to this module. else
30
  user should add a FF near the pads
31
 
32
  To Do:
33
    nothing
34
 
35
  Author(s):
36
      - Dinesh Annayya, dinesha@opencores.org
37
  Version  : 1.0 - 8th Jan 2012
38
 
39
 
40
 
41
 Copyright (C) 2000 Authors and OPENCORES.ORG
42
 
43
 This source file may be used and distributed without
44
 restriction provided that this copyright statement is not
45
 removed from the file and that any derivative work contains
46
 the original copyright notice and the associated disclaimer.
47
 
48
 This source file is free software; you can redistribute it
49
 and/or modify it under the terms of the GNU Lesser General
50
 Public License as published by the Free Software Foundation;
51
 either version 2.1 of the License, or (at your option) any
52
later version.
53
 
54
 This source is distributed in the hope that it will be
55
 useful, but WITHOUT ANY WARRANTY; without even the implied
56
 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
57
 PURPOSE.  See the GNU Lesser General Public License for more
58
 details.
59
 
60
 You should have received a copy of the GNU Lesser General
61
 Public License along with this source; if not, download it
62
 from http://www.opencores.org/lgpl.shtml
63
 
64
*******************************************************************/
65
 
66
 
67
`include "sdrc.def"
68
module sdrc_core
69
           (
70 4 dinesha
                clk,
71
                pad_clk,
72 3 dinesha
                reset_n,
73
                sdr_width,
74
 
75
                /* Request from app */
76
                app_req,                // Transfer Request
77
                app_req_addr,           // SDRAM Address
78
                app_req_addr_mask,      // Address mask for queue wrap
79
                app_req_len,            // Burst Length (in 16 bit words)
80
                app_req_wrap,           // Wrap mode request (xfr_len = 4)
81
                app_req_wr_n,           // 0 => Write request, 1 => read req
82
                app_req_ack,            // Request has been accepted
83
                sdr_core_busy_n,                // OK to arbitrate next request
84
                cfg_req_depth,          //how many req. buffer should hold
85
 
86
                app_wr_data,
87
                app_wr_en_n,
88
                app_rd_data,
89
                app_rd_valid,
90
                app_wr_next_req,
91
                sdr_init_done,
92
                app_req_dma_last,
93
 
94
                /* Interface to SDRAMs */
95
                sdr_cs_n,
96
                sdr_cke,
97
                sdr_ras_n,
98
                sdr_cas_n,
99
                sdr_we_n,
100
                sdr_dqm,
101
                sdr_ba,
102
                sdr_addr,
103
                pad_sdr_din,
104
                sdr_dout,
105
                sdr_den_n,
106
 
107
                /* Parameters */
108
                cfg_sdr_en,
109
                cfg_sdr_dev_config,     // using 64M/4bank SDRAMs
110
                cfg_sdr_mode_reg,
111
                cfg_sdr_tras_d,
112
                cfg_sdr_trp_d,
113
                cfg_sdr_trcd_d,
114
                cfg_sdr_cas,
115
                cfg_sdr_trcar_d,
116
                cfg_sdr_twr_d,
117
                cfg_sdr_rfsh,
118
                cfg_sdr_rfmax);
119
 
120
parameter  APP_AW   = 30;  // Application Address Width
121
parameter  APP_DW   = 32;  // Application Data Width 
122
parameter  APP_BW   = 4;   // Application Byte Width
123
parameter  APP_RW   = 9;   // Application Request Width
124
 
125
parameter  SDR_DW   = 16;  // SDR Data Width 
126
parameter  SDR_BW   = 2;   // SDR Byte Width
127
 
128
 
129
//-----------------------------------------------
130
// Global Variable
131
// ----------------------------------------------
132 4 dinesha
input                   clk                 ; // SDRAM Clock 
133
input                   pad_clk             ; // SDRAM Clock from Pad, used for registering Read Data
134 3 dinesha
input                   reset_n             ; // Reset Signal
135
input                   sdr_width           ; // 0 - 32 Bit SDR, 1 - 16 Bit SDR
136
 
137
//------------------------------------------------
138
// Request from app
139
//------------------------------------------------
140
input                   app_req             ; // Application Request
141
input [APP_AW-1:0]       app_req_addr        ; // Address 
142
input [APP_AW-2:0]      app_req_addr_mask   ; // Address Mask
143
input                   app_req_wr_n        ; // 0 - Write, 1 - Read
144
input                   app_req_wrap        ; // Address Wrap
145
output                  app_req_ack         ; // Application Request Ack
146
output                  sdr_core_busy_n     ; // 0 - busy, 1 - free
147
 
148
input [APP_DW-1:0]       app_wr_data         ; // Write Data
149
output                  app_wr_next_req     ; // Next Write Data Request
150
input [APP_BW-1:0]       app_wr_en_n         ; // Byte wise Write Enable
151
output [APP_DW-1:0]      app_rd_data         ; // Read Data
152
output                  app_rd_valid        ; // Read Valid
153
 
154
//------------------------------------------------
155
// Interface to SDRAMs
156
//------------------------------------------------
157
output                  sdr_cke             ; // SDRAM CKE
158
output                  sdr_cs_n            ; // SDRAM Chip Select
159
output                  sdr_ras_n           ; // SDRAM ras
160
output                  sdr_cas_n           ; // SDRAM cas
161
output                  sdr_we_n            ; // SDRAM write enable
162
output [SDR_BW-1:0]      sdr_dqm             ; // SDRAM Data Mask
163
output [1:0]             sdr_ba              ; // SDRAM Bank Enable
164
output [11:0]            sdr_addr            ; // SDRAM Address
165
input [SDR_DW-1:0]       pad_sdr_din         ; // SDRA Data Input
166
output [SDR_DW-1:0]      sdr_dout            ; // SDRAM Data Output
167
output [SDR_BW-1:0]      sdr_den_n           ; // SDRAM Data Output enable
168
 
169
//------------------------------------------------
170
// Configuration Parameter
171
//------------------------------------------------
172
output                  sdr_init_done       ;
173
input [3:0]              cfg_sdr_tras_d      ;
174
input [3:0]             cfg_sdr_trp_d       ;
175
input [3:0]             cfg_sdr_trcd_d      ;
176
input                   cfg_sdr_en          ;
177
input [1:0]             cfg_sdr_dev_config  ; // 2'b00 - 8 MB, 01 - 16 MB, 10 - 32 MB , 11 - 64 MB
178
input [1:0]              cfg_req_depth       ;
179
input [APP_RW-1:0]       app_req_len         ;
180
input [11:0]             cfg_sdr_mode_reg    ;
181
input [2:0]              cfg_sdr_cas         ;
182
input [3:0]              cfg_sdr_trcar_d     ;
183
input [3:0]             cfg_sdr_twr_d       ;
184
input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
185
input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
186
input                   app_req_dma_last;    // this signal should close the bank
187
 
188
/****************************************************************************/
189
// Internal Nets
190
 
191
// SDR_REQ_GEN
192
wire                    r2x_idle, app_req_ack,app_req_ack_int;
193
wire                    app_req_dma_last_int;
194
wire                    r2b_req, r2b_start, r2b_last, r2b_write;
195
wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
196
wire [1:0]               r2b_ba;
197
wire [11:0]              r2b_raddr;
198
wire [11:0]              r2b_caddr;
199
wire [APP_RW-1:0]        r2b_len;
200
 
201
// SDR BANK CTL
202
wire                    b2r_ack, b2x_idle;
203
wire                    b2x_req, b2x_start, b2x_last, b2x_tras_ok;
204
wire [`SDR_REQ_ID_W-1:0]b2x_id;
205
wire [1:0]               b2x_ba;
206
wire                    b2x_ba_last;
207
wire [11:0]              b2x_addr;
208
wire [APP_RW-1:0]        b2x_len;
209
wire [1:0]               b2x_cmd;
210
 
211
// SDR_XFR_CTL
212
wire                    x2b_ack;
213
wire [3:0]               x2b_pre_ok;
214
wire                    x2b_refresh, x2b_act_ok, x2b_rdok, x2b_wrok;
215
wire                    xfr_rdstart, xfr_rdlast;
216
wire                    xfr_wrstart, xfr_wrlast;
217
wire [`SDR_REQ_ID_W-1:0]xfr_id;
218
wire [13:0]              xfr_addr_msb;
219
wire [APP_DW-1:0]        app_rd_data;
220
wire                    app_wr_next_req, app_rd_valid;
221
wire                    sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n;
222
wire [SDR_BW-1:0]        sdr_dqm;
223
wire [1:0]               sdr_ba;
224
wire [11:0]              sdr_addr;
225
wire [SDR_DW-1:0]        sdr_dout;
226
wire [SDR_DW-1:0]        sdr_dout_int;
227
wire [SDR_BW-1:0]        sdr_den_n;
228
wire [SDR_BW-1:0]        sdr_den_n_int;
229
 
230
wire [1:0]               xfr_bank_sel;
231
wire [1:0]               cfg_sdr_dev_config;
232
 
233
wire [APP_AW:0]          app_req_addr_int;
234
wire [APP_AW-1:0]        app_req_addr;
235
wire [APP_RW-1:0]        app_req_len_int;
236
wire [APP_RW-1:0]        app_req_len;
237
 
238
wire [APP_DW-1:0]        app_wr_data;
239
wire [SDR_DW-1:0]        add_wr_data_int;
240
wire [APP_BW-1:0]        app_wr_en_n;
241
wire [SDR_BW-1:0]        app_wr_en_n_int;
242
 
243
//wire [31:0] app_rd_data;
244
wire [SDR_DW-1:0]        app_rd_data_int;
245
 
246
//
247
wire                     app_req_int;
248
wire                     r2b_wrap;
249
wire                     b2r_arb_ok;
250
wire                     b2x_wrap;
251
wire                     app_wr_next_int;
252
wire                     app_rd_valid_int;
253
 
254
// synopsys translate_off 
255
   wire [3:0]           sdr_cmd;
256
   assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n};
257
// synopsys translate_on 
258
 
259
   assign sdr_den_n = sdr_width ? {2'b00,sdr_den_n_int[1:0]} : sdr_den_n_int;
260
   assign sdr_dout = sdr_width ? {16'h0000,sdr_dout_int[15:0]} : sdr_dout_int;
261
 
262
 
263
   /****************************************************************************/
264
   // Instantiate sdr_req_gen
265
   // This module takes requests from the app, chops them to burst booundaries
266
   // if wrap=0, decodes the bank and passe the request to bank_ctl
267
 
268 9 dinesha
sdrc_req_gen #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_req_gen (
269 4 dinesha
          .clk                (clk          ),
270 3 dinesha
          .reset_n            (reset_n            ),
271
          .sdr_dev_config     (cfg_sdr_dev_config ),
272
 
273
        /* Request from app */
274
          .r2x_idle           (r2x_idle           ),
275
          .req                (app_req_int        ),
276
          .req_id             (4'b0               ),
277
          .req_addr           (app_req_addr_int   ),
278
          .req_addr_mask      (app_req_addr_mask  ),
279
          .req_len            (app_req_len_int    ),
280
          .req_wrap           (app_req_wrap       ),
281
          .req_wr_n           (app_req_wr_n       ),
282
          .req_ack            (app_req_ack_int      ),
283
          .sdr_core_busy_n    (sdr_core_busy_n    ),
284
 
285
       /* Req to bank_ctl */
286
          .r2b_req            (r2b_req            ),
287
          .r2b_req_id         (r2b_req_id         ),
288
          .r2b_start          (r2b_start          ),
289
          .r2b_last           (r2b_last           ),
290
          .r2b_wrap           (r2b_wrap           ),
291
          .r2b_ba             (r2b_ba             ),
292
          .r2b_raddr          (r2b_raddr          ),
293
          .r2b_caddr          (r2b_caddr          ),
294
          .r2b_len            (r2b_len            ),
295
          .r2b_write          (r2b_write          ),
296
          .b2r_ack            (b2r_ack            ),
297
          .b2r_arb_ok         (b2r_arb_ok         ),
298
          .sdr_width          (sdr_width          ),
299
          .sdr_init_done      (sdr_init_done      )
300
     );
301
 
302
   /****************************************************************************/
303
   // Instantiate sdr_bank_ctl
304
   // This module takes requests from sdr_req_gen, checks for page hit/miss and
305
   // issues precharge/activate commands and then passes the request to
306
   // sdr_xfr_ctl. 
307
 
308 9 dinesha
sdrc_bank_ctl #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_bank_ctl (
309 4 dinesha
          .clk                (clk          ),
310 3 dinesha
          .reset_n            (reset_n            ),
311
          .a2b_req_depth      (cfg_req_depth      ),
312
 
313
      /* Req from req_gen */
314
          .r2b_req            (r2b_req            ),
315
          .r2b_req_id         (r2b_req_id         ),
316
          .r2b_start          (r2b_start          ),
317
          .r2b_last           (r2b_last           ),
318
          .r2b_wrap           (r2b_wrap           ),
319
          .r2b_ba             (r2b_ba             ),
320
          .r2b_raddr          (r2b_raddr          ),
321
          .r2b_caddr          (r2b_caddr          ),
322
          .r2b_len            (r2b_len            ),
323
          .r2b_write          (r2b_write          ),
324
          .b2r_arb_ok         (b2r_arb_ok         ),
325
          .b2r_ack            (b2r_ack            ),
326
 
327
      /* Transfer request to xfr_ctl */
328
          .b2x_idle           (b2x_idle           ),
329
          .b2x_req            (b2x_req            ),
330
          .b2x_start          (b2x_start          ),
331
          .b2x_last           (b2x_last           ),
332
          .b2x_wrap           (b2x_wrap           ),
333
          .b2x_id             (b2x_id             ),
334
          .b2x_ba             (b2x_ba             ),
335
          .b2x_addr           (b2x_addr           ),
336
          .b2x_len            (b2x_len            ),
337
          .b2x_cmd            (b2x_cmd            ),
338
          .x2b_ack            (x2b_ack            ),
339
 
340
      /* Status from xfr_ctl */
341
          .b2x_tras_ok        (b2x_tras_ok        ),
342
          .x2b_refresh        (x2b_refresh        ),
343
          .x2b_pre_ok         (x2b_pre_ok         ),
344
          .x2b_act_ok         (x2b_act_ok         ),
345
          .x2b_rdok           (x2b_rdok           ),
346
          .x2b_wrok           (x2b_wrok           ),
347
 
348
      /* for generate cuurent xfr address msb */
349
          .sdr_dev_config     (cfg_sdr_dev_config ),
350
          .sdr_req_norm_dma_last(app_req_dma_last_int),
351
          .xfr_bank_sel       (xfr_bank_sel       ),
352
          .xfr_addr_msb       (xfr_addr_msb       ),
353
 
354
       /* SDRAM Timing */
355
          .tras_delay         (cfg_sdr_tras_d     ),
356
          .trp_delay          (cfg_sdr_trp_d      ),
357
          .trcd_delay         (cfg_sdr_trcd_d     )
358
      );
359
 
360
   /****************************************************************************/
361
   // Instantiate sdr_xfr_ctl
362
   // This module takes requests from sdr_bank_ctl, runs the transfer and
363
   // controls data flow to/from the app. At the end of the transfer it issues a
364
   // burst terminate if not at the end of a burst and another command to this
365
   // bank is not available.
366
 
367 9 dinesha
sdrc_xfr_ctl #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_xfr_ctl (
368 4 dinesha
          .clk                (clk          ),
369 3 dinesha
          .reset_n            (reset_n            ),
370
 
371
      /* Transfer request from bank_ctl */
372
          .r2x_idle           (r2x_idle           ),
373
          .b2x_idle           (b2x_idle           ),
374
          .b2x_req            (b2x_req            ),
375
          .b2x_start          (b2x_start          ),
376
          .b2x_last           (b2x_last           ),
377
          .b2x_wrap           (b2x_wrap           ),
378
          .b2x_id             (b2x_id             ),
379
          .b2x_ba             (b2x_ba             ),
380
          .b2x_addr           (b2x_addr           ),
381
          .b2x_len            (b2x_len            ),
382
          .b2x_cmd            (b2x_cmd            ),
383
          .x2b_ack            (x2b_ack            ),
384
 
385
       /* Status to bank_ctl, req_gen */
386
          .b2x_tras_ok        (b2x_tras_ok        ),
387
          .x2b_refresh        (x2b_refresh        ),
388
          .x2b_pre_ok         (x2b_pre_ok         ),
389
          .x2b_act_ok         (x2b_act_ok         ),
390
          .x2b_rdok           (x2b_rdok           ),
391
          .x2b_wrok           (x2b_wrok           ),
392
 
393
       /* SDRAM I/O */
394
          .sdr_cs_n           (sdr_cs_n           ),
395
          .sdr_cke            (sdr_cke            ),
396
          .sdr_ras_n          (sdr_ras_n          ),
397
          .sdr_cas_n          (sdr_cas_n          ),
398
          .sdr_we_n           (sdr_we_n           ),
399
          .sdr_dqm            (sdr_dqm            ),
400
          .sdr_ba             (sdr_ba             ),
401
          .sdr_addr           (sdr_addr           ),
402
          .sdr_din            (pad_sdr_din        ),
403
          .sdr_dout           (sdr_dout_int       ),
404
          .sdr_den_n          (sdr_den_n_int      ),
405
 
406
      /* Data Flow to the app */
407
          .x2a_rdstart        (xfr_rdstart        ),
408
          .x2a_wrstart        (xfr_wrstart        ),
409
          .x2a_id             (xfr_id             ),
410
          .x2a_rdlast         (xfr_rdlast         ),
411
          .x2a_wrlast         (xfr_wrlast         ),
412
          .app_wrdt           (add_wr_data_int    ),
413 4 dinesha
          .app_wren_n         (app_wr_en_n_int    ),
414 3 dinesha
          .x2a_wrnext         (app_wr_next_int    ),
415
          .x2a_rddt           (app_rd_data_int    ),
416
          .x2a_rdok           (app_rd_valid_int   ),
417
          .sdr_init_done      (sdr_init_done      ),
418
 
419
      /* SDRAM Parameters */
420
          .sdram_enable       (cfg_sdr_en         ),
421
          .sdram_mode_reg     (cfg_sdr_mode_reg   ),
422
 
423
      /* current xfr bank */
424
          .xfr_bank_sel       (xfr_bank_sel       ),
425
 
426
      /* SDRAM Timing */
427
          .cas_latency        (cfg_sdr_cas        ),
428
          .trp_delay          (cfg_sdr_trp_d      ),
429
          .trcar_delay        (cfg_sdr_trcar_d    ),
430
          .twr_delay          (cfg_sdr_twr_d      ),
431
          .rfsh_time          (cfg_sdr_rfsh       ),
432
          .rfsh_rmax          (cfg_sdr_rfmax      )
433
    );
434
 
435 9 dinesha
sdrc_bs_convert #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_bs_convert (
436 4 dinesha
          .clk                (clk          ),
437 3 dinesha
          .reset_n            (reset_n            ),
438
          .sdr_width          (sdr_width          ),
439
 
440
          .app_req_addr       (app_req_addr       ),
441
          .app_req_addr_int   (app_req_addr_int   ),
442
          .app_req_len        (app_req_len        ),
443
          .app_req_len_int    (app_req_len_int    ),
444
          .app_sdr_req        (app_req            ),
445
          .app_sdr_req_int    (app_req_int        ),
446
          .app_req_dma_last   (app_req_dma_last   ),
447
          .app_req_dma_last_int(app_req_dma_last_int),
448
          .app_req_wr_n       (app_req_wr_n       ),
449 4 dinesha
          .app_req_ack_int    (app_req_ack_int    ),
450 3 dinesha
          .app_req_ack        (app_req_ack        ),
451
 
452
          .app_wr_data        (app_wr_data        ),
453
          .app_wr_data_int    (add_wr_data_int    ),
454
          .app_wr_en_n        (app_wr_en_n        ),
455
          .app_wr_en_n_int    (app_wr_en_n_int    ),
456
          .app_wr_next_int    (app_wr_next_int    ),
457
          .app_wr_next        (app_wr_next_req    ),
458
 
459
          .app_rd_data_int    (app_rd_data_int    ),
460
          .app_rd_data        (app_rd_data        ),
461
          .app_rd_valid_int   (app_rd_valid_int   ),
462
          .app_rd_valid       (app_rd_valid       )
463
       );
464
 
465
endmodule // sdrc_core

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