OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_define.v] - Blame information for rev 73

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 dinesha
 
2
`define SDR_REQ_ID_W       4
3
 
4
`define SDR_RFSH_TIMER_W    12
5
`define SDR_RFSH_ROW_CNT_W   3
6
 
7
// B2X Command
8
 
9
`define OP_PRE           2'b00
10
`define OP_ACT           2'b01
11
`define OP_RD            2'b10
12
`define OP_WR            2'b11
13
 
14
// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
15
 
16
`define SDR_DESEL        4'b1111
17
`define SDR_NOOP         4'b0111
18
`define SDR_ACTIVATE     4'b0011
19
`define SDR_READ         4'b0101
20
`define SDR_WRITE        4'b0100
21
`define SDR_BT           4'b0110
22
`define SDR_PRECHARGE    4'b0010
23
`define SDR_REFRESH      4'b0001
24
`define SDR_MODE         4'b0000
25
 
26 51 dinesha
`define  ASIC            1'b1
27
`define  FPGA            1'b0
28 73 dinesha
// Don't Enable FPGA mode, there is functional bug  in handling Active to
29
// Precharge timing
30
`define  TARGET_DESIGN   `ASIC
31 54 dinesha
// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
32
`define  REQ_BW    (`TARGET_DESIGN == `FPGA) ? 6 : 12   //  Request Width
33 3 dinesha
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.