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[/] [sdr_ctrl/] [trunk/] [rtl/] [top/] [sdrc_top.v] - Blame information for rev 38

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1 31 dinesha
/*********************************************************************
2
 
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  SDRAM Controller top File
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  This file is part of the sdram controller project
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  http://www.opencores.org/cores/sdr_ctrl/
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8 33 dinesha
  Description: SDRAM Controller Top Module.
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    Support 81/6/32 Bit SDRAM.
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    Column Address is Programmable
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    Bank Bit are 2 Bit
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    Row Bits are 12 Bits
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14 31 dinesha
    This block integrate following sub modules
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    sdrc_core
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        SDRAM Controller file
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    wb2sdrc
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        This module transalate the bus protocl from wishbone to custome
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        sdram controller
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  To Do:
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    nothing
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  Author(s): Dinesh Annayya, dinesha@opencores.org
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  Version  : 0.0 - 8th Jan 2012
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                Initial version with 16/32 Bit SDRAM Support
28 37 dinesha
           : 0.1 - 24th Jan 2012
29 31 dinesha
                 8 Bit SDRAM Support is added
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             0.2 - 31st Jan 2012
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                 sdram_dq and sdram_pad_clk are internally generated
32 31 dinesha
 
33
 
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 Copyright (C) 2000 Authors and OPENCORES.ORG
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 This source file may be used and distributed without
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 restriction provided that this copyright statement is not
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 removed from the file and that any derivative work contains
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 the original copyright notice and the associated disclaimer.
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 This source file is free software; you can redistribute it
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 and/or modify it under the terms of the GNU Lesser General
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 Public License as published by the Free Software Foundation;
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 either version 2.1 of the License, or (at your option) any
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later version.
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 This source is distributed in the hope that it will be
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 useful, but WITHOUT ANY WARRANTY; without even the implied
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 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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 PURPOSE.  See the GNU Lesser General Public License for more
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 details.
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 You should have received a copy of the GNU Lesser General
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 Public License along with this source; if not, download it
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 from http://www.opencores.org/lgpl.shtml
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*******************************************************************/
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60 37 dinesha
`include "sdrc_define.v"
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module sdrc_top
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           (
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                    cfg_sdr_width       ,
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                    cfg_colbits         ,
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                // WB bus
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                    wb_rst_i            ,
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                    wb_clk_i            ,
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                    wb_stb_i            ,
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                    wb_ack_o            ,
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                    wb_addr_i           ,
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                    wb_we_i             ,
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                    wb_dat_i            ,
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                    wb_sel_i            ,
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                    wb_dat_o            ,
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                    wb_cyc_i            ,
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                    wb_cti_i            ,
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80
 
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                /* Interface to SDRAMs */
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                    sdram_clk           ,
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                    sdram_resetn        ,
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                    sdr_cs_n            ,
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                    sdr_cke             ,
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                    sdr_ras_n           ,
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                    sdr_cas_n           ,
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                    sdr_we_n            ,
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                    sdr_dqm             ,
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                    sdr_ba              ,
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                    sdr_addr            ,
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                    sdr_dq              ,
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94 31 dinesha
                /* Parameters */
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                    sdr_init_done       ,
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                    cfg_req_depth       ,               //how many req. buffer should hold
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                    cfg_sdr_en          ,
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                    cfg_sdr_mode_reg    ,
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                    cfg_sdr_tras_d      ,
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                    cfg_sdr_trp_d       ,
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                    cfg_sdr_trcd_d      ,
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                    cfg_sdr_cas         ,
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                    cfg_sdr_trcar_d     ,
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                    cfg_sdr_twr_d       ,
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                    cfg_sdr_rfsh        ,
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                    cfg_sdr_rfmax
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            );
108 31 dinesha
 
109 33 dinesha
parameter      APP_AW   = 30;  // Application Address Width
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parameter      APP_DW   = 32;  // Application Data Width 
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parameter      APP_BW   = 4;   // Application Byte Width
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parameter      APP_RW   = 9;   // Application Request Width
113 31 dinesha
 
114 33 dinesha
parameter      SDR_DW   = 16;  // SDR Data Width 
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parameter      SDR_BW   = 2;   // SDR Byte Width
116 31 dinesha
 
117 33 dinesha
parameter      dw       = 32;  // data width
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parameter      tw       = 8;   // tag id width
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parameter      bl       = 9;   // burst_lenght_width 
120 31 dinesha
 
121
//-----------------------------------------------
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// Global Variable
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// ----------------------------------------------
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input                   sdram_clk          ; // SDRAM Clock 
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input                   sdram_resetn       ; // Reset Signal
126 38 dinesha
input [1:0]             cfg_sdr_width      ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
127 33 dinesha
input [1:0]             cfg_colbits        ; // 2'b00 - 8 Bit column address, 
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                                             // 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
129 31 dinesha
 
130
//--------------------------------------
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// Wish Bone Interface
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// -------------------------------------      
133 33 dinesha
input                   wb_rst_i           ;
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input                   wb_clk_i           ;
135 31 dinesha
 
136 33 dinesha
input                   wb_stb_i           ;
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output                  wb_ack_o           ;
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input [29:0]            wb_addr_i          ;
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input                   wb_we_i            ; // 1 - Write, 0 - Read
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input [dw-1:0]          wb_dat_i           ;
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input [dw/8-1:0]        wb_sel_i           ; // Byte enable
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output [dw-1:0]         wb_dat_o           ;
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input                   wb_cyc_i           ;
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input  [2:0]            wb_cti_i           ;
145 31 dinesha
 
146
//------------------------------------------------
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// Interface to SDRAMs
148
//------------------------------------------------
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output                  sdr_cke             ; // SDRAM CKE
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output                  sdr_cs_n            ; // SDRAM Chip Select
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output                  sdr_ras_n           ; // SDRAM ras
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output                  sdr_cas_n           ; // SDRAM cas
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output                  sdr_we_n            ; // SDRAM write enable
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output [SDR_BW-1:0]      sdr_dqm             ; // SDRAM Data Mask
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output [1:0]             sdr_ba              ; // SDRAM Bank Enable
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output [11:0]            sdr_addr            ; // SDRAM Address
157 37 dinesha
inout [SDR_DW-1:0]       sdr_dq              ; // SDRA Data Input/output
158 31 dinesha
 
159
//------------------------------------------------
160
// Configuration Parameter
161
//------------------------------------------------
162
output                  sdr_init_done       ; // Indicate SDRAM Initialisation Done
163
input [3:0]              cfg_sdr_tras_d      ; // Active to precharge delay
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input [3:0]             cfg_sdr_trp_d       ; // Precharge to active delay
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input [3:0]             cfg_sdr_trcd_d      ; // Active to R/W delay
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input                   cfg_sdr_en          ; // Enable SDRAM controller
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input [1:0]              cfg_req_depth       ; // Maximum Request accepted by SDRAM controller
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input [11:0]             cfg_sdr_mode_reg    ;
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input [2:0]              cfg_sdr_cas         ; // SDRAM CAS Latency
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input [3:0]              cfg_sdr_trcar_d     ; // Auto-refresh period
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input [3:0]             cfg_sdr_twr_d       ; // Write recovery delay
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input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
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input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
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175
//--------------------------------------------
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// SDRAM controller Interface 
177
//--------------------------------------------
178
wire                  app_req            ; // SDRAM request
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wire [29:0]           app_req_addr       ; // SDRAM Request Address
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wire [bl-1:0]         app_req_len        ;
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wire                  app_req_wr_n       ; // 0 - Write, 1 -> Read
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wire                  app_req_ack        ; // SDRAM request Accepted
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wire                  app_busy_n         ; // 0 -> sdr busy
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wire [dw/8-1:0]       app_wr_en_n        ; // Active low sdr byte-wise write data valid
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wire                  app_wr_next_req    ; // Ready to accept the next write
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wire                  app_rd_valid       ; // sdr read valid
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wire                  app_last_rd        ; // Indicate last Read of Burst Transfer
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wire [dw-1:0]         app_wr_data        ; // sdr write data
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wire  [dw-1:0]        app_rd_data        ; // sdr read data
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191 37 dinesha
/****************************************
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*  These logic has to be implemented using Pads
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*  **************************************/
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wire  [SDR_DW-1:0]    pad_sdr_din         ; // SDRA Data Input
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wire  [SDR_DW-1:0]    sdr_dout            ; // SDRAM Data Output
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wire  [SDR_BW-1:0]    sdr_den_n           ; // SDRAM Data Output enable
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assign   sdr_dq = (&sdr_den_n == 1'b0) ? sdr_dout :  {SDR_DW{1'bz}};
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assign   pad_sdr_din = sdr_dq;
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// sdram pad clock is routed back through pad
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// SDRAM Clock from Pad, used for registering Read Data
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wire #(1.0) sdram_pad_clk = sdram_clk;
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/************** Ends Here **************************/
207 31 dinesha
wb2sdrc u_wb2sdrc (
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      // WB bus
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          .wb_rst_i           (wb_rst_i           ) ,
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          .wb_clk_i           (wb_clk_i           ) ,
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          .wb_stb_i           (wb_stb_i           ) ,
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          .wb_ack_o           (wb_ack_o           ) ,
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          .wb_addr_i          (wb_addr_i          ) ,
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          .wb_we_i            (wb_we_i            ) ,
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          .wb_dat_i           (wb_dat_i           ) ,
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          .wb_sel_i           (wb_sel_i           ) ,
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          .wb_dat_o           (wb_dat_o           ) ,
219
          .wb_cyc_i           (wb_cyc_i           ) ,
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          .wb_cti_i           (wb_cti_i           ) ,
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      //SDRAM Controller Hand-Shake Signal 
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          .sdram_clk          (sdram_clk          ) ,
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          .sdram_resetn       (sdram_resetn       ) ,
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          .sdr_req            (app_req            ) ,
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          .sdr_req_addr       (app_req_addr       ) ,
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          .sdr_req_len        (app_req_len        ) ,
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          .sdr_req_wr_n       (app_req_wr_n       ) ,
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          .sdr_req_ack        (app_req_ack        ) ,
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          .sdr_busy_n         (app_busy_n         ) ,
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          .sdr_wr_en_n        (app_wr_en_n        ) ,
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          .sdr_wr_next        (app_wr_next_req    ) ,
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          .sdr_rd_valid       (app_rd_valid       ) ,
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          .sdr_last_rd        (app_last_rd        ) ,
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          .sdr_wr_data        (app_wr_data        ) ,
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          .sdr_rd_data        (app_rd_data        )
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239
      );
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sdrc_core #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_sdrc_core (
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          .clk                (sdram_clk          ) ,
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          .pad_clk            (sdram_pad_clk      ) ,
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          .reset_n            (sdram_resetn       ) ,
246 38 dinesha
          .sdr_width          (cfg_sdr_width      ) ,
247 31 dinesha
          .cfg_colbits        (cfg_colbits        ) ,
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                /* Request from app */
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          .app_req            (app_req            ) ,// Transfer Request
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          .app_req_addr       (app_req_addr       ) ,// SDRAM Address
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          .app_req_addr_mask  (29'h0              ) ,// Address mask for queue wrap
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          .app_req_len        (app_req_len        ) ,// Burst Length (in 16 bit words)
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          .app_req_wrap       (1'b0               ) ,// Wrap mode request 
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          .app_req_wr_n       (app_req_wr_n       ) ,// 0 => Write request, 1 => read req
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          .app_req_ack        (app_req_ack        ) ,// Request has been accepted
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          .sdr_core_busy_n    (app_core_busy_n    ) ,// OK to arbitrate next request
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          .cfg_req_depth      (cfg_req_depth      ) ,//how many req. buffer should hold
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          .app_wr_data        (app_wr_data        ) ,
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          .app_wr_en_n        (app_wr_en_n        ) ,
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          .app_rd_data        (app_rd_data        ) ,
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          .app_rd_valid       (app_rd_valid       ) ,
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          .app_last_rd        (app_last_rd        ) ,
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          .app_wr_next_req    (app_wr_next_req    ) ,
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          .sdr_init_done      (sdr_init_done      ) ,
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          .app_req_dma_last   (app_req            ) ,
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                /* Interface to SDRAMs */
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          .sdr_cs_n           (sdr_cs_n           ) ,
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          .sdr_cke            (sdr_cke            ) ,
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          .sdr_ras_n          (sdr_ras_n          ) ,
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          .sdr_cas_n          (sdr_cas_n          ) ,
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          .sdr_we_n           (sdr_we_n           ) ,
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          .sdr_dqm            (sdr_dqm            ) ,
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          .sdr_ba             (sdr_ba             ) ,
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          .sdr_addr           (sdr_addr           ) ,
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          .pad_sdr_din        (pad_sdr_din        ) ,
279
          .sdr_dout           (sdr_dout           ) ,
280
          .sdr_den_n          (sdr_den_n          ) ,
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282
                /* Parameters */
283
          .cfg_sdr_en         (cfg_sdr_en         ) ,
284
          .cfg_sdr_mode_reg   (cfg_sdr_mode_reg   ) ,
285
          .cfg_sdr_tras_d     (cfg_sdr_tras_d     ) ,
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          .cfg_sdr_trp_d      (cfg_sdr_trp_d      ) ,
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          .cfg_sdr_trcd_d     (cfg_sdr_trcd_d     ) ,
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          .cfg_sdr_cas        (cfg_sdr_cas        ) ,
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          .cfg_sdr_trcar_d    (cfg_sdr_trcar_d    ) ,
290
          .cfg_sdr_twr_d      (cfg_sdr_twr_d      ) ,
291
          .cfg_sdr_rfsh       (cfg_sdr_rfsh       ) ,
292
          .cfg_sdr_rfmax      (cfg_sdr_rfmax      )
293
               );
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295
endmodule // sdrc_core

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