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[/] [sdr_ctrl/] [trunk/] [rtl/] [wb2sdrc/] [wb2sdrc.v] - Blame information for rev 40

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1 31 dinesha
/*********************************************************************
2
 
3
  This file is part of the sdram controller project
4
  http://www.opencores.org/cores/sdr_ctrl/
5
 
6
  Description: WISHBONE to SDRAM Controller Bus Transalator
7 33 dinesha
     1. This module translate the WISHBONE protocol to custom sdram controller i/f
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     2. Also Handle the clock domain change from Application layer to Sdram layer
9 31 dinesha
 
10
  To Do:
11
    nothing
12
 
13
  Author(s):  Dinesh Annayya, dinesha@opencores.org
14 40 dinesha
  Version  : 0.0 - Initial Release
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             0.1 - 2nd Feb 2012
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                   Async Fifo towards the application layer is selected with Registered Full Generation
17 31 dinesha
 
18
 Copyright (C) 2000 Authors and OPENCORES.ORG
19
 
20 40 dinesha
 
21 31 dinesha
 This source file may be used and distributed without
22
 restriction provided that this copyright statement is not
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 removed from the file and that any derivative work contains
24
 the original copyright notice and the associated disclaimer.
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26
 This source file is free software; you can redistribute it
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 and/or modify it under the terms of the GNU Lesser General
28
 Public License as published by the Free Software Foundation;
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 either version 2.1 of the License, or (at your option) any
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later version.
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 This source is distributed in the hope that it will be
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 useful, but WITHOUT ANY WARRANTY; without even the implied
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 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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 PURPOSE.  See the GNU Lesser General Public License for more
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 details.
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38
 You should have received a copy of the GNU Lesser General
39
 Public License along with this source; if not, download it
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 from http://www.opencores.org/lgpl.shtml
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42
*******************************************************************/
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45
module wb2sdrc (
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      // WB bus
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                    wb_rst_i            ,
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                    wb_clk_i            ,
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                    wb_stb_i            ,
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                    wb_ack_o            ,
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                    wb_addr_i           ,
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                    wb_we_i             ,
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                    wb_dat_i            ,
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                    wb_sel_i            ,
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                    wb_dat_o            ,
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                    wb_cyc_i            ,
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                    wb_cti_i            ,
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60
 
61
      //SDRAM Controller Hand-Shake Signal 
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                    sdram_clk           ,
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                    sdram_resetn        ,
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                    sdr_req             ,
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                    sdr_req_addr        ,
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                    sdr_req_len         ,
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                    sdr_req_wr_n        ,
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                    sdr_req_ack         ,
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                    sdr_busy_n          ,
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                    sdr_wr_en_n         ,
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                    sdr_wr_next         ,
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                    sdr_rd_valid        ,
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                    sdr_last_rd         ,
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                    sdr_wr_data         ,
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                    sdr_rd_data
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77
      );
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79
parameter      dw              = 32;  // data width
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parameter      tw              = 8;   // tag id width
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parameter      bl              = 9;   // burst_lenght_width 
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//--------------------------------------
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// Wish Bone Interface
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// -------------------------------------      
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input                   wb_rst_i           ;
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input                   wb_clk_i           ;
87 31 dinesha
 
88 33 dinesha
input                   wb_stb_i           ;
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output                  wb_ack_o           ;
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input [29:0]            wb_addr_i          ;
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input                   wb_we_i            ; // 1 - Write , 0 - Read
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input [dw-1:0]          wb_dat_i           ;
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input [dw/8-1:0]        wb_sel_i           ; // Byte enable
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output [dw-1:0]         wb_dat_o           ;
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input                   wb_cyc_i           ;
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input  [2:0]            wb_cti_i           ;
97 31 dinesha
/***************************************************
98
The Cycle Type Idenfier [CTI_IO()] Address Tag provides
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additional information about the current cycle.
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The MASTER sends this information to the SLAVE. The SLAVE can use this
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information to prepare the response for the next cycle.
102
Table 4-2 Cycle Type Identifiers
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CTI_O(2:0) Description
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000 Classic cycle.
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001 Constant address burst cycle
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010 Incrementing burst cycle
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011 Reserved
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100 Reserved
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101 Reserved
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110 Reserved
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111 End-of-Burst
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****************************************************/
113
//--------------------------------------------
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// SDRAM controller Interface 
115
//--------------------------------------------
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input                   sdram_clk          ; // sdram clock
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input                   sdram_resetn       ; // sdram reset
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output                  sdr_req            ; // SDRAM request
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output [29:0]           sdr_req_addr       ; // SDRAM Request Address
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output [bl-1:0]         sdr_req_len        ;
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output                  sdr_req_wr_n       ; // 0 - Write, 1 -> Read
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input                   sdr_req_ack        ; // SDRAM request Accepted
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input                   sdr_busy_n         ; // 0 -> sdr busy
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output [dw/8-1:0]       sdr_wr_en_n        ; // Active low sdr byte-wise write data valid
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input                   sdr_wr_next        ; // Ready to accept the next write
126
input                   sdr_rd_valid       ; // sdr read valid
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input                   sdr_last_rd        ; // Indicate last Read of Burst Transfer
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output [dw-1:0]         sdr_wr_data        ; // sdr write data
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input  [dw-1:0]         sdr_rd_data        ; // sdr read data
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131
//----------------------------------------------------
132
// Wire Decleration
133
// ---------------------------------------------------
134 33 dinesha
wire                    cmdfifo_full       ;
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wire                    cmdfifo_empty      ;
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wire                    wrdatafifo_full    ;
137
wire                    wrdatafifo_empty   ;
138
wire                    tagfifo_full       ;
139
wire                    tagfifo_empty      ;
140
wire                    rddatafifo_empty   ;
141
wire                    rddatafifo_full    ;
142 31 dinesha
 
143 33 dinesha
reg                     pending_read       ;
144 31 dinesha
 
145
 
146 33 dinesha
//-----------------------------------------------------------------------------
147
// Ack Generaltion Logic
148
//  If Write Request - Acknowledge if the command and write FIFO are not full
149
//  If Read Request  - Generate the Acknowledgment once read fifo has data
150
//                     available
151
//-----------------------------------------------------------------------------
152 31 dinesha
 
153
assign wb_ack_o = (wb_stb_i && wb_cyc_i && wb_we_i) ?  // Write Phase
154
                          ((!cmdfifo_full) && (!wrdatafifo_full)) :
155
                  (wb_stb_i && wb_cyc_i && !wb_we_i) ? // Read Phase 
156
                           !rddatafifo_empty : 1'b0;
157
 
158 33 dinesha
//---------------------------------------------------------------------------
159
// Command FIFO Write Generation
160
//    If Write Request - Generate write, when Write fifo and command fifo is
161
//                       not full
162
//    If Read Request - Generate write, when command fifo not full and there
163
//                      is no pending read request.
164
//---------------------------------------------------------------------------
165
wire           cmdfifo_wr   = (wb_stb_i && wb_cyc_i && wb_we_i && (!cmdfifo_full) ) ? wb_ack_o :
166
                              (wb_stb_i && wb_cyc_i && !wb_we_i && (!cmdfifo_full)) ? !pending_read: 1'b0 ;
167
 
168
//---------------------------------------------------------------------------
169
// command fifo read generation
170
//    Command FIFo read will be generated, whenever SDRAM Controller
171
//    Acknowldge the Request
172
//----------------------------------------------------------------------------
173
 
174 31 dinesha
wire           cmdfifo_rd   = sdr_req_ack;
175 33 dinesha
 
176
//---------------------------------------------------------------------------
177
// Application layer request is generated towards the controller, whenever
178
// Command FIFO is not full
179
// --------------------------------------------------------------------------
180 31 dinesha
assign         sdr_req      = !cmdfifo_empty;
181
 
182 33 dinesha
//----------------------------------------------------------------------------
183
// Since Burst length is not known at the start of the Burst, It's assumed as
184
// Single Cycle Burst. We need to improvise this ...
185
// --------------------------------------------------------------------------
186 31 dinesha
wire [bl-1:0]  burst_length  = 1;  // 0 Mean 1 Transfer
187
 
188 33 dinesha
//-----------------------------------------------------------------------------
189
// In Wish Bone Spec, For Read Request has to be acked along with data.
190
// We need to identify the pending read request.
191
// Once we accept the read request, we should not accept one more read
192
// request, untill we have transmitted the read data.
193
//  Pending Read will 
194
//     set - with Read Request 
195
//     reset - with Read Request + Ack
196
// ----------------------------------------------------------------------------
197 31 dinesha
always @(posedge wb_rst_i or posedge wb_clk_i) begin
198
   if(wb_rst_i) begin
199
       pending_read <= 1'b0;
200
   end else begin
201
      pending_read <=  wb_stb_i & wb_cyc_i & !wb_we_i & !wb_ack_o;
202
   end
203
end
204
 
205 33 dinesha
//---------------------------------------------------------------------
206
// Async Command FIFO. This block handle the clock domain change from
207
// Application layer to SDRAM Controller
208
// ------------------------------------------------------------------
209 31 dinesha
   // Address + Burst Length + W/R Request 
210 40 dinesha
    async_fifo #(.W(30+bl+1),.DP(4),.WR_FAST(1'b0), .RD_FAST(1'b1)) u_cmdfifo (
211 31 dinesha
     // Write Path Sys CLock Domain
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          .wr_clk             (wb_clk_i           ),
213
          .wr_reset_n         (!wb_rst_i          ),
214
          .wr_en              (cmdfifo_wr         ),
215
          .wr_data            ({burst_length,
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                                !wb_we_i,
217
                                wb_addr_i}        ),
218
          .afull              (                   ),
219
          .full               (cmdfifo_full       ),
220 31 dinesha
 
221
     // Read Path, SDRAM clock domain
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          .rd_clk             (sdram_clk          ),
223
          .rd_reset_n         (sdram_resetn       ),
224
          .aempty             (                   ),
225
          .empty              (cmdfifo_empty      ),
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          .rd_en              (cmdfifo_rd         ),
227
          .rd_data            ({sdr_req_len,
228
                                sdr_req_wr_n,
229
                                sdr_req_addr}     )
230 31 dinesha
     );
231
 
232
// synopsys translate_off
233
always @(posedge wb_clk_i) begin
234
  if (cmdfifo_full == 1'b1 && cmdfifo_wr == 1'b1)  begin
235
     $display("ERROR:%m COMMAND FIFO WRITE OVERFLOW");
236
  end
237
end
238 37 dinesha
// synopsys translate_on
239 31 dinesha
// synopsys translate_off
240
always @(posedge sdram_clk) begin
241
   if (cmdfifo_empty == 1'b1 && cmdfifo_rd == 1'b1) begin
242
      $display("ERROR:%m COMMAND FIFO READ OVERFLOW");
243
   end
244
end
245
// synopsys translate_on
246
 
247 33 dinesha
//---------------------------------------------------------------------
248
// Write Data FIFO Write Generation, when ever Acked + Write Request
249
//   Note: Ack signal generation already taking account of FIFO full condition
250
// ---------------------------------------------------------------------
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252
wire  wrdatafifo_wr  = wb_ack_o & wb_we_i ;
253 33 dinesha
 
254
//------------------------------------------------------------------------
255
// Write Data FIFO Read Generation, When ever Next Write request generated
256
// from SDRAM Controller
257
// ------------------------------------------------------------------------
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wire  wrdatafifo_rd  = sdr_wr_next;
259
 
260
 
261 33 dinesha
//------------------------------------------------------------------------
262
// Async Write Data FIFO
263
//    This block handle the clock domain change over + Write Data + Byte mask 
264
//    From Application layer to SDRAM controller layer
265
//------------------------------------------------------------------------
266
 
267 31 dinesha
   // Write DATA + Data Mask FIFO
268 40 dinesha
    async_fifo #(.W(dw+(dw/8)), .DP(8), .WR_FAST(1'b0), .RD_FAST(1'b1)) u_wrdatafifo (
269 31 dinesha
       // Write Path , System clock domain
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          .wr_clk             (wb_clk_i           ),
271
          .wr_reset_n         (!wb_rst_i          ),
272
          .wr_en              (wrdatafifo_wr      ),
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          .wr_data            ({~wb_sel_i,
274
                                 wb_dat_i}        ),
275
          .afull              (                   ),
276
          .full               (wrdatafifo_full    ),
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278
 
279
       // Read Path , SDRAM clock domain
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          .rd_clk             (sdram_clk          ),
281
          .rd_reset_n         (sdram_resetn       ),
282
          .aempty             (                   ),
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          .empty              (wrdatafifo_empty   ),
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          .rd_en              (wrdatafifo_rd      ),
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          .rd_data            ({sdr_wr_en_n,
286
                                sdr_wr_data}      )
287 31 dinesha
     );
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// synopsys translate_off
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always @(posedge wb_clk_i) begin
290
  if (wrdatafifo_full == 1'b1 && wrdatafifo_wr == 1'b1)  begin
291
     $display("ERROR:%m WRITE DATA FIFO WRITE OVERFLOW");
292
  end
293
end
294
 
295
always @(posedge sdram_clk) begin
296
   if (wrdatafifo_empty == 1'b1 && wrdatafifo_rd == 1'b1) begin
297
      $display("ERROR:%m WRITE DATA FIFO READ OVERFLOW");
298
   end
299
end
300
// synopsys translate_on
301
 
302
// -------------------------------------------------------------------
303
//  READ DATA FIFO
304
//  ------------------------------------------------------------------
305
wire    rd_eop; // last read indication
306 33 dinesha
 
307
// Read FIFO write generation, when ever SDRAM controller issues the read
308
// valid signal
309 31 dinesha
wire    rddatafifo_wr = sdr_rd_valid;
310
 
311 33 dinesha
// Read FIFO read generation, when ever ack is generated along with read
312
// request.
313
// Note: Ack generation is already accounted the write FIFO Not Empty
314
//       condition
315
wire    rddatafifo_rd = wb_ack_o & !wb_we_i;
316
 
317
//-------------------------------------------------------------------------
318
// Async Read FIFO
319
// This block handles the clock domain change over + Read data from SDRAM
320
// controller to Application layer.
321
//  Note: 
322
//    1. READ DATA FIFO depth is kept small, assuming that Sys-CLock > SDRAM Clock
323
//       READ DATA + EOP
324
//    2. EOP indicate, last transfer of Burst Read Access. use-full for future
325
//       Tag handling per burst
326
//
327
// ------------------------------------------------------------------------
328 40 dinesha
    async_fifo #(.W(dw+1), .DP(4), .WR_FAST(1'b0), .RD_FAST(1'b1) ) u_rddatafifo (
329 31 dinesha
       // Write Path , SDRAM clock domain
330 33 dinesha
          .wr_clk             (sdram_clk          ),
331
          .wr_reset_n         (sdram_resetn       ),
332
          .wr_en              (rddatafifo_wr      ),
333
          .wr_data            ({sdr_last_rd,
334
                                sdr_rd_data}      ),
335
          .afull              (                   ),
336
          .full               (rddatafifo_full    ),
337 31 dinesha
 
338
 
339
       // Read Path , SYS clock domain
340 33 dinesha
          .rd_clk             (wb_clk_i           ),
341
          .rd_reset_n         (!wb_rst_i          ),
342
          .empty              (rddatafifo_empty   ),
343
          .aempty             (                   ),
344
          .rd_en              (rddatafifo_rd      ),
345
          .rd_data            ({rd_eop,
346
                                wb_dat_o}         )
347 31 dinesha
     );
348
 
349
// synopsys translate_off
350
always @(posedge sdram_clk) begin
351
  if (rddatafifo_full == 1'b1 && rddatafifo_wr == 1'b1)  begin
352
     $display("ERROR:%m READ DATA FIFO WRITE OVERFLOW");
353
  end
354
end
355
 
356
always @(posedge wb_clk_i) begin
357
   if (rddatafifo_empty == 1'b1 && rddatafifo_rd == 1'b1) begin
358
      $display("ERROR:%m READ DATA FIFO READ OVERFLOW");
359
   end
360
end
361
// synopsys translate_on
362
 
363
 
364
endmodule

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