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[/] [sdr_ctrl/] [trunk/] [verif/] [run/] [compile.modelsim] - Blame information for rev 72

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Line No. Rev Author Line
1 72 dinesha
#!/bin/csh -f
2 5 dinesha
 
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if(! -e work) then
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   vlib work
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else
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   \rm -rf work
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   vlib work
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endif
9 29 dinesha
if($1 == "core") then # run SDRAM Core level test case
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   vlog -work work +define+$2 -f filelist_core.f
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else # Run SDRAM Top Level test cases
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   vlog -work work +define+$2 -f filelist_top.f
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endif

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