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URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [run/] [read.me] - Blame information for rev 72

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Line No. Rev Author Line
1 5 dinesha
1. To run SDRM 16 Bit Test
2 72 dinesha
   ./run_modelsim top SDR_16BIT
3 5 dinesha
   Note: All the logs will be prefixed with SDR_16BBIT
4 45 dinesha
 
5
2. To run SDRAM top 32 Bit Test
6 72 dinesha
   ./run_modelsim top SDR_32BIT
7 5 dinesha
   Note: All the logs will be prefixed with SDR_32BBIT
8 45 dinesha
 
9
3. To run SDRM 8 Bit Test
10 72 dinesha
   ./run_modelsim top SDR_8BIT
11 45 dinesha
 
12
4. to debug the test in modelsim
13 72 dinesha
   ./compile.modelsim  
14 5 dinesha
   vsim tb_top &
15
 
16 45 dinesha
5. to complile indipendently
17 72 dinesha
   ./compile.modelsim  
18 45 dinesha
 
19
6. To run SDRM 16 Bit Test at SDRAM Core level
20 72 dinesha
   ./run_modelsim core SDR_16BIT
21 45 dinesha
   Note: All the logs will be prefixed with SDR_16BBIT
22
 
23
7. To run SDRAM top 32 Bit Test at SDRAM Core level
24 72 dinesha
   ./run_modelsim core SDR_32BIT
25 45 dinesha
   Note: All the logs will be prefixed with SDR_32BBIT
26
 
27
8. To run SDRM 8 Bit Test  at SDRAM Core level
28 72 dinesha
   ./run_modelsim core SDR_8BIT
29 45 dinesha
 

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