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1 30 dinesha
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////                                                              ////
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////  This file is part of the SDRAM Controller project           ////
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////  http://www.opencores.org/cores/sdr_ctrl/                    ////
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////                                                              ////
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////  Description                                                 ////
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////  SDRAM CTRL definitions.                                     ////
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////                                                              ////
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////  To Do:                                                      ////
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////    nothing                                                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Dinesh Annayya, dinesha@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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// This testbench stand-alone verify the sdram core
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45
`timescale 1ns/1ps
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module tb_core;
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parameter P_SYS  = 10;     //    100MHz
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51
// General
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reg            RESETN;
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reg            sdram_clk;
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initial sdram_clk = 0;
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always #(P_SYS/2) sdram_clk = !sdram_clk;
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parameter      dw              = 32;  // data width
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parameter      tw              = 8;   // tag id width
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parameter      bl              = 5;   // burst_lenght_width
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//-------------------------------------------
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// Application Interface bus
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//-------------------------------------------
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reg                   app_req            ; // Application Request
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reg  [8:0]            app_req_len        ; // Burst Request length
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wire                  app_req_ack        ; // Application Request Ack
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reg [29:0]            app_req_addr       ; // Application Address
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reg                   app_req_wr_n       ; // 1 -> Read, 0 -> Write
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reg [dw-1:0]          app_wr_data        ; // Write Data
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reg [dw/8-1:0]        app_wr_en_n        ; // Write Enable, Active Low
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wire                  app_rd_valid       ; // Read Valid
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wire                  app_last_rd        ; // Last Read Valid
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wire [dw-1:0]         app_rd_data        ; // Read Data
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//--------------------------------------------
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// SDRAM I/F
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//--------------------------------------------
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`ifdef SDR_32BIT
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   wire [31:0]           Dq                 ; // SDRAM Read/Write Data Bus
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   wire [31:0]           sdr_dout           ; // SDRAM Data Out
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   wire [31:0]           pad_sdr_din        ; // SDRAM Data Input
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   wire [3:0]            sdr_den_n          ; // SDRAM Data Enable
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   wire [3:0]            sdr_dqm            ; // SDRAM DATA Mask
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`elsif SDR_16BIT
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   wire [15:0]           Dq                 ; // SDRAM Read/Write Data Bus
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   wire [15:0]           sdr_dout           ; // SDRAM Data Out
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   wire [15:0]           pad_sdr_din        ; // SDRAM Data Input
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   wire [1:0]            sdr_den_n          ; // SDRAM Data Enable
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   wire [1:0]            sdr_dqm            ; // SDRAM DATA Mask
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`else
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   wire [7:0]           Dq                 ; // SDRAM Read/Write Data Bus
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   wire [7:0]           sdr_dout           ; // SDRAM Data Out
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   wire [7:0]           pad_sdr_din        ; // SDRAM Data Input
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   wire [0:0]           sdr_den_n          ; // SDRAM Data Enable
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   wire [0:0]           sdr_dqm            ; // SDRAM DATA Mask
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`endif
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101
wire [1:0]            sdr_ba             ; // SDRAM Bank Select
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wire [11:0]           sdr_addr           ; // SDRAM ADRESS
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wire                  sdr_init_done      ; // SDRAM Init Done
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105
// to fix the sdram interface timing issue
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wire #(2.0) sdram_clk_d = sdram_clk;
107
wire #(1.0) pad_clk     = sdram_clk_d;
108
 
109
`ifdef SDR_32BIT
110
 
111
   sdrc_core #(.SDR_DW(32),.SDR_BW(4)) u_dut(
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`elsif SDR_16BIT
113
   sdrc_core #(.SDR_DW(16),.SDR_BW(2)) u_dut(
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`else  // 8 BIT SDRAM
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   sdrc_core #(.SDR_DW(8),.SDR_BW(1)) u_dut(
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`endif
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      // System
118
          .clk                (sdram_clk          ),
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          .reset_n            (RESETN             ),
120
          .pad_clk            (pad_clk            ),
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`ifdef SDR_32BIT
122
          .sdr_width          (2'b00              ), // 32 BIT SDRAM
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`elsif SDR_16BIT
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          .sdr_width          (2'b01              ), // 16 BIT SDRAM
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`else
126
          .sdr_width          (2'b10              ), // 8 BIT SDRAM
127
`endif
128
          .cfg_colbits        (2'b00              ), // 8 Bit Column Address
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130
 
131
/* Request from app */
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          .app_req            (app_req            ),    // Transfer Request
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          .app_req_addr       (app_req_addr       ),    // SDRAM Address
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          .app_req_addr_mask  (29'h1FFF_FFFF      ),    // Address mask for queue wrap
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          .app_req_len        (app_req_len        ),    // Burst Length (in 16 bit words)
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          .app_req_wrap       (1'b0               ),    // Wrap mode request (xfr_len = 4)
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          .app_req_wr_n       (app_req_wr_n       ),    // 0 => Write request, 1 => read req
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          .app_req_ack        (app_req_ack        ),    // Request has been accepted
139
          .sdr_core_busy_n    (                   ),    // OK to arbitrate next request
140
 
141
          .app_wr_data        (app_wr_data        ),
142
          .app_wr_en_n        (app_wr_en_n        ),
143
          .app_rd_data        (app_rd_data        ),
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          .app_last_rd        (app_last_rd        ),
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          .app_rd_valid       (app_rd_valid       ),
146
          .app_wr_next_req    (app_wr_next_req    ),
147
          .app_req_dma_last   (app_req            ),
148
 
149
/* Interface to SDRAMs */
150
          .sdr_cs_n           (sdr_cs_n           ),
151
          .sdr_cke            (sdr_cke            ),
152
          .sdr_ras_n          (sdr_ras_n          ),
153
          .sdr_cas_n          (sdr_cas_n          ),
154
          .sdr_we_n           (sdr_we_n           ),
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          .sdr_dqm            (sdr_dqm            ),
156
          .sdr_ba             (sdr_ba             ),
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          .sdr_addr           (sdr_addr           ),
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          .pad_sdr_din        (Dq                 ),
159
          .sdr_dout           (sdr_dout           ),
160
          .sdr_den_n          (sdr_den_n          ),
161
 
162
    /* Parameters */
163
          .sdr_init_done      (sdr_init_done      ),
164
          .cfg_req_depth      (2'h2               ),            //how many req. buffer should hold
165
          .cfg_sdr_en         (1'b1               ),
166
          .cfg_sdr_mode_reg   (12'h033            ),
167
          .cfg_sdr_tras_d     (4'h4               ),
168
          .cfg_sdr_trp_d      (4'h2               ),
169
          .cfg_sdr_trcd_d     (4'h2               ),
170
          .cfg_sdr_cas        (3'h3               ),
171
          .cfg_sdr_trcar_d    (4'h7               ),
172
          .cfg_sdr_twr_d      (4'h1               ),
173
          .cfg_sdr_rfsh       (12'hC35            ),
174
          .cfg_sdr_rfmax      (3'h6               )
175
 
176
);
177
 
178
 
179
`ifdef SDR_32BIT
180
  assign Dq[7:0]    = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]   : 8'hZZ;
181
  assign Dq[15:8]   = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8]  : 8'hZZ;
182
  assign Dq[23:16]  = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;
183
  assign Dq[31:24]  = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
184
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
185
          .Dq                 (Dq                 ) ,
186
          .Addr               (sdr_addr           ),
187
          .Ba                 (sdr_ba             ),
188
          .Clk                (sdram_clk_d        ),
189
          .Cke                (sdr_cke            ),
190
          .Cs_n               (sdr_cs_n           ),
191
          .Ras_n              (sdr_ras_n          ),
192
          .Cas_n              (sdr_cas_n          ),
193
          .We_n               (sdr_we_n           ),
194
          .Dqm                (sdr_dqm            )
195
     );
196
 
197
`elsif SDR_16BIT
198
 
199
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
200
assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
201
 
202
   IS42VM16400K u_sdram16 (
203
          .dq                 (Dq                 ),
204
          .addr               (sdr_addr           ),
205
          .ba                 (sdr_ba             ),
206
          .clk                (sdram_clk_d        ),
207
          .cke                (sdr_cke            ),
208
          .csb                (sdr_cs_n           ),
209
          .rasb               (sdr_ras_n          ),
210
          .casb               (sdr_cas_n          ),
211
          .web                (sdr_we_n           ),
212
          .dqm                (sdr_dqm            )
213
    );
214
`else
215
 
216
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
217
 
218
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
219
          .Dq                 (Dq                 ) ,
220
          .Addr               (sdr_addr           ),
221
          .Ba                 (sdr_ba             ),
222
          .Clk                (sdram_clk_d        ),
223
          .Cke                (sdr_cke            ),
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          .Cs_n               (sdr_cs_n           ),
225
          .Ras_n              (sdr_ras_n          ),
226
          .Cas_n              (sdr_cas_n          ),
227
          .We_n               (sdr_we_n           ),
228
          .Dqm                (sdr_dqm            )
229
     );
230
`endif
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232
//--------------------
233
// Write/Read Burst FIFO
234
//--------------------
235
int wrdfifo[$]; // write data fifo
236
int rddfifo[$]; // read data fifo
237
 
238
reg [31:0] read_data;
239
reg [31:0] ErrCnt;
240
int k;
241
reg [31:0] StartAddr;
242
/////////////////////////////////////////////////////////////////////////
243
// Test Case
244
/////////////////////////////////////////////////////////////////////////
245
 
246
initial begin //{
247
  ErrCnt          = 0;
248
   app_req_addr  = 0;
249
   app_wr_data    = 0;
250
   app_wr_en_n    = 4'hF;
251
   app_req_wr_n   = 0;
252
   app_req        = 0;
253
   app_req_len    = 0;
254
 
255
  RESETN    = 1'h1;
256
 
257
 #100
258
  // Applying reset
259
  RESETN    = 1'h0;
260
  #10000;
261
  // Releasing reset
262
  RESETN    = 1'h1;
263
  #1000;
264
  wait(u_dut.sdr_init_done == 1);
265
 
266
  #1000;
267
 
268
  wrdfifo.push_back(32'h11223344);
269
  wrdfifo.push_back(32'h22334455);
270
  wrdfifo.push_back(32'h33445566);
271
  wrdfifo.push_back(32'h44556677);
272
  wrdfifo.push_back(32'h55667788);
273
 
274
  burst_write(32'h40000);
275
 #1000;
276
  burst_read(32'h40000);
277
 
278
 #1000;
279
  burst_write(32'h7000_0000);
280
 #1000;
281
  burst_read(32'h7000_0000);
282
 
283
  for(k=0; k < 20; k++) begin
284
     StartAddr = $random & 32'h07FFFFFF;
285
     burst_write(StartAddr);
286
    #1000;
287
     burst_read(StartAddr);
288
  end
289
 
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291
  #10000;
292
 
293
        $display("###############################");
294
    if(ErrCnt == 0)
295
        $display("STATUS: SDRAM Write/Read TEST PASSED");
296
    else
297
        $display("ERROR:  SDRAM Write/Read TEST FAILED");
298
        $display("###############################");
299
 
300
    $finish;
301
end
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303
task burst_write;
304
input [31:0] Address;
305
int i;
306
begin
307
   @ (negedge sdram_clk);
308
   app_req        = 1;
309
   app_wr_en_n    = 0;
310
   app_req_wr_n   = 1'b0;
311
   $display("Write Address: %x, Burst Size: %d",Address,wrdfifo.size);
312
   app_req_addr  = Address[31:2];
313
   app_req_len    = wrdfifo.size;
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315
   // wait for app_req_ack == 1
316
   do begin
317
       @ (posedge sdram_clk);
318
   end while(app_req_ack == 1'b0);
319
   @ (negedge sdram_clk);
320
   app_req           = 0;
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322
   for(i=0; i < wrdfifo.size; i++) begin
323
      app_wr_data     = wrdfifo[i];
324
 
325
      do begin
326
          @ (posedge sdram_clk);
327
      end while(app_wr_next_req == 1'b0);
328
          @ (negedge sdram_clk);
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330
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,Address,app_wr_data);
331
   end
332
   app_req           = 0;
333
   app_wr_en_n       = 4'hF;
334
end
335
endtask
336
 
337
task burst_read;
338
input [31:0] Address;
339
 
340
int i,j;
341
reg [31:0]   rd_data;
342
begin
343
   @ (negedge sdram_clk);
344
 
345
      app_req        = 1;
346
      app_wr_en_n    = 0;
347
      app_req_wr_n   = 1;
348
      app_req_addr   = Address[29:2];
349
      app_req_len    = wrdfifo.size;
350
      // wait for app_req_ack == 1
351
      do begin
352
          @ (posedge sdram_clk);
353
      end while(app_req_ack == 1'b0);
354
      @ (negedge sdram_clk);
355
      app_req           = 0;
356
 
357
      for(j=0; j < wrdfifo.size; j++) begin
358
         wait(app_rd_valid == 1);
359
         if(app_rd_data !== wrdfifo[j]) begin
360
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,Address+(j*2),app_rd_data,wrdfifo[j]);
361
             ErrCnt = ErrCnt+1;
362
         end else begin
363
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,Address+(j*2),app_rd_data);
364
         end
365
         @ (posedge sdram_clk);
366
         @ (negedge sdram_clk);
367
      end
368
end
369
endtask
370
 
371
 
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endmodule

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