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//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  This file is part of the SDRAM Controller project           ////
////  http://www.opencores.org/cores/sdr_ctrl/                    ////
////                                                              ////
////  Description                                                 ////
////  SDRAM CTRL definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
//   Version  :0.1 - Test Bench automation is improvised with     ////
//             seperate data,address,burst length fifo.           ////
//             Now user can create different write and            ////
//             read sequence                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// This testbench stand-alone verify the sdram core
 
`timescale 1ns/1ps
 
module tb_core;
 
parameter P_SYS  = 10;     //    100MHz
 
// General
reg            RESETN;
reg            sdram_clk;
 
initial sdram_clk = 0;
 
always #(P_SYS/2) sdram_clk = !sdram_clk;
 
parameter      dw              = 32;  // data width
parameter      tw              = 8;   // tag id width
parameter      bl              = 5;   // burst_lenght_width
 
//-------------------------------------------
// Application Interface bus
//-------------------------------------------
reg                   app_req            ; // Application Request
reg  [8:0]            app_req_len        ; // Burst Request length
wire                  app_req_ack        ; // Application Request Ack
reg [29:0]            app_req_addr       ; // Application Address
reg                   app_req_wr_n       ; // 1 -> Read, 0 -> Write
reg [dw-1:0]          app_wr_data        ; // Write Data
reg [dw/8-1:0]        app_wr_en_n        ; // Write Enable, Active Low
wire                  app_rd_valid       ; // Read Valid
wire                  app_last_rd        ; // Last Read Valid
wire [dw-1:0]         app_rd_data        ; // Read Data
 
//--------------------------------------------
// SDRAM I/F
//--------------------------------------------
 
`ifdef SDR_32BIT
   wire [31:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [31:0]           sdr_dout           ; // SDRAM Data Out
   wire [31:0]           pad_sdr_din        ; // SDRAM Data Input
   wire [3:0]            sdr_den_n          ; // SDRAM Data Enable
   wire [3:0]            sdr_dqm            ; // SDRAM DATA Mask
`elsif SDR_16BIT
   wire [15:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [15:0]           sdr_dout           ; // SDRAM Data Out
   wire [15:0]           pad_sdr_din        ; // SDRAM Data Input
   wire [1:0]            sdr_den_n          ; // SDRAM Data Enable
   wire [1:0]            sdr_dqm            ; // SDRAM DATA Mask
`else
   wire [7:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [7:0]           sdr_dout           ; // SDRAM Data Out
   wire [7:0]           pad_sdr_din        ; // SDRAM Data Input
   wire [0:0]           sdr_den_n          ; // SDRAM Data Enable
   wire [0:0]           sdr_dqm            ; // SDRAM DATA Mask
`endif
 
wire [1:0]            sdr_ba             ; // SDRAM Bank Select
wire [11:0]           sdr_addr           ; // SDRAM ADRESS
wire                  sdr_init_done      ; // SDRAM Init Done
 
// to fix the sdram interface timing issue
wire #(2.0) sdram_clk_d = sdram_clk;
wire #(1.0) pad_clk     = sdram_clk_d;
 
`ifdef SDR_32BIT
 
   sdrc_core #(.SDR_DW(32),.SDR_BW(4)) u_dut(
`elsif SDR_16BIT
   sdrc_core #(.SDR_DW(16),.SDR_BW(2)) u_dut(
`else  // 8 BIT SDRAM
   sdrc_core #(.SDR_DW(8),.SDR_BW(1)) u_dut(
`endif
      // System
          .clk                (sdram_clk          ),
          .reset_n            (RESETN             ),
          .pad_clk            (pad_clk            ),
`ifdef SDR_32BIT
          .sdr_width          (2'b00              ), // 32 BIT SDRAM
`elsif SDR_16BIT
          .sdr_width          (2'b01              ), // 16 BIT SDRAM
`else
          .sdr_width          (2'b10              ), // 8 BIT SDRAM
`endif
          .cfg_colbits        (2'b00              ), // 8 Bit Column Address
 
 
/* Request from app */
          .app_req            (app_req            ),    // Transfer Request
          .app_req_addr       (app_req_addr       ),    // SDRAM Address
          .app_req_addr_mask  (29'h1FFF_FFFF      ),    // Address mask for queue wrap
          .app_req_len        (app_req_len        ),    // Burst Length (in 16 bit words)
          .app_req_wrap       (1'b0               ),    // Wrap mode request (xfr_len = 4)
          .app_req_wr_n       (app_req_wr_n       ),    // 0 => Write request, 1 => read req
          .app_req_ack        (app_req_ack        ),    // Request has been accepted
          .sdr_core_busy_n    (                   ),    // OK to arbitrate next request
 
          .app_wr_data        (app_wr_data        ),
          .app_wr_en_n        (app_wr_en_n        ),
          .app_rd_data        (app_rd_data        ),
          .app_last_rd        (app_last_rd        ),
          .app_rd_valid       (app_rd_valid       ),
          .app_wr_next_req    (app_wr_next_req    ),
          .app_req_dma_last   (app_req            ),
 
/* Interface to SDRAMs */
          .sdr_cs_n           (sdr_cs_n           ),
          .sdr_cke            (sdr_cke            ),
          .sdr_ras_n          (sdr_ras_n          ),
          .sdr_cas_n          (sdr_cas_n          ),
          .sdr_we_n           (sdr_we_n           ),
          .sdr_dqm            (sdr_dqm            ),
          .sdr_ba             (sdr_ba             ),
          .sdr_addr           (sdr_addr           ),
          .pad_sdr_din        (Dq                 ),
          .sdr_dout           (sdr_dout           ),
          .sdr_den_n          (sdr_den_n          ),
 
    /* Parameters */
          .sdr_init_done      (sdr_init_done      ),
          .cfg_req_depth      (2'h2               ),            //how many req. buffer should hold
          .cfg_sdr_en         (1'b1               ),
          .cfg_sdr_mode_reg   (12'h033            ),
          .cfg_sdr_tras_d     (4'h4               ),
          .cfg_sdr_trp_d      (4'h2               ),
          .cfg_sdr_trcd_d     (4'h2               ),
          .cfg_sdr_cas        (3'h3               ),
          .cfg_sdr_trcar_d    (4'h7               ),
          .cfg_sdr_twr_d      (4'h1               ),
          .cfg_sdr_rfsh       (12'hC35            ),
          .cfg_sdr_rfmax      (3'h6               )
 
);
 
 
`ifdef SDR_32BIT
  assign Dq[7:0]    = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]   : 8'hZZ;
  assign Dq[15:8]   = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8]  : 8'hZZ;
  assign Dq[23:16]  = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;
  assign Dq[31:24]  = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
          .Dq                 (Dq                 ) ,
          .Addr               (sdr_addr           ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Cas_n              (sdr_cas_n          ),
          .We_n               (sdr_we_n           ),
          .Dqm                (sdr_dqm            )
     );
 
`elsif SDR_16BIT
 
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
 
   IS42VM16400K u_sdram16 (
          .dq                 (Dq                 ),
          .addr               (sdr_addr           ),
          .ba                 (sdr_ba             ),
          .clk                (sdram_clk_d        ),
          .cke                (sdr_cke            ),
          .csb                (sdr_cs_n           ),
          .rasb               (sdr_ras_n          ),
          .casb               (sdr_cas_n          ),
          .web                (sdr_we_n           ),
          .dqm                (sdr_dqm            )
    );
`else
 
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
 
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
          .Dq                 (Dq                 ) ,
          .Addr               (sdr_addr           ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Cas_n              (sdr_cas_n          ),
          .We_n               (sdr_we_n           ),
          .Dqm                (sdr_dqm            )
     );
`endif
 
//--------------------
// data/address/burst length FIFO
//--------------------
int dfifo[$]; // data fifo
int afifo[$]; // address  fifo
int bfifo[$]; // Burst Length fifo
 
reg [31:0] read_data;
reg [31:0] ErrCnt;
int k;
reg [31:0] StartAddr;
/////////////////////////////////////////////////////////////////////////
// Test Case
/////////////////////////////////////////////////////////////////////////
 
initial begin //{
  ErrCnt          = 0;
   app_req_addr  = 0;
   app_wr_data    = 0;
   app_wr_en_n    = 4'hF;
   app_req_wr_n   = 0;
   app_req        = 0;
   app_req_len    = 0;
 
  RESETN    = 1'h1;
 
 #100
  // Applying reset
  RESETN    = 1'h0;
  #10000;
  // Releasing reset
  RESETN    = 1'h1;
  #1000;
  wait(u_dut.sdr_init_done == 1);
 
  #1000;
 
  burst_write(32'h4_0000,6'h4);
 #1000;
  burst_read();
 
 #1000;
  burst_write(32'h0040_0000,6'h5);
 #1000;
  burst_read();
 
  // 4 Write & 4 Read
  burst_write(32'h4_0000,6'h4);
  burst_write(32'h5_0000,6'h5);
  burst_write(32'h6_0000,6'h6);
  burst_write(32'h7_0000,6'h7);
  burst_read();
  burst_read();
  burst_read();
  burst_read();
 
 
  // 2 write and 2 read random
 
  for(k=0; k < 20; k++) begin
     StartAddr = $random & 32'h003FFFFF;
     burst_write(StartAddr,($random & 8'h3f)+1);
 #100;
 
     StartAddr = $random & 32'h003FFFFF;
     burst_write(StartAddr,($random & 8'h3f)+1);
 #100;
     burst_read();
 #100;
     burst_read();
 #100;
  end
 
 
 
  #10000;
 
        $display("###############################");
    if(ErrCnt == 0)
        $display("STATUS: SDRAM Write/Read TEST PASSED");
    else
        $display("ERROR:  SDRAM Write/Read TEST FAILED");
        $display("###############################");
 
    $finish;
end
 
 
task burst_write;
input [31:0] Address;
input [7:0]  bl;
int i;
begin
  afifo.push_back(Address);
  bfifo.push_back(bl);
 
   @ (negedge sdram_clk);
   app_req        = 1;
   app_wr_en_n    = 0;
   app_req_wr_n   = 1'b0;
   app_req_addr   = Address[31:2];
   app_req_len    = bl;
   $display("Write Address: %x, Burst Size: %d",Address,bl);
 
   // wait for app_req_ack == 1
   do begin
       @ (posedge sdram_clk);
   end while(app_req_ack == 1'b0);
   @ (negedge sdram_clk);
   app_req           = 0;
 
   for(i=0; i < bl; i++) begin
      app_wr_data        = $random & 32'hFFFFFFFF;
      dfifo.push_back(app_wr_data);
 
      do begin
          @ (posedge sdram_clk);
      end while(app_wr_next_req == 1'b0);
          @ (negedge sdram_clk);
 
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,Address,app_wr_data);
   end
   app_req           = 0;
   app_wr_en_n       = 4'hF;
 
 
end
endtask
 
task burst_read;
reg [31:0] Address;
reg [7:0]  bl;
 
int i,j;
reg [31:0]   exp_data;
begin
 
   Address = afifo.pop_front();
   bl      = bfifo.pop_front();
 
   app_req        = 1;
   app_wr_en_n    = 0;
   app_req_wr_n   = 1;
   app_req_addr   = Address[29:2];
   app_req_len    = bl;
 
      // wait for app_req_ack == 1
      do begin
          @ (posedge sdram_clk);
      end while(app_req_ack == 1'b0);
      @ (negedge sdram_clk);
      app_req           = 0;
 
      for(j=0; j < bl; j++) begin
         wait(app_rd_valid == 1);
         exp_data        = dfifo.pop_front(); // Exptected Read Data
         if(app_rd_data !== exp_data) begin
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,Address+(j*2),app_rd_data,exp_data);
             ErrCnt = ErrCnt+1;
         end else begin
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,Address+(j*2),app_rd_data);
         end
         @ (posedge sdram_clk);
         @ (negedge sdram_clk);
      end
end
endtask
 
 
endmodule

Line No.	Rev	Author	Line
1	30	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the SDRAM Controller project ////`
5			`//// http://www.opencores.org/cores/sdr_ctrl/ ////`
6			`//// ////`
7			`//// Description ////`
8			`//// SDRAM CTRL definitions. ////`
9			`//// ////`
10			`//// To Do: ////`
11			`//// nothing ////`
12	43	dinesha	`// Version :0.1 - Test Bench automation is improvised with ////`
13			`// seperate data,address,burst length fifo. ////`
14			`// Now user can create different write and ////`
15			`// read sequence ////`
16	30	dinesha	`//// ////`
17			`//// Author(s): ////`
18			`//// - Dinesh Annayya, dinesha@opencores.org ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46
47			`// This testbench stand-alone verify the sdram core`
48
49			`timescale 1ns/1ps
50
51			`module tb_core;`
52
53			`parameter P_SYS = 10; // 100MHz`
54
55			`// General`
56			`reg RESETN;`
57			`reg sdram_clk;`
58
59			`initial sdram_clk = 0;`
60
61			`always #(P_SYS/2) sdram_clk = !sdram_clk;`
62
63			`parameter dw = 32; // data width`
64			`parameter tw = 8; // tag id width`
65			`parameter bl = 5; // burst_lenght_width`
66
67			`//-------------------------------------------`
68			`// Application Interface bus`
69			`//-------------------------------------------`
70			`reg app_req ; // Application Request`
71			`reg [8:0] app_req_len ; // Burst Request length`
72			`wire app_req_ack ; // Application Request Ack`
73			`reg [29:0] app_req_addr ; // Application Address`
74			`reg app_req_wr_n ; // 1 -> Read, 0 -> Write`
75			`reg [dw-1:0] app_wr_data ; // Write Data`
76			`reg [dw/8-1:0] app_wr_en_n ; // Write Enable, Active Low`
77			`wire app_rd_valid ; // Read Valid`
78			`wire app_last_rd ; // Last Read Valid`
79			`wire [dw-1:0] app_rd_data ; // Read Data`
80
81			`//--------------------------------------------`
82			`// SDRAM I/F`
83			`//--------------------------------------------`
84
85			`ifdef SDR_32BIT
86			`wire [31:0] Dq ; // SDRAM Read/Write Data Bus`
87			`wire [31:0] sdr_dout ; // SDRAM Data Out`
88			`wire [31:0] pad_sdr_din ; // SDRAM Data Input`
89			`wire [3:0] sdr_den_n ; // SDRAM Data Enable`
90			`wire [3:0] sdr_dqm ; // SDRAM DATA Mask`
91			`elsif SDR_16BIT
92			`wire [15:0] Dq ; // SDRAM Read/Write Data Bus`
93			`wire [15:0] sdr_dout ; // SDRAM Data Out`
94			`wire [15:0] pad_sdr_din ; // SDRAM Data Input`
95			`wire [1:0] sdr_den_n ; // SDRAM Data Enable`
96			`wire [1:0] sdr_dqm ; // SDRAM DATA Mask`
97			`else
98			`wire [7:0] Dq ; // SDRAM Read/Write Data Bus`
99			`wire [7:0] sdr_dout ; // SDRAM Data Out`
100			`wire [7:0] pad_sdr_din ; // SDRAM Data Input`
101			`wire [0:0] sdr_den_n ; // SDRAM Data Enable`
102			`wire [0:0] sdr_dqm ; // SDRAM DATA Mask`
103			`endif
104
105			`wire [1:0] sdr_ba ; // SDRAM Bank Select`
106			`wire [11:0] sdr_addr ; // SDRAM ADRESS`
107			`wire sdr_init_done ; // SDRAM Init Done`
108
109			`// to fix the sdram interface timing issue`
110			`wire #(2.0) sdram_clk_d = sdram_clk;`
111			`wire #(1.0) pad_clk = sdram_clk_d;`
112
113			`ifdef SDR_32BIT
114
115			`sdrc_core #(.SDR_DW(32),.SDR_BW(4)) u_dut(`
116			`elsif SDR_16BIT
117			`sdrc_core #(.SDR_DW(16),.SDR_BW(2)) u_dut(`
118			`else // 8 BIT SDRAM
119			`sdrc_core #(.SDR_DW(8),.SDR_BW(1)) u_dut(`
120			`endif
121			`// System`
122			`.clk (sdram_clk ),`
123			`.reset_n (RESETN ),`
124			`.pad_clk (pad_clk ),`
125			`ifdef SDR_32BIT
126			`.sdr_width (2'b00 ), // 32 BIT SDRAM`
127			`elsif SDR_16BIT
128			`.sdr_width (2'b01 ), // 16 BIT SDRAM`
129			`else
130			`.sdr_width (2'b10 ), // 8 BIT SDRAM`
131			`endif
132			`.cfg_colbits (2'b00 ), // 8 Bit Column Address`
133
134
135			`/* Request from app */`
136			`.app_req (app_req ), // Transfer Request`
137			`.app_req_addr (app_req_addr ), // SDRAM Address`
138			`.app_req_addr_mask (29'h1FFF_FFFF ), // Address mask for queue wrap`
139			`.app_req_len (app_req_len ), // Burst Length (in 16 bit words)`
140			`.app_req_wrap (1'b0 ), // Wrap mode request (xfr_len = 4)`
141			`.app_req_wr_n (app_req_wr_n ), // 0 => Write request, 1 => read req`
142			`.app_req_ack (app_req_ack ), // Request has been accepted`
143			`.sdr_core_busy_n ( ), // OK to arbitrate next request`
144
145			`.app_wr_data (app_wr_data ),`
146			`.app_wr_en_n (app_wr_en_n ),`
147			`.app_rd_data (app_rd_data ),`
148			`.app_last_rd (app_last_rd ),`
149			`.app_rd_valid (app_rd_valid ),`
150			`.app_wr_next_req (app_wr_next_req ),`
151			`.app_req_dma_last (app_req ),`
152
153			`/* Interface to SDRAMs */`
154			`.sdr_cs_n (sdr_cs_n ),`
155			`.sdr_cke (sdr_cke ),`
156			`.sdr_ras_n (sdr_ras_n ),`
157			`.sdr_cas_n (sdr_cas_n ),`
158			`.sdr_we_n (sdr_we_n ),`
159			`.sdr_dqm (sdr_dqm ),`
160			`.sdr_ba (sdr_ba ),`
161			`.sdr_addr (sdr_addr ),`
162			`.pad_sdr_din (Dq ),`
163			`.sdr_dout (sdr_dout ),`
164			`.sdr_den_n (sdr_den_n ),`
165
166			`/* Parameters */`
167			`.sdr_init_done (sdr_init_done ),`
168			`.cfg_req_depth (2'h2 ), //how many req. buffer should hold`
169			`.cfg_sdr_en (1'b1 ),`
170			`.cfg_sdr_mode_reg (12'h033 ),`
171			`.cfg_sdr_tras_d (4'h4 ),`
172			`.cfg_sdr_trp_d (4'h2 ),`
173			`.cfg_sdr_trcd_d (4'h2 ),`
174			`.cfg_sdr_cas (3'h3 ),`
175			`.cfg_sdr_trcar_d (4'h7 ),`
176			`.cfg_sdr_twr_d (4'h1 ),`
177			`.cfg_sdr_rfsh (12'hC35 ),`
178			`.cfg_sdr_rfmax (3'h6 )`
179
180			`);`
181
182
183			`ifdef SDR_32BIT
184			`assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;`
185			`assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;`
186			`assign Dq[23:16] = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;`
187			`assign Dq[31:24] = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;`
188			`mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (`
189			`.Dq (Dq ) ,`
190			`.Addr (sdr_addr ),`
191			`.Ba (sdr_ba ),`
192			`.Clk (sdram_clk_d ),`
193			`.Cke (sdr_cke ),`
194			`.Cs_n (sdr_cs_n ),`
195			`.Ras_n (sdr_ras_n ),`
196			`.Cas_n (sdr_cas_n ),`
197			`.We_n (sdr_we_n ),`
198			`.Dqm (sdr_dqm )`
199			`);`
200
201			`elsif SDR_16BIT
202
203			`assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;`
204			`assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;`
205
206			`IS42VM16400K u_sdram16 (`
207			`.dq (Dq ),`
208			`.addr (sdr_addr ),`
209			`.ba (sdr_ba ),`
210			`.clk (sdram_clk_d ),`
211			`.cke (sdr_cke ),`
212			`.csb (sdr_cs_n ),`
213			`.rasb (sdr_ras_n ),`
214			`.casb (sdr_cas_n ),`
215			`.web (sdr_we_n ),`
216			`.dqm (sdr_dqm )`
217			`);`
218			`else
219
220			`assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;`
221
222			`mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (`
223			`.Dq (Dq ) ,`
224			`.Addr (sdr_addr ),`
225			`.Ba (sdr_ba ),`
226			`.Clk (sdram_clk_d ),`
227			`.Cke (sdr_cke ),`
228			`.Cs_n (sdr_cs_n ),`
229			`.Ras_n (sdr_ras_n ),`
230			`.Cas_n (sdr_cas_n ),`
231			`.We_n (sdr_we_n ),`
232			`.Dqm (sdr_dqm )`
233			`);`
234			`endif
235
236			`//--------------------`
237	43	dinesha	`// data/address/burst length FIFO`
238	30	dinesha	`//--------------------`
239	43	dinesha	`int dfifo[$]; // data fifo`
240			`int afifo[$]; // address fifo`
241			`int bfifo[$]; // Burst Length fifo`
242	30	dinesha
243			`reg [31:0] read_data;`
244			`reg [31:0] ErrCnt;`
245			`int k;`
246			`reg [31:0] StartAddr;`
247			`/////////////////////////////////////////////////////////////////////////`
248			`// Test Case`
249			`/////////////////////////////////////////////////////////////////////////`
250
251			`initial begin //{`
252			`ErrCnt = 0;`
253			`app_req_addr = 0;`
254			`app_wr_data = 0;`
255			`app_wr_en_n = 4'hF;`
256			`app_req_wr_n = 0;`
257			`app_req = 0;`
258			`app_req_len = 0;`
259
260			`RESETN = 1'h1;`
261
262			`#100`
263			`// Applying reset`
264			`RESETN = 1'h0;`
265			`#10000;`
266			`// Releasing reset`
267			`RESETN = 1'h1;`
268			`#1000;`
269			`wait(u_dut.sdr_init_done == 1);`
270
271			`#1000;`
272
273	43	dinesha	`burst_write(32'h4_0000,6'h4);`
274	30	dinesha	`#1000;`
275	43	dinesha	`burst_read();`
276	30	dinesha
277			`#1000;`
278	43	dinesha	`burst_write(32'h0040_0000,6'h5);`
279	30	dinesha	`#1000;`
280	43	dinesha	`burst_read();`
281	30	dinesha
282	43	dinesha	`// 4 Write & 4 Read`
283			`burst_write(32'h4_0000,6'h4);`
284			`burst_write(32'h5_0000,6'h5);`
285			`burst_write(32'h6_0000,6'h6);`
286			`burst_write(32'h7_0000,6'h7);`
287			`burst_read();`
288			`burst_read();`
289			`burst_read();`
290			`burst_read();`
291
292
293			`// 2 write and 2 read random`
294
295	30	dinesha	`for(k=0; k < 20; k++) begin`
296	43	dinesha	`StartAddr = $random & 32'h003FFFFF;`
297			`burst_write(StartAddr,($random & 8'h3f)+1);`
298			`#100;`
299
300			`StartAddr = $random & 32'h003FFFFF;`
301			`burst_write(StartAddr,($random & 8'h3f)+1);`
302			`#100;`
303			`burst_read();`
304			`#100;`
305			`burst_read();`
306			`#100;`
307	30	dinesha	`end`
308
309
310	43	dinesha
311	30	dinesha	`#10000;`
312
313			`$display("###############################");`
314			`if(ErrCnt == 0)`
315			`$display("STATUS: SDRAM Write/Read TEST PASSED");`
316			`else`
317			`$display("ERROR: SDRAM Write/Read TEST FAILED");`
318			`$display("###############################");`
319
320			`$finish;`
321			`end`
322
323	43	dinesha
324	30	dinesha	`task burst_write;`
325			`input [31:0] Address;`
326	43	dinesha	`input [7:0] bl;`
327	30	dinesha	`int i;`
328			`begin`
329	43	dinesha	`afifo.push_back(Address);`
330			`bfifo.push_back(bl);`
331
332	30	dinesha	`@ (negedge sdram_clk);`
333			`app_req = 1;`
334			`app_wr_en_n = 0;`
335			`app_req_wr_n = 1'b0;`
336	43	dinesha	`app_req_addr = Address[31:2];`
337			`app_req_len = bl;`
338			`$display("Write Address: %x, Burst Size: %d",Address,bl);`
339	30	dinesha
340			`// wait for app_req_ack == 1`
341			`do begin`
342			`@ (posedge sdram_clk);`
343			`end while(app_req_ack == 1'b0);`
344			`@ (negedge sdram_clk);`
345			`app_req = 0;`
346
347	43	dinesha	`for(i=0; i < bl; i++) begin`
348			`app_wr_data = $random & 32'hFFFFFFFF;`
349			`dfifo.push_back(app_wr_data);`
350	30	dinesha
351			`do begin`
352			`@ (posedge sdram_clk);`
353			`end while(app_wr_next_req == 1'b0);`
354			`@ (negedge sdram_clk);`
355
356			`$display("Status: Burst-No: %d Write Address: %x WriteData: %x ",i,Address,app_wr_data);`
357			`end`
358			`app_req = 0;`
359			`app_wr_en_n = 4'hF;`
360	43	dinesha
361
362	30	dinesha	`end`
363			`endtask`
364
365			`task burst_read;`
366	43	dinesha	`reg [31:0] Address;`
367			`reg [7:0] bl;`
368	30	dinesha
369			`int i,j;`
370	43	dinesha	`reg [31:0] exp_data;`
371	30	dinesha	`begin`
372	43	dinesha
373			`Address = afifo.pop_front();`
374			`bl = bfifo.pop_front();`
375	30	dinesha
376	43	dinesha	`app_req = 1;`
377			`app_wr_en_n = 0;`
378			`app_req_wr_n = 1;`
379			`app_req_addr = Address[29:2];`
380			`app_req_len = bl;`
381
382	30	dinesha	`// wait for app_req_ack == 1`
383			`do begin`
384			`@ (posedge sdram_clk);`
385			`end while(app_req_ack == 1'b0);`
386			`@ (negedge sdram_clk);`
387			`app_req = 0;`
388
389	43	dinesha	`for(j=0; j < bl; j++) begin`
390	30	dinesha	`wait(app_rd_valid == 1);`
391	43	dinesha	`exp_data = dfifo.pop_front(); // Exptected Read Data`
392			`if(app_rd_data !== exp_data) begin`
393			`$display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,Address+(j*2),app_rd_data,exp_data);`
394	30	dinesha	`ErrCnt = ErrCnt+1;`
395			`end else begin`
396			`$display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,Address+(j*2),app_rd_data);`
397			`end`
398			`@ (posedge sdram_clk);`
399			`@ (negedge sdram_clk);`
400			`end`
401			`end`
402			`endtask`
403
404
405			`endmodule`

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