OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Blame information for rev 38

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 dinesha
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////                                                              ////
4
////  This file is part of the SDRAM Controller project           ////
5
////  http://www.opencores.org/cores/sdr_ctrl/                    ////
6
////                                                              ////
7
////  Description                                                 ////
8
////  SDRAM CTRL definitions.                                     ////
9
////                                                              ////
10
////  To Do:                                                      ////
11
////    nothing                                                   ////
12
////                                                              ////
13
////  Author(s):                                                  ////
14
////      - Dinesh Annayya, dinesha@opencores.org                 ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
 
44
`timescale 1ns/1ps
45
 
46 24 dinesha
// This testbench verify with SDRAM TOP
47
 
48 8 dinesha
module tb_top;
49
 
50 30 dinesha
parameter P_SYS  = 10;     //    200MHz
51
parameter P_SDR  = 20;     //    100MHz
52 8 dinesha
 
53
// General
54
reg            RESETN;
55
reg            sdram_clk;
56 30 dinesha
reg            sys_clk;
57 8 dinesha
 
58 30 dinesha
initial sys_clk = 0;
59 8 dinesha
initial sdram_clk = 0;
60
 
61 30 dinesha
always #(P_SYS/2) sys_clk = !sys_clk;
62
always #(P_SDR/2) sdram_clk = !sdram_clk;
63 8 dinesha
 
64
parameter      dw              = 32;  // data width
65
parameter      tw              = 8;   // tag id width
66
parameter      bl              = 5;   // burst_lenght_width
67
 
68
//-------------------------------------------
69 30 dinesha
// WISH BONE Interface
70 8 dinesha
//-------------------------------------------
71 30 dinesha
//--------------------------------------
72
// Wish Bone Interface
73
// -------------------------------------
74
reg             wb_stb_i           ;
75
wire            wb_ack_o           ;
76
reg  [29:0]     wb_addr_i          ;
77
reg             wb_we_i            ; // 1 - Write, 0 - Read
78
reg  [dw-1:0]   wb_dat_i           ;
79
reg  [dw/8-1:0] wb_sel_i           ; // Byte enable
80
wire  [dw-1:0]  wb_dat_o           ;
81
reg             wb_cyc_i           ;
82
reg   [2:0]     wb_cti_i           ;
83 8 dinesha
 
84 30 dinesha
 
85
 
86 8 dinesha
//--------------------------------------------
87
// SDRAM I/F
88
//--------------------------------------------
89
 
90
`ifdef SDR_32BIT
91
   wire [31:0]           Dq                 ; // SDRAM Read/Write Data Bus
92
   wire [3:0]            sdr_dqm            ; // SDRAM DATA Mask
93 18 dinesha
`elsif SDR_16BIT
94 8 dinesha
   wire [15:0]           Dq                 ; // SDRAM Read/Write Data Bus
95
   wire [1:0]            sdr_dqm            ; // SDRAM DATA Mask
96 18 dinesha
`else
97
   wire [7:0]           Dq                 ; // SDRAM Read/Write Data Bus
98
   wire [0:0]           sdr_dqm            ; // SDRAM DATA Mask
99 8 dinesha
`endif
100
 
101
wire [1:0]            sdr_ba             ; // SDRAM Bank Select
102
wire [11:0]           sdr_addr           ; // SDRAM ADRESS
103
wire                  sdr_init_done      ; // SDRAM Init Done
104
 
105
// to fix the sdram interface timing issue
106 30 dinesha
wire #(2.0) sdram_clk_d   = sdram_clk;
107 8 dinesha
 
108
`ifdef SDR_32BIT
109
 
110 30 dinesha
   sdrc_top #(.SDR_DW(32),.SDR_BW(4)) u_dut(
111 18 dinesha
`elsif SDR_16BIT
112 30 dinesha
   sdrc_top #(.SDR_DW(16),.SDR_BW(2)) u_dut(
113 18 dinesha
`else  // 8 BIT SDRAM
114 30 dinesha
   sdrc_top #(.SDR_DW(8),.SDR_BW(1)) u_dut(
115 8 dinesha
`endif
116
      // System
117
`ifdef SDR_32BIT
118 38 dinesha
          .cfg_sdr_width      (2'b00              ), // 32 BIT SDRAM
119 18 dinesha
`elsif SDR_16BIT
120 38 dinesha
          .cfg_sdr_width      (2'b01              ), // 16 BIT SDRAM
121 18 dinesha
`else
122 38 dinesha
          .cfg_sdr_width      (2'b10              ), // 8 BIT SDRAM
123 8 dinesha
`endif
124 12 dinesha
          .cfg_colbits        (2'b00              ), // 8 Bit Column Address
125 8 dinesha
 
126 30 dinesha
/* WISH BONE */
127
          .wb_rst_i           (!RESETN            ),
128
          .wb_clk_i           (sys_clk            ),
129 8 dinesha
 
130 30 dinesha
          .wb_stb_i           (wb_stb_i           ),
131
          .wb_ack_o           (wb_ack_o           ),
132
          .wb_addr_i          (wb_addr_i          ),
133
          .wb_we_i            (wb_we_i            ),
134
          .wb_dat_i           (wb_dat_i           ),
135
          .wb_sel_i           (wb_sel_i           ),
136
          .wb_dat_o           (wb_dat_o           ),
137
          .wb_cyc_i           (wb_cyc_i           ),
138
          .wb_cti_i           (wb_cti_i           ),
139 8 dinesha
 
140
/* Interface to SDRAMs */
141 30 dinesha
          .sdram_clk          (sdram_clk          ),
142
          .sdram_resetn       (RESETN             ),
143 8 dinesha
          .sdr_cs_n           (sdr_cs_n           ),
144
          .sdr_cke            (sdr_cke            ),
145
          .sdr_ras_n          (sdr_ras_n          ),
146
          .sdr_cas_n          (sdr_cas_n          ),
147
          .sdr_we_n           (sdr_we_n           ),
148
          .sdr_dqm            (sdr_dqm            ),
149
          .sdr_ba             (sdr_ba             ),
150
          .sdr_addr           (sdr_addr           ),
151 37 dinesha
          .sdr_dq             (Dq                 ),
152 8 dinesha
 
153
    /* Parameters */
154
          .sdr_init_done      (sdr_init_done      ),
155
          .cfg_req_depth      (2'h2               ),            //how many req. buffer should hold
156
          .cfg_sdr_en         (1'b1               ),
157
          .cfg_sdr_mode_reg   (12'h033            ),
158
          .cfg_sdr_tras_d     (4'h4               ),
159
          .cfg_sdr_trp_d      (4'h2               ),
160
          .cfg_sdr_trcd_d     (4'h2               ),
161 22 dinesha
          .cfg_sdr_cas        (3'h3               ),
162 8 dinesha
          .cfg_sdr_trcar_d    (4'h7               ),
163
          .cfg_sdr_twr_d      (4'h1               ),
164
          .cfg_sdr_rfsh       (12'hC35            ),
165
          .cfg_sdr_rfmax      (3'h6               )
166
 
167
);
168
 
169
 
170
`ifdef SDR_32BIT
171
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
172
          .Dq                 (Dq                 ) ,
173
          .Addr               (sdr_addr           ),
174
          .Ba                 (sdr_ba             ),
175 22 dinesha
          .Clk                (sdram_clk_d        ),
176 8 dinesha
          .Cke                (sdr_cke            ),
177
          .Cs_n               (sdr_cs_n           ),
178
          .Ras_n              (sdr_ras_n          ),
179
          .Cas_n              (sdr_cas_n          ),
180
          .We_n               (sdr_we_n           ),
181
          .Dqm                (sdr_dqm            )
182
     );
183
 
184 18 dinesha
`elsif SDR_16BIT
185 8 dinesha
 
186
   IS42VM16400K u_sdram16 (
187
          .dq                 (Dq                 ),
188
          .addr               (sdr_addr           ),
189
          .ba                 (sdr_ba             ),
190 22 dinesha
          .clk                (sdram_clk_d        ),
191 8 dinesha
          .cke                (sdr_cke            ),
192
          .csb                (sdr_cs_n           ),
193
          .rasb               (sdr_ras_n          ),
194
          .casb               (sdr_cas_n          ),
195
          .web                (sdr_we_n           ),
196
          .dqm                (sdr_dqm            )
197
    );
198 18 dinesha
`else
199
 
200
 
201
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
202
          .Dq                 (Dq                 ) ,
203
          .Addr               (sdr_addr           ),
204
          .Ba                 (sdr_ba             ),
205 22 dinesha
          .Clk                (sdram_clk_d        ),
206 18 dinesha
          .Cke                (sdr_cke            ),
207
          .Cs_n               (sdr_cs_n           ),
208
          .Ras_n              (sdr_ras_n          ),
209
          .Cas_n              (sdr_cas_n          ),
210
          .We_n               (sdr_we_n           ),
211
          .Dqm                (sdr_dqm            )
212
     );
213 8 dinesha
`endif
214
 
215
//--------------------
216
// Write/Read Burst FIFO
217
//--------------------
218
int wrdfifo[$]; // write data fifo
219
int rddfifo[$]; // read data fifo
220
 
221
reg [31:0] read_data;
222
reg [31:0] ErrCnt;
223
int k;
224
reg [31:0] StartAddr;
225
/////////////////////////////////////////////////////////////////////////
226
// Test Case
227
/////////////////////////////////////////////////////////////////////////
228
 
229
initial begin //{
230
  ErrCnt          = 0;
231 30 dinesha
   wb_addr_i      = 0;
232
   wb_dat_i      = 0;
233
   wb_sel_i       = 4'h0;
234
   wb_we_i        = 0;
235
   wb_stb_i       = 0;
236
   wb_cyc_i       = 0;
237 8 dinesha
 
238
  RESETN    = 1'h1;
239
 
240
 #100
241
  // Applying reset
242
  RESETN    = 1'h0;
243
  #10000;
244
  // Releasing reset
245
  RESETN    = 1'h1;
246
  #1000;
247
  wait(u_dut.sdr_init_done == 1);
248
 
249
  #1000;
250
 
251
  wrdfifo.push_back(32'h11223344);
252
  wrdfifo.push_back(32'h22334455);
253
  wrdfifo.push_back(32'h33445566);
254
  wrdfifo.push_back(32'h44556677);
255
  wrdfifo.push_back(32'h55667788);
256
 
257
  burst_write(32'h40000);
258
 #1000;
259
  burst_read(32'h40000);
260
 
261
 #1000;
262
  burst_write(32'h7000_0000);
263
 #1000;
264
  burst_read(32'h7000_0000);
265
 
266
  for(k=0; k < 20; k++) begin
267
     StartAddr = $random & 32'h07FFFFFF;
268
     burst_write(StartAddr);
269
    #1000;
270
     burst_read(StartAddr);
271
  end
272
 
273
 
274
  #10000;
275
 
276
        $display("###############################");
277
    if(ErrCnt == 0)
278
        $display("STATUS: SDRAM Write/Read TEST PASSED");
279
    else
280
        $display("ERROR:  SDRAM Write/Read TEST FAILED");
281
        $display("###############################");
282
 
283
    $finish;
284
end
285
 
286
task burst_write;
287
input [31:0] Address;
288
int i;
289
begin
290 30 dinesha
   @ (negedge sys_clk);
291 8 dinesha
   $display("Write Address: %x, Burst Size: %d",Address,wrdfifo.size);
292
 
293
   for(i=0; i < wrdfifo.size; i++) begin
294 30 dinesha
      wb_stb_i        = 1;
295
      wb_cyc_i        = 1;
296
      wb_we_i         = 1;
297
      wb_sel_i        = 4'b1111;
298
      wb_addr_i       = Address[31:2]+i;
299
      wb_dat_i        = wrdfifo[i];
300 8 dinesha
 
301
      do begin
302 30 dinesha
          @ (posedge sys_clk);
303
      end while(wb_ack_o == 1'b0);
304
          @ (negedge sys_clk);
305 8 dinesha
 
306 30 dinesha
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,wb_addr_i,wb_dat_i);
307 8 dinesha
   end
308 30 dinesha
   wb_stb_i           = 0;
309
   wb_cyc_i           = 0;
310 8 dinesha
end
311
endtask
312
 
313
task burst_read;
314
input [31:0] Address;
315
 
316
int i,j;
317
reg [31:0]   rd_data;
318
begin
319 30 dinesha
   @ (negedge sys_clk);
320 8 dinesha
 
321 30 dinesha
      for(j=0; j < wrdfifo.size; j++) begin
322
         wb_stb_i        = 1;
323
         wb_cyc_i        = 1;
324
         wb_we_i         = 0;
325
         wb_addr_i       = Address[31:2]+j;
326 8 dinesha
 
327 30 dinesha
         do begin
328
             @ (posedge sys_clk);
329
         end while(wb_ack_o == 1'b0);
330
         if(wb_dat_o !== wrdfifo[j]) begin
331
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,wb_addr_i,wb_dat_o,wrdfifo[j]);
332 8 dinesha
             ErrCnt = ErrCnt+1;
333
         end else begin
334 30 dinesha
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,wb_addr_i,wb_dat_o);
335 8 dinesha
         end
336
         @ (negedge sdram_clk);
337
      end
338 30 dinesha
   wb_stb_i           = 0;
339
   wb_cyc_i           = 0;
340 8 dinesha
end
341
endtask
342
 
343
 
344
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.