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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Blame information for rev 44

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1 8 dinesha
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////                                                              ////
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////  This file is part of the SDRAM Controller project           ////
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////  http://www.opencores.org/cores/sdr_ctrl/                    ////
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////                                                              ////
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////  Description                                                 ////
8
////  SDRAM CTRL definitions.                                     ////
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////                                                              ////
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////  To Do:                                                      ////
11
////    nothing                                                   ////
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////                                                              ////
13 43 dinesha
//   Version  :0.1 - Test Bench automation is improvised with     ////
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//             seperate data,address,burst length fifo.           ////
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//             Now user can create different write and            ////
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//             read sequence                                      ////
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//                                                                ////
18 8 dinesha
////  Author(s):                                                  ////
19
////      - Dinesh Annayya, dinesha@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
22
////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
31
//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
47
 
48
 
49
`timescale 1ns/1ps
50
 
51 24 dinesha
// This testbench verify with SDRAM TOP
52
 
53 8 dinesha
module tb_top;
54
 
55 30 dinesha
parameter P_SYS  = 10;     //    200MHz
56
parameter P_SDR  = 20;     //    100MHz
57 8 dinesha
 
58
// General
59
reg            RESETN;
60
reg            sdram_clk;
61 30 dinesha
reg            sys_clk;
62 8 dinesha
 
63 30 dinesha
initial sys_clk = 0;
64 8 dinesha
initial sdram_clk = 0;
65
 
66 30 dinesha
always #(P_SYS/2) sys_clk = !sys_clk;
67
always #(P_SDR/2) sdram_clk = !sdram_clk;
68 8 dinesha
 
69
parameter      dw              = 32;  // data width
70
parameter      tw              = 8;   // tag id width
71
parameter      bl              = 5;   // burst_lenght_width
72
 
73
//-------------------------------------------
74 30 dinesha
// WISH BONE Interface
75 8 dinesha
//-------------------------------------------
76 30 dinesha
//--------------------------------------
77
// Wish Bone Interface
78
// -------------------------------------
79
reg             wb_stb_i           ;
80
wire            wb_ack_o           ;
81
reg  [29:0]     wb_addr_i          ;
82
reg             wb_we_i            ; // 1 - Write, 0 - Read
83
reg  [dw-1:0]   wb_dat_i           ;
84
reg  [dw/8-1:0] wb_sel_i           ; // Byte enable
85
wire  [dw-1:0]  wb_dat_o           ;
86
reg             wb_cyc_i           ;
87
reg   [2:0]     wb_cti_i           ;
88 8 dinesha
 
89 30 dinesha
 
90
 
91 8 dinesha
//--------------------------------------------
92
// SDRAM I/F
93
//--------------------------------------------
94
 
95
`ifdef SDR_32BIT
96
   wire [31:0]           Dq                 ; // SDRAM Read/Write Data Bus
97
   wire [3:0]            sdr_dqm            ; // SDRAM DATA Mask
98 18 dinesha
`elsif SDR_16BIT
99 8 dinesha
   wire [15:0]           Dq                 ; // SDRAM Read/Write Data Bus
100
   wire [1:0]            sdr_dqm            ; // SDRAM DATA Mask
101 18 dinesha
`else
102
   wire [7:0]           Dq                 ; // SDRAM Read/Write Data Bus
103
   wire [0:0]           sdr_dqm            ; // SDRAM DATA Mask
104 8 dinesha
`endif
105
 
106
wire [1:0]            sdr_ba             ; // SDRAM Bank Select
107
wire [11:0]           sdr_addr           ; // SDRAM ADRESS
108
wire                  sdr_init_done      ; // SDRAM Init Done
109
 
110
// to fix the sdram interface timing issue
111 30 dinesha
wire #(2.0) sdram_clk_d   = sdram_clk;
112 8 dinesha
 
113
`ifdef SDR_32BIT
114
 
115 30 dinesha
   sdrc_top #(.SDR_DW(32),.SDR_BW(4)) u_dut(
116 18 dinesha
`elsif SDR_16BIT
117 30 dinesha
   sdrc_top #(.SDR_DW(16),.SDR_BW(2)) u_dut(
118 18 dinesha
`else  // 8 BIT SDRAM
119 30 dinesha
   sdrc_top #(.SDR_DW(8),.SDR_BW(1)) u_dut(
120 8 dinesha
`endif
121
      // System
122
`ifdef SDR_32BIT
123 38 dinesha
          .cfg_sdr_width      (2'b00              ), // 32 BIT SDRAM
124 18 dinesha
`elsif SDR_16BIT
125 38 dinesha
          .cfg_sdr_width      (2'b01              ), // 16 BIT SDRAM
126 18 dinesha
`else
127 38 dinesha
          .cfg_sdr_width      (2'b10              ), // 8 BIT SDRAM
128 8 dinesha
`endif
129 12 dinesha
          .cfg_colbits        (2'b00              ), // 8 Bit Column Address
130 8 dinesha
 
131 30 dinesha
/* WISH BONE */
132
          .wb_rst_i           (!RESETN            ),
133
          .wb_clk_i           (sys_clk            ),
134 8 dinesha
 
135 30 dinesha
          .wb_stb_i           (wb_stb_i           ),
136
          .wb_ack_o           (wb_ack_o           ),
137
          .wb_addr_i          (wb_addr_i          ),
138
          .wb_we_i            (wb_we_i            ),
139
          .wb_dat_i           (wb_dat_i           ),
140
          .wb_sel_i           (wb_sel_i           ),
141
          .wb_dat_o           (wb_dat_o           ),
142
          .wb_cyc_i           (wb_cyc_i           ),
143
          .wb_cti_i           (wb_cti_i           ),
144 8 dinesha
 
145
/* Interface to SDRAMs */
146 30 dinesha
          .sdram_clk          (sdram_clk          ),
147
          .sdram_resetn       (RESETN             ),
148 8 dinesha
          .sdr_cs_n           (sdr_cs_n           ),
149
          .sdr_cke            (sdr_cke            ),
150
          .sdr_ras_n          (sdr_ras_n          ),
151
          .sdr_cas_n          (sdr_cas_n          ),
152
          .sdr_we_n           (sdr_we_n           ),
153
          .sdr_dqm            (sdr_dqm            ),
154
          .sdr_ba             (sdr_ba             ),
155
          .sdr_addr           (sdr_addr           ),
156 37 dinesha
          .sdr_dq             (Dq                 ),
157 8 dinesha
 
158
    /* Parameters */
159
          .sdr_init_done      (sdr_init_done      ),
160 44 dinesha
          .cfg_req_depth      (2'h3               ),            //how many req. buffer should hold
161 8 dinesha
          .cfg_sdr_en         (1'b1               ),
162
          .cfg_sdr_mode_reg   (12'h033            ),
163
          .cfg_sdr_tras_d     (4'h4               ),
164
          .cfg_sdr_trp_d      (4'h2               ),
165
          .cfg_sdr_trcd_d     (4'h2               ),
166 22 dinesha
          .cfg_sdr_cas        (3'h3               ),
167 8 dinesha
          .cfg_sdr_trcar_d    (4'h7               ),
168
          .cfg_sdr_twr_d      (4'h1               ),
169
          .cfg_sdr_rfsh       (12'hC35            ),
170
          .cfg_sdr_rfmax      (3'h6               )
171
 
172
);
173
 
174
 
175
`ifdef SDR_32BIT
176
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
177
          .Dq                 (Dq                 ) ,
178
          .Addr               (sdr_addr           ),
179
          .Ba                 (sdr_ba             ),
180 22 dinesha
          .Clk                (sdram_clk_d        ),
181 8 dinesha
          .Cke                (sdr_cke            ),
182
          .Cs_n               (sdr_cs_n           ),
183
          .Ras_n              (sdr_ras_n          ),
184
          .Cas_n              (sdr_cas_n          ),
185
          .We_n               (sdr_we_n           ),
186
          .Dqm                (sdr_dqm            )
187
     );
188
 
189 18 dinesha
`elsif SDR_16BIT
190 8 dinesha
 
191
   IS42VM16400K u_sdram16 (
192
          .dq                 (Dq                 ),
193
          .addr               (sdr_addr           ),
194
          .ba                 (sdr_ba             ),
195 22 dinesha
          .clk                (sdram_clk_d        ),
196 8 dinesha
          .cke                (sdr_cke            ),
197
          .csb                (sdr_cs_n           ),
198
          .rasb               (sdr_ras_n          ),
199
          .casb               (sdr_cas_n          ),
200
          .web                (sdr_we_n           ),
201
          .dqm                (sdr_dqm            )
202
    );
203 18 dinesha
`else
204
 
205
 
206
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
207
          .Dq                 (Dq                 ) ,
208
          .Addr               (sdr_addr           ),
209
          .Ba                 (sdr_ba             ),
210 22 dinesha
          .Clk                (sdram_clk_d        ),
211 18 dinesha
          .Cke                (sdr_cke            ),
212
          .Cs_n               (sdr_cs_n           ),
213
          .Ras_n              (sdr_ras_n          ),
214
          .Cas_n              (sdr_cas_n          ),
215
          .We_n               (sdr_we_n           ),
216
          .Dqm                (sdr_dqm            )
217
     );
218 8 dinesha
`endif
219
 
220
//--------------------
221 43 dinesha
// data/address/burst length FIFO
222 8 dinesha
//--------------------
223 43 dinesha
int dfifo[$]; // data fifo
224
int afifo[$]; // address  fifo
225
int bfifo[$]; // Burst Length fifo
226 8 dinesha
 
227
reg [31:0] read_data;
228
reg [31:0] ErrCnt;
229
int k;
230
reg [31:0] StartAddr;
231
/////////////////////////////////////////////////////////////////////////
232
// Test Case
233
/////////////////////////////////////////////////////////////////////////
234
 
235
initial begin //{
236
  ErrCnt          = 0;
237 30 dinesha
   wb_addr_i      = 0;
238
   wb_dat_i      = 0;
239
   wb_sel_i       = 4'h0;
240
   wb_we_i        = 0;
241
   wb_stb_i       = 0;
242
   wb_cyc_i       = 0;
243 8 dinesha
 
244
  RESETN    = 1'h1;
245
 
246
 #100
247
  // Applying reset
248
  RESETN    = 1'h0;
249
  #10000;
250
  // Releasing reset
251
  RESETN    = 1'h1;
252
  #1000;
253
  wait(u_dut.sdr_init_done == 1);
254
 
255
  #1000;
256
 
257
 
258 43 dinesha
  burst_write(32'h4_0000,8'h4);
259 8 dinesha
 #1000;
260 43 dinesha
  burst_read();
261 8 dinesha
 
262
 #1000;
263 43 dinesha
  burst_write(32'h0040_0000,8'h5);
264 8 dinesha
 #1000;
265 43 dinesha
  burst_read();
266 8 dinesha
 
267 43 dinesha
  // 4 Write & 4 Read
268
  burst_write(32'h4_0000,8'h4);
269
  burst_write(32'h5_0000,8'h5);
270
  burst_write(32'h6_0000,8'h6);
271
  burst_write(32'h7_0000,8'h7);
272
  burst_read();
273
  burst_read();
274
  burst_read();
275
  burst_read();
276
 
277
 
278
  // 2 write and 2 read random
279
 
280 8 dinesha
  for(k=0; k < 20; k++) begin
281 43 dinesha
     StartAddr = $random & 32'h003FFFFF;
282
     burst_write(StartAddr,($random & 8'h3f)+1);
283
 #100;
284
 
285
     StartAddr = $random & 32'h003FFFFF;
286
     burst_write(StartAddr,($random & 8'h3f)+1);
287
 #100;
288
     burst_read();
289
 #100;
290
     burst_read();
291
 #100;
292 8 dinesha
  end
293
 
294
 
295
  #10000;
296
 
297
        $display("###############################");
298
    if(ErrCnt == 0)
299
        $display("STATUS: SDRAM Write/Read TEST PASSED");
300
    else
301
        $display("ERROR:  SDRAM Write/Read TEST FAILED");
302
        $display("###############################");
303
 
304
    $finish;
305
end
306
 
307
task burst_write;
308
input [31:0] Address;
309 43 dinesha
input [7:0]  bl;
310 8 dinesha
int i;
311
begin
312 43 dinesha
  afifo.push_back(Address);
313
  bfifo.push_back(bl);
314
 
315 30 dinesha
   @ (negedge sys_clk);
316 43 dinesha
   $display("Write Address: %x, Burst Size: %d",Address,bl);
317 8 dinesha
 
318 43 dinesha
   for(i=0; i < bl; i++) begin
319 30 dinesha
      wb_stb_i        = 1;
320
      wb_cyc_i        = 1;
321
      wb_we_i         = 1;
322
      wb_sel_i        = 4'b1111;
323
      wb_addr_i       = Address[31:2]+i;
324 43 dinesha
      wb_dat_i        = $random & 32'hFFFFFFFF;
325
      dfifo.push_back(wb_dat_i);
326 8 dinesha
 
327
      do begin
328 30 dinesha
          @ (posedge sys_clk);
329
      end while(wb_ack_o == 1'b0);
330
          @ (negedge sys_clk);
331 8 dinesha
 
332 30 dinesha
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,wb_addr_i,wb_dat_i);
333 8 dinesha
   end
334 30 dinesha
   wb_stb_i           = 0;
335
   wb_cyc_i           = 0;
336 8 dinesha
end
337
endtask
338
 
339
task burst_read;
340 43 dinesha
reg [31:0] Address;
341
reg [7:0]  bl;
342 8 dinesha
 
343
int i,j;
344 43 dinesha
reg [31:0]   exp_data;
345 8 dinesha
begin
346 43 dinesha
 
347
   Address = afifo.pop_front();
348
   bl      = bfifo.pop_front();
349 30 dinesha
   @ (negedge sys_clk);
350 8 dinesha
 
351 43 dinesha
      for(j=0; j < bl; j++) begin
352 30 dinesha
         wb_stb_i        = 1;
353
         wb_cyc_i        = 1;
354
         wb_we_i         = 0;
355
         wb_addr_i       = Address[31:2]+j;
356 8 dinesha
 
357 43 dinesha
         exp_data        = dfifo.pop_front(); // Exptected Read Data
358 30 dinesha
         do begin
359
             @ (posedge sys_clk);
360
         end while(wb_ack_o == 1'b0);
361 43 dinesha
         if(wb_dat_o !== exp_data) begin
362
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,wb_addr_i,wb_dat_o,exp_data);
363 8 dinesha
             ErrCnt = ErrCnt+1;
364
         end else begin
365 30 dinesha
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,wb_addr_i,wb_dat_o);
366 8 dinesha
         end
367
         @ (negedge sdram_clk);
368
      end
369 30 dinesha
   wb_stb_i           = 0;
370
   wb_cyc_i           = 0;
371 8 dinesha
end
372
endtask
373
 
374
 
375
endmodule

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