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                  <P><B><FONT COLOR="#bf0000" SIZE="+2" FACE="Helvetica, Arial">Project
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                  Name: Synchronous-DRAM Controller</FONT></B></P>
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                  <P><B><FONT SIZE="+1">Description</FONT></B></P>
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                  <P>The Synchronous-DRAM controller core allows any asynchronous
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                  bus masters, such as most Intel microcontroller and x86 processors,
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                  to effortlessly interface to a large capacity SDRAM. By default
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                  the core is configured to work with 2-bank x 512-Word x 16-bit
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                  SDRAMs such as NEC uPD451616A, Samsung KM416S1120D, OKIMSM56V16160D.
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                  Easy modifications allows the core to work with different capacity
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                  SDRAMs. Most of the critical parameters are defines in a global
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                  include file allowing easy reconfigurability of the core.</P>
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                  <P>The core handles much of the low level functions such as address
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                  demultiplexing, refresh generation and busy status generation.
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                  In addtion, the non-trivial powerup initialization sequence is
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                  also handled transparently to the host. Flexible refresh generation
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                  permits burst refresh, normal refresh or everything in between.
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                  The SDRAM mode-register can also be reprogrammed on the fly by
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                  the host, although the core uses a default value upon powerup.</P>
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                  <P>The core also includes a set of synthesiable &quot;test&quot;
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                  modules. When enabled for compilation, these test modules becomes
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                  a host to the SDRAM controller and issues a series of read/write
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                  test sequences to the SDRAM. This allows designers working on
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                  FPGA/CPLD platforms to turn the SDRAM controller core into a
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                  &quot;stand-alone&quot; SDRAM tester. </P>
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                  <P>The core has been sucessfully tested with a Samsung KM416S1120D
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                  SDRAM on Altera Flex10K20 FPGA and :Lattice isp3256 CPLD devices
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                  (using the built-in tester).</P>
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                  <P>&nbsp;</P>
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                  <P><CENTER><IMG SRC="intefacing%20block%20diagram.gif" WIDTH="681"
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                  HEIGHT="348" ALIGN="BOTTOM" BORDER="0" NATURALSIZEFLAG="0"></CENTER></P>
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                  <P>Current Status:</P>
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                  <UL>
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                    <LI>Initial release available in CVS for download.
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                    <LI>Working on the specification documentation.
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                  </UL>
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                  <P>Maintainer(s):</P>
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                  <UL>
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                    <P>SDRAM development team
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                  </UL>
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                  <P>Author(s):</P>
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                  <UL>
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                    <P>SDRAM development team
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                  </UL>
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                  <P>Mailing-list:</P>
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                    <P><A HREF="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</ul></A>
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