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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: sdspi.v
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//
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// Project: SD-Card controller, using a shared SPI interface
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//
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// Purpose:
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`define SDSPI_CMD_ADDRESS 2'h0
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`define SDSPI_DAT_ADDRESS 2'h1
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`define SDSPI_FIFO_A_ADDR 2'h2
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`define SDSPI_FIFO_B_ADDR 2'h3
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//
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// `define SDSPI_CMD_ID 3'h0
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// `define SDSPI_CMD_A1 3'h1
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// `define SDSPI_CMD_A2 3'h2
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// `define SDSPI_CMD_A3 3'h3
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// `define SDSPI_CMD_A4 3'h4
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// `define SDSPI_CMD_CRC 3'h5
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// `define SDSPI_CMD_FIFO 3'h6
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// `define SDSPI_CMD_WAIT 3'h7
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//
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`define SDSPI_EXPECT_R1 2'b00
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`define SDSPI_EXPECT_R1B 2'b01
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`define SDSPI_EXPECT_R3 2'b10
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//
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`define SDSPI_RSP_NONE 3'h0 // No response yet from device
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`define SDSPI_RSP_BSYWAIT 3'h1 // R1b, wait for device to send nonzero
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`define SDSPI_RSP_GETWORD 3'h2 // Get 32-bit data word from device
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`define SDSPI_RSP_GETTOKEN 3'h4 // Write to device, read from FIFO, wait for completion token
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`define SDSPI_RSP_WAIT_WHILE_BUSY 3'h5 // Read from device
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`define SDSPI_RSP_RDCOMPLETE 3'h6
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`define SDSPI_RSP_WRITING 3'h7 // Read from device, write into FIFO
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//
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module sdspi(i_clk,
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// Wishbone interface
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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// SDCard interface
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o_cs_n, o_sck, o_mosi, i_miso,
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// Our interrupt
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o_int,
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// And whether or not we own the bus
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i_bus_grant,
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// And some wires for debugging it all
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o_debug);
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parameter LGFIFOLN = 7;
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input i_clk;
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//
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [1:0] i_wb_addr;
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input [31:0] i_wb_data;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output reg [31:0] o_wb_data;
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//
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output wire o_cs_n, o_sck, o_mosi;
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input i_miso;
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// The interrupt
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output reg o_int;
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// .. and whether or not we can use the SPI port
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input i_bus_grant;
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//
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output wire [31:0] o_debug;
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//
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// Some WB simplifications:
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//
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reg r_cmd_busy;
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wire wb_stb, write_stb, cmd_stb; // read_stb
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assign wb_stb = ((i_wb_cyc)&&(i_wb_stb)&&(~o_wb_stall));
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assign write_stb = ((wb_stb)&&( i_wb_we));
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// assign read_stb = ((wb_stb)&&(~i_wb_we));
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assign cmd_stb = (~r_cmd_busy)&&(write_stb)
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&&(i_wb_addr==`SDSPI_CMD_ADDRESS);
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//
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// Access to our lower-level SDSPI driver, the one that actually
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// uses/sets the SPI ports
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//
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reg [6:0] r_sdspi_clk;
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reg ll_cmd_stb;
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reg [7:0] ll_cmd_dat;
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wire ll_out_stb, ll_idle;
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wire [7:0] ll_out_dat;
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llsdspi lowlevel(i_clk, r_sdspi_clk, r_cmd_busy, ll_cmd_stb, ll_cmd_dat,
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o_cs_n, o_sck, o_mosi, i_miso,
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ll_out_stb, ll_out_dat, ll_idle,
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i_bus_grant);
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// CRC
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reg r_cmd_crc_stb;
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wire [7:0] cmd_crc;
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// State machine
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reg [2:0] r_cmd_state, r_rsp_state;
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// Current status, beyond state
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reg r_have_resp, r_use_fifo, r_fifo_wr,
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ll_fifo_rd_complete, ll_fifo_wr_complete,
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r_fifo_id,
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ll_fifo_wr, ll_fifo_rd,
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r_have_data_response_token,
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r_have_start_token;
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reg [7:0] fifo_byte;
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reg [7:0] r_last_r_one;
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//
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reg [31:0] r_data_reg;
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reg [1:0] r_data_fil, r_cmd_resp;
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//
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//
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wire need_reset;
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reg r_cmd_err;
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reg r_cmd_sent;
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reg [31:0] fifo_a_reg, fifo_b_reg;
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//
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reg q_busy;
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//
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reg [7:0] fifo_a_mem[((1<<(LGFIFOLN+2))-1):0];
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reg [7:0] fifo_b_mem[((1<<(LGFIFOLN+2))-1):0];
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reg [(LGFIFOLN-1):0] fifo_wb_addr;
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reg [(LGFIFOLN+1):0] rd_fifo_sd_addr;
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reg [(LGFIFOLN+1):0] wr_fifo_sd_addr;
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//
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reg [(LGFIFOLN+1):0] ll_fifo_addr;
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//
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reg fifo_crc_err;
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reg [1:0] ll_fifo_wr_state;
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reg [7:0] fifo_a_byte, fifo_b_byte;
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//
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reg [2:0] ll_fifo_pkt_state;
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reg fifo_rd_crc_stb, fifo_wr_crc_stb;
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//
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reg [3:0] fifo_rd_crc_count, fifo_wr_crc_count;
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reg [15:0] fifo_rd_crc_reg, fifo_wr_crc_reg;
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//
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reg [3:0] r_cmd_crc_cnt;
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reg [7:0] r_cmd_crc;
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//
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reg r_cmd_crc_ff;
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//
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reg [3:0] r_lgblklen;
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wire [3:0] max_lgblklen;
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assign max_lgblklen = LGFIFOLN;
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//
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reg [25:0] r_watchdog;
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reg r_watchdog_err;
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reg pre_cmd_state;
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initial r_cmd_busy = 1'b0;
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initial r_data_reg = 32'h00;
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initial r_last_r_one = 8'hff;
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initial ll_cmd_stb = 1'b0;
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initial ll_fifo_rd = 1'b0;
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initial ll_fifo_wr = 1'b0;
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initial r_rsp_state = 3'h0;
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initial r_cmd_state = 3'h0;
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initial r_use_fifo = 1'b0;
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initial r_data_fil = 2'b00;
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initial r_lgblklen = LGFIFOLN;
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initial r_cmd_err = 1'b0;
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always @(posedge i_clk)
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begin
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if (~ll_cmd_stb)
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begin
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r_have_resp <= 1'b0;
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ll_fifo_wr <= 1'b0;
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ll_fifo_rd <= 1'b0;
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// r_rsp_state <= 3'h0;
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r_cmd_state <= 3'h0;
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r_use_fifo <= 1'b0;
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r_data_fil <= 2'b00;
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r_cmd_resp <= `SDSPI_EXPECT_R1;
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end
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r_cmd_crc_stb <= 1'b0;
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if (pre_cmd_state)
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begin // While we are actively sending data, and clocking the
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// interface, do:
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//
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// Here we use the transmit command state, or
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// r_cmd_state, to determine where we are at in this
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// process, and we use (ll_cmd_stb)&&(ll_idle) to
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// determine that we have sent a byte. ll_cmd_dat is
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// set here as well--it's the byte we wish to transmit.
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if (r_cmd_state == 3'h0)
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begin
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r_cmd_state <= r_cmd_state + 3'h1;
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ll_cmd_dat <= r_data_reg[31:24];
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r_cmd_crc_stb <= 1'b1;
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end else if (r_cmd_state == 3'h1)
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begin
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r_cmd_state <= r_cmd_state + 3'h1;
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ll_cmd_dat <= r_data_reg[23:16];
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r_cmd_crc_stb <= 1'b1;
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end else if (r_cmd_state == 3'h2)
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begin
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r_cmd_state <= r_cmd_state + 3'h1;
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ll_cmd_dat <= r_data_reg[15:8];
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r_cmd_crc_stb <= 1'b1;
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end else if (r_cmd_state == 3'h3)
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begin
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r_cmd_state <= r_cmd_state + 3'h1;
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ll_cmd_dat <= r_data_reg[7:0];
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r_cmd_crc_stb <= 1'b1;
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end else if (r_cmd_state == 3'h4)
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begin
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r_cmd_state <= r_cmd_state + 3'h1;
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ll_cmd_dat <= cmd_crc;
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end else if (r_cmd_state == 3'h5)
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begin
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ll_cmd_dat <= 8'hff;
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if (r_have_resp)
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begin
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if (r_use_fifo)
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r_cmd_state <= r_cmd_state + 3'h1;
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else
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r_cmd_state <= r_cmd_state + 3'h2;
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ll_fifo_rd <= (r_use_fifo)&&(r_fifo_wr);
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if ((r_use_fifo)&&(r_fifo_wr))
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ll_cmd_dat <= 8'hfe;
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end
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end else if (r_cmd_state == 3'h6)
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begin
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ll_cmd_dat <= 8'hff;
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if (ll_fifo_rd_complete)
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begin // If we've finished reading from the
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// FIFO, then move on
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r_cmd_state <= r_cmd_state + 3'h1;
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ll_fifo_rd <= 1'b0;
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end else if (ll_fifo_rd)
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ll_cmd_dat <= fifo_byte;
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end else // if (r_cmd_state == 7)
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ll_cmd_dat <= 8'hff;
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// Here we handle the receive portion of the interface.
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// Note that the IF begins with an if of ll_out_stb.
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// That is, if a byte is ready from the lower level.
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//
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// Here we depend upon r_cmd_resp, the response we are
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// expecting from the SDCard, and r_rsp_state, the
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// state machine for where we are at receive what we
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// are expecting.
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if (pre_rsp_state)
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begin
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if (r_rsp_state == `SDSPI_RSP_NONE)
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begin // Waiting on R1
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if (~ll_out_dat[7])
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begin
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r_last_r_one <= ll_out_dat;
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if (r_cmd_resp == `SDSPI_EXPECT_R1)
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begin // Expecting R1 alone
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r_have_resp <= 1'b1;
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ll_cmd_stb <= (r_use_fifo);
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r_data_reg <= 32'hffffffff;
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ll_fifo_wr<=(r_use_fifo)&&(~r_fifo_wr);
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end else if (r_cmd_resp == `SDSPI_EXPECT_R1B)
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begin // Go wait on R1b
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r_data_reg <= 32'hffffffff;
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end // else wait on 32-bit rsp
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end
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end else if (r_rsp_state == `SDSPI_RSP_BSYWAIT)
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begin // Waiting on R1b, have R1
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if (nonzero_out)
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r_have_resp <= 1'b1;
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ll_cmd_stb <= (r_use_fifo);
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end else if (r_rsp_state == `SDSPI_RSP_GETWORD)
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begin // Have R1, waiting on all of R2/R3/R7
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r_data_reg <= { r_data_reg[23:0], ll_out_dat };
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r_data_fil <= r_data_fil+2'b01;
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if (r_data_fil == 2'b11)
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begin
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ll_cmd_stb <= (r_use_fifo);
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// r_rsp_state <= 3'h3;
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end
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|
end else if (r_rsp_state == `SDSPI_RSP_WAIT_WHILE_BUSY)
|
| 307 |
|
|
begin // Wait while device is busy writing
|
| 308 |
|
|
// if (nonzero_out)
|
| 309 |
|
|
// begin
|
| 310 |
|
|
// r_data_reg[31:8] <= 24'h00;
|
| 311 |
|
|
// r_data_reg[7:0] <= ll_out_dat;
|
| 312 |
|
|
// // r_rsp_state <= 3'h6;
|
| 313 |
|
|
// end
|
| 314 |
|
|
;
|
| 315 |
|
|
end else if (r_rsp_state == `SDSPI_RSP_RDCOMPLETE)
|
| 316 |
|
|
begin // Block write command has completed
|
| 317 |
|
|
ll_cmd_stb <= 1'b0;
|
| 318 |
|
|
end else if (r_rsp_state == `SDSPI_RSP_WRITING)
|
| 319 |
|
|
begin // We are reading from the device into
|
| 320 |
|
|
// our FIFO
|
| 321 |
|
|
if ((ll_fifo_wr_complete)
|
| 322 |
|
|
// Or ... we receive an error
|
| 323 |
|
|
||((~r_have_start_token)
|
| 324 |
|
|
&&(~ll_out_dat[4])
|
| 325 |
|
|
&&(ll_out_dat[0])))
|
| 326 |
|
|
begin
|
| 327 |
|
|
ll_fifo_wr <= 1'b0;
|
| 328 |
|
|
ll_cmd_stb <= 1'b0;
|
| 329 |
|
|
end
|
| 330 |
|
|
end
|
| 331 |
|
|
end
|
| 332 |
|
|
|
| 333 |
|
|
if (r_watchdog_err)
|
| 334 |
|
|
ll_cmd_stb <= 1'b0;
|
| 335 |
|
|
r_cmd_err<= (r_cmd_err)|(fifo_crc_err)|(r_watchdog_err);
|
| 336 |
|
|
end else if (r_cmd_busy)
|
| 337 |
|
|
begin
|
| 338 |
|
|
r_cmd_busy <= (ll_cmd_stb)||(~ll_idle);
|
| 339 |
|
|
end else if (cmd_stb)
|
| 340 |
|
|
begin // Command write
|
| 341 |
|
|
// Clear the error on any write, whether a commanding
|
| 342 |
|
|
// one or not. -- provided the user requests clearing
|
| 343 |
|
|
// it (by setting the bit high)
|
| 344 |
|
|
r_cmd_err <= (r_cmd_err)&&(~i_wb_data[15]);
|
| 345 |
|
|
// In a similar fashion, we can switch fifos even if
|
| 346 |
|
|
// not in the middle of a command
|
| 347 |
|
|
r_fifo_id <= i_wb_data[12];
|
| 348 |
|
|
//
|
| 349 |
|
|
// Doesn't matter what this is set to as long as we
|
| 350 |
|
|
// aren't busy, so we can set it irrelevantly here.
|
| 351 |
|
|
ll_cmd_dat <= i_wb_data[7:0];
|
| 352 |
|
|
//
|
| 353 |
|
|
// Note that we only issue a write upon receiving a
|
| 354 |
|
|
// valid command. Such a command is 8 bits, and must
|
| 355 |
|
|
// start with its high order bits set to zero and one.
|
| 356 |
|
|
// Hence ... we test for that here.
|
| 357 |
|
|
if (i_wb_data[7:6] == 2'b01)
|
| 358 |
|
|
begin // Issue a command
|
| 359 |
|
|
//
|
| 360 |
|
|
r_cmd_busy <= 1'b1;
|
| 361 |
|
|
//
|
| 362 |
|
|
ll_cmd_stb <= 1'b1;
|
| 363 |
|
|
r_cmd_resp <= i_wb_data[9:8];
|
| 364 |
|
|
//
|
| 365 |
|
|
r_cmd_crc_stb <= 1'b1;
|
| 366 |
|
|
//
|
| 367 |
|
|
r_fifo_wr <= i_wb_data[10];
|
| 368 |
|
|
r_use_fifo <= i_wb_data[11];
|
| 369 |
|
|
//
|
| 370 |
|
|
end else if (i_wb_data[7])
|
| 371 |
|
|
// If, on the other hand, the command was invalid,
|
| 372 |
|
|
// then it must have been an attempt to read our
|
| 373 |
|
|
// internal configuration. So we'll place that on
|
| 374 |
|
|
// our data register.
|
| 375 |
|
|
r_data_reg <= { 8'h00,
|
| 376 |
|
|
4'h0, max_lgblklen,
|
| 377 |
|
|
4'h0, r_lgblklen, 1'b0, r_sdspi_clk };
|
| 378 |
|
|
end else if ((write_stb)&&(i_wb_addr == `SDSPI_DAT_ADDRESS))
|
| 379 |
|
|
begin // Data write
|
| 380 |
|
|
r_data_reg <= i_wb_data;
|
| 381 |
|
|
end
|
| 382 |
|
|
end
|
| 383 |
|
|
|
| 384 |
|
|
always @(posedge i_clk)
|
| 385 |
|
|
pre_cmd_state <= (ll_cmd_stb)&&(ll_idle);
|
| 386 |
|
|
|
| 387 |
|
|
reg ready_for_response_token;
|
| 388 |
|
|
always @(posedge i_clk)
|
| 389 |
|
|
if (~r_cmd_busy)
|
| 390 |
|
|
ready_for_response_token <= 1'b0;
|
| 391 |
|
|
else if (ll_fifo_rd)
|
| 392 |
|
|
ready_for_response_token <= 1'b1;
|
| 393 |
|
|
always @(posedge i_clk)
|
| 394 |
|
|
if (~r_cmd_busy)
|
| 395 |
|
|
r_have_data_response_token <= 1'b0;
|
| 396 |
|
|
else if ((ll_out_stb)&&(ready_for_response_token)&&(~ll_out_dat[4]))
|
| 397 |
|
|
r_have_data_response_token <= 1'b1;
|
| 398 |
|
|
|
| 399 |
|
|
reg [2:0] second_rsp_state;
|
| 400 |
|
|
always @(posedge i_clk)
|
| 401 |
|
|
if((r_cmd_resp == `SDSPI_EXPECT_R1)&&(r_use_fifo)&&(r_fifo_wr))
|
| 402 |
|
|
second_rsp_state <= `SDSPI_RSP_GETTOKEN;
|
| 403 |
|
|
else if (r_cmd_resp == `SDSPI_EXPECT_R1)
|
| 404 |
|
|
second_rsp_state <= `SDSPI_RSP_WRITING;
|
| 405 |
|
|
else if (r_cmd_resp == `SDSPI_EXPECT_R1B)
|
| 406 |
|
|
second_rsp_state <= `SDSPI_RSP_BSYWAIT;
|
| 407 |
|
|
else
|
| 408 |
|
|
second_rsp_state <= `SDSPI_RSP_GETWORD;
|
| 409 |
|
|
|
| 410 |
|
|
reg pre_rsp_state, nonzero_out;
|
| 411 |
|
|
always @(posedge i_clk)
|
| 412 |
|
|
if (ll_out_stb)
|
| 413 |
|
|
nonzero_out <= (|ll_out_dat);
|
| 414 |
|
|
always @(posedge i_clk)
|
| 415 |
|
|
pre_rsp_state <= (ll_out_stb)&&(r_cmd_sent);
|
| 416 |
|
|
|
| 417 |
|
|
// Each bit depends upon 8 bits of input
|
| 418 |
|
|
initial r_rsp_state = 3'h0;
|
| 419 |
|
|
always @(posedge i_clk)
|
| 420 |
|
|
if (~r_cmd_sent)
|
| 421 |
|
|
r_rsp_state <= 3'h0;
|
| 422 |
|
|
else if (pre_rsp_state)
|
| 423 |
|
|
begin
|
| 424 |
|
|
if ((r_rsp_state == `SDSPI_RSP_NONE)&&(~ll_out_dat[7]))
|
| 425 |
|
|
begin
|
| 426 |
|
|
r_rsp_state <= second_rsp_state;
|
| 427 |
|
|
end else if (r_rsp_state == `SDSPI_RSP_BSYWAIT)
|
| 428 |
|
|
begin // Waiting on R1b, have R1
|
| 429 |
|
|
// R1b never uses the FIFO
|
| 430 |
|
|
if (nonzero_out)
|
| 431 |
|
|
r_rsp_state <= 3'h6;
|
| 432 |
|
|
end else if (r_rsp_state == `SDSPI_RSP_GETWORD)
|
| 433 |
|
|
begin // Have R1, waiting on all of R2/R3/R7
|
| 434 |
|
|
if (r_data_fil == 2'b11)
|
| 435 |
|
|
r_rsp_state <= `SDSPI_RSP_RDCOMPLETE;
|
| 436 |
|
|
end else if (r_rsp_state == `SDSPI_RSP_GETTOKEN)
|
| 437 |
|
|
begin // Wait on data token response
|
| 438 |
|
|
if (r_have_data_response_token)
|
| 439 |
|
|
r_rsp_state <= `SDSPI_RSP_WAIT_WHILE_BUSY;
|
| 440 |
|
|
end else if (r_rsp_state == `SDSPI_RSP_WAIT_WHILE_BUSY)
|
| 441 |
|
|
begin // Wait while device is busy writing
|
| 442 |
|
|
if (nonzero_out)
|
| 443 |
|
|
r_rsp_state <= `SDSPI_RSP_RDCOMPLETE;
|
| 444 |
|
|
end
|
| 445 |
|
|
//else if (r_rsp_state == 3'h6)
|
| 446 |
|
|
//begin // Block write command has completed
|
| 447 |
|
|
// // ll_cmd_stb <= 1'b0;
|
| 448 |
|
|
// end else if (r_rsp_state == 3'h7)
|
| 449 |
|
|
// begin // We are reading from the device into
|
| 450 |
|
|
// // our FIFO
|
| 451 |
|
|
// end
|
| 452 |
|
|
end
|
| 453 |
|
|
|
| 454 |
|
|
always @(posedge i_clk)
|
| 455 |
|
|
r_cmd_sent <= (ll_cmd_stb)&&(r_cmd_state >= 3'h5);
|
| 456 |
|
|
|
| 457 |
|
|
// initial r_sdspi_clk = 6'h3c;
|
| 458 |
|
|
initial r_sdspi_clk = 7'h63;
|
| 459 |
|
|
always @(posedge i_clk)
|
| 460 |
|
|
begin
|
| 461 |
|
|
// Update our internal configuration parameters, unconnected
|
| 462 |
|
|
// with the card. These include the speed of the interface,
|
| 463 |
|
|
// and the size of the block length to expect as part of a FIFO
|
| 464 |
|
|
// command.
|
| 465 |
|
|
if ((cmd_stb)&&(i_wb_data[7:6]==2'b11)&&(~r_data_reg[7])
|
| 466 |
|
|
&&(r_data_reg[15:12]==4'h00))
|
| 467 |
|
|
begin
|
| 468 |
|
|
if (|r_data_reg[6:0])
|
| 469 |
|
|
r_sdspi_clk <= r_data_reg[6:0];
|
| 470 |
|
|
if (|r_data_reg[11:8])
|
| 471 |
|
|
r_lgblklen <= r_data_reg[11:8];
|
| 472 |
|
|
end if (r_lgblklen > max_lgblklen)
|
| 473 |
|
|
r_lgblklen <= max_lgblklen;
|
| 474 |
|
|
end
|
| 475 |
|
|
|
| 476 |
|
|
assign need_reset = 1'b0;
|
| 477 |
|
|
always @(posedge i_clk)
|
| 478 |
|
|
case(i_wb_addr)
|
| 479 |
|
|
`SDSPI_CMD_ADDRESS:
|
| 480 |
|
|
o_wb_data <= { need_reset, 11'h00,
|
| 481 |
|
|
3'h0, fifo_crc_err,
|
| 482 |
|
|
r_cmd_err, r_cmd_busy, 1'b0, r_fifo_id,
|
| 483 |
|
|
r_use_fifo, r_fifo_wr, r_cmd_resp,
|
| 484 |
|
|
r_last_r_one };
|
| 485 |
|
|
`SDSPI_DAT_ADDRESS:
|
| 486 |
|
|
o_wb_data <= r_data_reg;
|
| 487 |
|
|
`SDSPI_FIFO_A_ADDR:
|
| 488 |
|
|
o_wb_data <= fifo_a_reg;
|
| 489 |
|
|
`SDSPI_FIFO_B_ADDR:
|
| 490 |
|
|
o_wb_data <= fifo_b_reg;
|
| 491 |
|
|
endcase
|
| 492 |
|
|
|
| 493 |
|
|
always @(posedge i_clk)
|
| 494 |
|
|
o_wb_ack <= wb_stb;
|
| 495 |
|
|
|
| 496 |
|
|
initial q_busy = 1'b1;
|
| 497 |
|
|
always @(posedge i_clk)
|
| 498 |
|
|
q_busy <= r_cmd_busy;
|
| 499 |
|
|
always @(posedge i_clk)
|
| 500 |
|
|
o_int <= (~r_cmd_busy)&&(q_busy);
|
| 501 |
|
|
|
| 502 |
|
|
assign o_wb_stall = 1'b0;
|
| 503 |
|
|
|
| 504 |
|
|
//
|
| 505 |
|
|
// Let's work with our FIFO memory here ...
|
| 506 |
|
|
//
|
| 507 |
|
|
//
|
| 508 |
|
|
always @(posedge i_clk)
|
| 509 |
|
|
begin
|
| 510 |
|
|
if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS))
|
| 511 |
|
|
begin // Command write
|
| 512 |
|
|
// Clear the read/write address
|
| 513 |
|
|
fifo_wb_addr <= {(LGFIFOLN){1'b0}};
|
| 514 |
|
|
end else if ((wb_stb)&&(i_wb_addr[1]))
|
| 515 |
|
|
begin // On read or write, of either FIFO,
|
| 516 |
|
|
// we increase our pointer
|
| 517 |
|
|
fifo_wb_addr <= fifo_wb_addr + 1;
|
| 518 |
|
|
// And let ourselves know we need to update ourselves
|
| 519 |
|
|
// on the next clock
|
| 520 |
|
|
end
|
| 521 |
|
|
end
|
| 522 |
|
|
|
| 523 |
|
|
// Prepare reading of the FIFO for the WB bus read
|
| 524 |
|
|
// Memory read #1
|
| 525 |
|
|
always @(posedge i_clk)
|
| 526 |
|
|
begin
|
| 527 |
|
|
fifo_a_reg <= {
|
| 528 |
|
|
fifo_a_mem[{ fifo_wb_addr, 2'b00 }],
|
| 529 |
|
|
fifo_a_mem[{ fifo_wb_addr, 2'b01 }],
|
| 530 |
|
|
fifo_a_mem[{ fifo_wb_addr, 2'b10 }],
|
| 531 |
|
|
fifo_a_mem[{ fifo_wb_addr, 2'b11 }] };
|
| 532 |
|
|
fifo_b_reg <= {
|
| 533 |
|
|
fifo_b_mem[{ fifo_wb_addr, 2'b00 }],
|
| 534 |
|
|
fifo_b_mem[{ fifo_wb_addr, 2'b01 }],
|
| 535 |
|
|
fifo_b_mem[{ fifo_wb_addr, 2'b10 }],
|
| 536 |
|
|
fifo_b_mem[{ fifo_wb_addr, 2'b11 }] };
|
| 537 |
|
|
end
|
| 538 |
|
|
|
| 539 |
|
|
// Okay, now ... writing our FIFO ...
|
| 540 |
|
|
reg pre_fifo_addr_inc_rd;
|
| 541 |
|
|
reg pre_fifo_addr_inc_wr;
|
| 542 |
|
|
initial pre_fifo_addr_inc_rd = 1'b0;
|
| 543 |
|
|
initial pre_fifo_addr_inc_wr = 1'b0;
|
| 544 |
|
|
always @(posedge i_clk)
|
| 545 |
|
|
pre_fifo_addr_inc_wr <= ((ll_fifo_wr)&&(ll_out_stb)&&(r_have_start_token));
|
| 546 |
|
|
always @(posedge i_clk)
|
| 547 |
|
|
pre_fifo_addr_inc_rd <= ((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle));//&&(ll_fifo_pkt_state[2:0]!=3'b000));
|
| 548 |
|
|
always @(posedge i_clk)
|
| 549 |
|
|
begin
|
| 550 |
|
|
// if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS)&&(i_wb_data[11]))
|
| 551 |
|
|
// ll_fifo_addr <= {(LGFIFOLN+2){1'b0}};
|
| 552 |
|
|
if (~r_cmd_busy)
|
| 553 |
|
|
ll_fifo_addr <= {(LGFIFOLN+2){1'b0}};
|
| 554 |
|
|
else if ((pre_fifo_addr_inc_wr)||(pre_fifo_addr_inc_rd))
|
| 555 |
|
|
ll_fifo_addr <= ll_fifo_addr + 1;
|
| 556 |
|
|
end
|
| 557 |
|
|
|
| 558 |
|
|
// Look for that start token
|
| 559 |
|
|
always @(posedge i_clk)
|
| 560 |
|
|
if (~r_cmd_busy)
|
| 561 |
|
|
r_have_start_token <= 1'b0;
|
| 562 |
|
|
else if ((ll_fifo_wr)&&(ll_out_stb)&&(ll_out_dat==8'hfe))
|
| 563 |
|
|
r_have_start_token <= 1'b1;
|
| 564 |
|
|
|
| 565 |
|
|
reg last_fifo_byte;
|
| 566 |
|
|
initial last_fifo_byte = 1'b0;
|
| 567 |
|
|
always @(posedge i_clk)
|
| 568 |
|
|
if (ll_fifo_wr)
|
| 569 |
|
|
last_fifo_byte <= (ll_fifo_addr == w_blklimit);
|
| 570 |
|
|
else
|
| 571 |
|
|
last_fifo_byte <= 1'b0;
|
| 572 |
|
|
|
| 573 |
|
|
// This is the one (and only allowed) write to the FIFO memory always
|
| 574 |
|
|
// block.
|
| 575 |
|
|
//
|
| 576 |
|
|
// If ll_fifo_wr is true, we'll be writing to the FIFO, and we'll do
|
| 577 |
|
|
// that here. This is different from r_fifo_wr, which specifies that
|
| 578 |
|
|
// we will be writing to the SDCard from the FIFO, and hence READING
|
| 579 |
|
|
// from the FIFO.
|
| 580 |
|
|
//
|
| 581 |
|
|
reg pre_fifo_a_wr, pre_fifo_b_wr, pre_fifo_crc_a, pre_fifo_crc_b,
|
| 582 |
|
|
clear_fifo_crc;
|
| 583 |
|
|
always @(posedge i_clk)
|
| 584 |
|
|
begin
|
| 585 |
|
|
pre_fifo_a_wr <= (ll_fifo_wr)&&(ll_out_stb)&&(~r_fifo_id)&&(ll_fifo_wr_state == 2'b00);
|
| 586 |
|
|
pre_fifo_b_wr <= (ll_fifo_wr)&&(ll_out_stb)&&( r_fifo_id)&&(ll_fifo_wr_state == 2'b00);
|
| 587 |
|
|
fifo_wr_crc_stb <= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b00)&&(r_have_start_token);
|
| 588 |
|
|
pre_fifo_crc_a<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b01);
|
| 589 |
|
|
pre_fifo_crc_b<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b10);
|
| 590 |
|
|
clear_fifo_crc <= (cmd_stb)&&(i_wb_data[15]);
|
| 591 |
|
|
end
|
| 592 |
|
|
|
| 593 |
|
|
initial fifo_crc_err = 1'b0;
|
| 594 |
|
|
always @(posedge i_clk)
|
| 595 |
|
|
begin // One and only memory write allowed
|
| 596 |
|
|
if ((write_stb)&&(i_wb_addr[1:0]==2'b10))
|
| 597 |
|
|
{fifo_a_mem[{ fifo_wb_addr, 2'b00 }],
|
| 598 |
|
|
fifo_a_mem[{ fifo_wb_addr, 2'b01 }],
|
| 599 |
|
|
fifo_a_mem[{ fifo_wb_addr, 2'b10 }],
|
| 600 |
|
|
fifo_a_mem[{ fifo_wb_addr, 2'b11 }] }
|
| 601 |
|
|
<= i_wb_data;
|
| 602 |
|
|
else if (pre_fifo_a_wr)
|
| 603 |
|
|
fifo_a_mem[{ ll_fifo_addr }] <= ll_out_dat;
|
| 604 |
|
|
|
| 605 |
|
|
if ((write_stb)&&(i_wb_addr[1:0]==2'b11))
|
| 606 |
|
|
{fifo_b_mem[{fifo_wb_addr, 2'b00 }],
|
| 607 |
|
|
fifo_b_mem[{ fifo_wb_addr, 2'b01 }],
|
| 608 |
|
|
fifo_b_mem[{ fifo_wb_addr, 2'b10 }],
|
| 609 |
|
|
fifo_b_mem[{ fifo_wb_addr, 2'b11 }] }
|
| 610 |
|
|
<= i_wb_data;
|
| 611 |
|
|
else if (pre_fifo_b_wr)
|
| 612 |
|
|
fifo_b_mem[{ ll_fifo_addr }] <= ll_out_dat;
|
| 613 |
|
|
|
| 614 |
|
|
if (~r_cmd_busy)
|
| 615 |
|
|
ll_fifo_wr_complete <= 1'b0;
|
| 616 |
|
|
|
| 617 |
|
|
if (~r_cmd_busy)
|
| 618 |
|
|
ll_fifo_wr_state <= 2'b00;
|
| 619 |
|
|
else if ((pre_fifo_a_wr)||(pre_fifo_b_wr))
|
| 620 |
|
|
ll_fifo_wr_state <= (last_fifo_byte)? 2'b01:2'b00;
|
| 621 |
|
|
|
| 622 |
|
|
if (pre_fifo_crc_a)
|
| 623 |
|
|
begin
|
| 624 |
|
|
fifo_crc_err <= fifo_crc_err | (fifo_wr_crc_reg[15:8]!=ll_out_dat);
|
| 625 |
|
|
ll_fifo_wr_state <= ll_fifo_wr_state + 2'b01;
|
| 626 |
|
|
end if (pre_fifo_crc_b)
|
| 627 |
|
|
begin
|
| 628 |
|
|
fifo_crc_err <= fifo_crc_err | (fifo_wr_crc_reg[7:0]!=ll_out_dat);
|
| 629 |
|
|
ll_fifo_wr_state <= ll_fifo_wr_state + 2'b01;
|
| 630 |
|
|
ll_fifo_wr_complete <= 1'b1;
|
| 631 |
|
|
end else if (clear_fifo_crc)
|
| 632 |
|
|
fifo_crc_err <= 1'b0;
|
| 633 |
|
|
end
|
| 634 |
|
|
|
| 635 |
|
|
always @(posedge i_clk)
|
| 636 |
|
|
begin // Second memory read, this time for the FIFO
|
| 637 |
|
|
fifo_a_byte <= fifo_a_mem[ ll_fifo_addr ];
|
| 638 |
|
|
fifo_b_byte <= fifo_b_mem[ ll_fifo_addr ];
|
| 639 |
|
|
end
|
| 640 |
|
|
|
| 641 |
|
|
reg [(LGFIFOLN-1):0] r_blklimit;
|
| 642 |
|
|
wire [(LGFIFOLN+1):0] w_blklimit;
|
| 643 |
|
|
always @(posedge i_clk)
|
| 644 |
|
|
r_blklimit[(LGFIFOLN-1):0] = (1<<r_lgblklen)-1;
|
| 645 |
|
|
assign w_blklimit = { r_blklimit, 2'b11 };
|
| 646 |
|
|
|
| 647 |
|
|
// Package the FIFO reads up into a packet
|
| 648 |
|
|
always @(posedge i_clk)
|
| 649 |
|
|
begin
|
| 650 |
|
|
fifo_rd_crc_stb <= 1'b0;
|
| 651 |
|
|
if (r_cmd_busy)
|
| 652 |
|
|
begin
|
| 653 |
|
|
if (ll_fifo_pkt_state[2:0] == 3'b000)
|
| 654 |
|
|
begin
|
| 655 |
|
|
if((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle))
|
| 656 |
|
|
begin
|
| 657 |
|
|
ll_fifo_pkt_state <= ll_fifo_pkt_state + 3'b001;
|
| 658 |
|
|
end
|
| 659 |
|
|
end else if (ll_fifo_pkt_state[2:0] == 3'b001)
|
| 660 |
|
|
begin
|
| 661 |
|
|
if((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle))
|
| 662 |
|
|
begin
|
| 663 |
|
|
ll_fifo_pkt_state <= ll_fifo_pkt_state + 3'b001;
|
| 664 |
|
|
fifo_byte <= (r_fifo_id)
|
| 665 |
|
|
? fifo_b_byte : fifo_a_byte;
|
| 666 |
|
|
fifo_rd_crc_stb <= 1'b1;
|
| 667 |
|
|
end
|
| 668 |
|
|
end else if (ll_fifo_pkt_state[2:0] == 3'b010)
|
| 669 |
|
|
begin
|
| 670 |
|
|
if((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle))
|
| 671 |
|
|
begin
|
| 672 |
|
|
fifo_byte <= (r_fifo_id)
|
| 673 |
|
|
? fifo_b_byte : fifo_a_byte;
|
| 674 |
|
|
fifo_rd_crc_stb <= 1'b1;
|
| 675 |
|
|
end
|
| 676 |
|
|
if (ll_fifo_addr == 0)
|
| 677 |
|
|
ll_fifo_pkt_state <= 3'b011;
|
| 678 |
|
|
end else if (ll_fifo_pkt_state == 3'b011)
|
| 679 |
|
|
begin // 1st CRC byte
|
| 680 |
|
|
if((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle))
|
| 681 |
|
|
begin
|
| 682 |
|
|
fifo_byte <= fifo_rd_crc_reg[15:8];
|
| 683 |
|
|
ll_fifo_pkt_state <= 3'b100;
|
| 684 |
|
|
end
|
| 685 |
|
|
end else if (ll_fifo_pkt_state == 3'b100)
|
| 686 |
|
|
begin // 2nd CRC byte
|
| 687 |
|
|
if((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle))
|
| 688 |
|
|
begin
|
| 689 |
|
|
fifo_byte <= fifo_rd_crc_reg[7:0];
|
| 690 |
|
|
ll_fifo_pkt_state <= 3'b101;
|
| 691 |
|
|
end
|
| 692 |
|
|
end else if((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle))
|
| 693 |
|
|
begin
|
| 694 |
|
|
// Idle the channel
|
| 695 |
|
|
ll_fifo_rd_complete <= 1'b1;
|
| 696 |
|
|
fifo_byte <= 8'hff;
|
| 697 |
|
|
end
|
| 698 |
|
|
end else if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS))
|
| 699 |
|
|
begin
|
| 700 |
|
|
ll_fifo_pkt_state <= 3'h0;
|
| 701 |
|
|
ll_fifo_rd_complete <= 1'b0;
|
| 702 |
|
|
fifo_byte <= (i_wb_data[12]) ? fifo_b_byte : fifo_a_byte;
|
| 703 |
|
|
fifo_rd_crc_stb <= 1'b1;
|
| 704 |
|
|
end else begin // Packet state is IDLE (clear the CRC registers)
|
| 705 |
|
|
ll_fifo_pkt_state <= 3'b111;
|
| 706 |
|
|
ll_fifo_rd_complete <= 1'b1;
|
| 707 |
|
|
end
|
| 708 |
|
|
end
|
| 709 |
|
|
|
| 710 |
|
|
always @(posedge i_clk)
|
| 711 |
|
|
begin
|
| 712 |
|
|
if (~ll_fifo_wr)
|
| 713 |
|
|
fifo_wr_crc_reg <= 16'h00;
|
| 714 |
|
|
else if (fifo_wr_crc_stb)
|
| 715 |
|
|
begin
|
| 716 |
|
|
fifo_wr_crc_reg[15:8] <=fifo_wr_crc_reg[15:8]^ll_out_dat;
|
| 717 |
|
|
fifo_wr_crc_count <= 4'h8;
|
| 718 |
|
|
end else if (|fifo_wr_crc_count)
|
| 719 |
|
|
begin
|
| 720 |
|
|
fifo_wr_crc_count <= fifo_wr_crc_count - 4'h1;
|
| 721 |
|
|
if (fifo_wr_crc_reg[15])
|
| 722 |
|
|
fifo_wr_crc_reg <= { fifo_wr_crc_reg[14:0], 1'b0 }
|
| 723 |
|
|
^ 16'h1021;
|
| 724 |
|
|
else
|
| 725 |
|
|
fifo_wr_crc_reg <= { fifo_wr_crc_reg[14:0], 1'b0 };
|
| 726 |
|
|
end
|
| 727 |
|
|
end
|
| 728 |
|
|
|
| 729 |
|
|
always @(posedge i_clk)
|
| 730 |
|
|
begin
|
| 731 |
|
|
if (~r_cmd_busy)
|
| 732 |
|
|
begin
|
| 733 |
|
|
fifo_rd_crc_reg <= 16'h00;
|
| 734 |
|
|
fifo_rd_crc_count <= 4'h0;
|
| 735 |
|
|
end else if (fifo_rd_crc_stb)
|
| 736 |
|
|
begin
|
| 737 |
|
|
fifo_rd_crc_reg[15:8] <=fifo_rd_crc_reg[15:8]^fifo_byte;
|
| 738 |
|
|
fifo_rd_crc_count <= 4'h8;
|
| 739 |
|
|
end else if (|fifo_rd_crc_count)
|
| 740 |
|
|
begin
|
| 741 |
|
|
fifo_rd_crc_count <= fifo_rd_crc_count - 4'h1;
|
| 742 |
|
|
if (fifo_rd_crc_reg[15])
|
| 743 |
|
|
fifo_rd_crc_reg <= { fifo_rd_crc_reg[14:0], 1'b0 }
|
| 744 |
|
|
^ 16'h1021;
|
| 745 |
|
|
else
|
| 746 |
|
|
fifo_rd_crc_reg <= { fifo_rd_crc_reg[14:0], 1'b0 };
|
| 747 |
|
|
end
|
| 748 |
|
|
end
|
| 749 |
|
|
|
| 750 |
|
|
//
|
| 751 |
|
|
// Calculate a CRC for the command section of our output
|
| 752 |
|
|
//
|
| 753 |
|
|
initial r_cmd_crc_ff = 1'b0;
|
| 754 |
|
|
always @(posedge i_clk)
|
| 755 |
|
|
begin
|
| 756 |
|
|
if (~r_cmd_busy)
|
| 757 |
|
|
begin
|
| 758 |
|
|
r_cmd_crc <= 8'h00;
|
| 759 |
|
|
r_cmd_crc_cnt <= 4'hf;
|
| 760 |
|
|
r_cmd_crc_ff <= 1'b0;
|
| 761 |
|
|
end else if (~r_cmd_crc_cnt[3])
|
| 762 |
|
|
begin
|
| 763 |
|
|
r_cmd_crc_cnt <= r_cmd_crc_cnt - 4'h1;
|
| 764 |
|
|
if (r_cmd_crc[7])
|
| 765 |
|
|
r_cmd_crc <= { r_cmd_crc[6:0], 1'b0 } ^ 8'h12;
|
| 766 |
|
|
else
|
| 767 |
|
|
r_cmd_crc <= { r_cmd_crc[6:0], 1'b0 };
|
| 768 |
|
|
r_cmd_crc_ff <= (r_cmd_crc_ff)||(r_cmd_crc_stb);
|
| 769 |
|
|
end else if ((r_cmd_crc_stb)||(r_cmd_crc_ff))
|
| 770 |
|
|
begin
|
| 771 |
|
|
r_cmd_crc <= r_cmd_crc ^ ll_cmd_dat;
|
| 772 |
|
|
r_cmd_crc_cnt <= 4'h7;
|
| 773 |
|
|
r_cmd_crc_ff <= 1'b0;
|
| 774 |
|
|
end
|
| 775 |
|
|
end
|
| 776 |
|
|
assign cmd_crc = { r_cmd_crc[7:1], 1'b1 };
|
| 777 |
|
|
|
| 778 |
|
|
//
|
| 779 |
|
|
// Some watchdog logic for us. This way, if we are waiting for the
|
| 780 |
|
|
// card to respond, and something goes wrong, we can timeout the
|
| 781 |
|
|
// transaction and ... figure out what to do about it later. At least
|
| 782 |
|
|
// we'll have an error indication.
|
| 783 |
|
|
//
|
| 784 |
|
|
initial r_watchdog = 26'h3ffffff;
|
| 785 |
|
|
initial r_watchdog_err = 1'b0;
|
| 786 |
|
|
always @(posedge i_clk)
|
| 787 |
|
|
if (~r_cmd_busy)
|
| 788 |
|
|
r_watchdog_err <= 1'b0;
|
| 789 |
|
|
else if (r_watchdog == 0)
|
| 790 |
|
|
r_watchdog_err <= 1'b1;
|
| 791 |
|
|
always @(posedge i_clk)
|
| 792 |
|
|
if (~r_cmd_busy)
|
| 793 |
|
|
r_watchdog <= 26'h3fffff;
|
| 794 |
|
|
else if (|r_watchdog)
|
| 795 |
|
|
r_watchdog <= r_watchdog - 26'h1;
|
| 796 |
|
|
|
| 797 |
|
|
assign o_debug = { ((ll_cmd_stb)&&(ll_idle))||(ll_out_stb),
|
| 798 |
|
|
ll_cmd_stb, ll_idle, ll_out_stb, // 4'h
|
| 799 |
|
|
o_cs_n, o_sck, o_mosi, i_miso, // 4'h
|
| 800 |
|
|
r_cmd_state, i_bus_grant, // 4'h
|
| 801 |
|
|
r_rsp_state, r_cmd_busy, // 4'h
|
| 802 |
|
|
ll_cmd_dat, // 8'b
|
| 803 |
|
|
ll_out_dat }; // 8'b
|
| 804 |
|
|
endmodule
|
| 805 |
|
|
|
