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[/] [sha256core/] [trunk/] [rtl/] [ff_bank.vhd] - Blame information for rev 2

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1 2 entactogen
 
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-- Copyright (c) 2013 Antonio de la Piedra
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity ff_bank is
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        port(clk : in std_logic;
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                                 d   : in std_logic_vector(31 downto 0);
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             q   : out std_logic_vector(31 downto 0));
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end ff_bank;
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architecture rtl of ff_bank is
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begin
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        process(clk)
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        begin
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                        if rising_edge(clk) then
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                                q <= d;
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         end if;
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        end process;
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end rtl;
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