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[/] [sha256core/] [trunk/] [rtl/] [sh_reg.vhd] - Blame information for rev 2

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-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
 
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.sha_fun.ALL;
 
entity sh_reg is
        port(clk  : in std_logic;
             rst : in std_logic;
 
                                 msg_0 : in std_logic_vector(31 downto 0);
                                 msg_1 : in std_logic_vector(31 downto 0);
                                 msg_2 : in std_logic_vector(31 downto 0);
                                 msg_3 : in std_logic_vector(31 downto 0);
                                 msg_4 : in std_logic_vector(31 downto 0);
                            msg_5 : in std_logic_vector(31 downto 0);
                            msg_6 : in std_logic_vector(31 downto 0);
                                 msg_7 : in std_logic_vector(31 downto 0);
                                 msg_8 : in std_logic_vector(31 downto 0);
                                 msg_9 : in std_logic_vector(31 downto 0);
                       msg_10 : in std_logic_vector(31 downto 0);
                       msg_11 : in std_logic_vector(31 downto 0);
                       msg_12 : in std_logic_vector(31 downto 0);
                       msg_13 : in std_logic_vector(31 downto 0);
                       msg_14 : in std_logic_vector(31 downto 0);
                       msg_15 : in std_logic_vector(31 downto 0);
 
                                 w_j : out std_logic_vector(31 downto 0));
end sh_reg;
 
architecture structural of sh_reg is
 
        component ff_bank is
                        port(clk : in std_logic;
                                  d   : in std_logic_vector(31 downto 0);
              q   : out std_logic_vector(31 downto 0));
        end component;
 
        signal d_0_tmp : std_logic_vector(31 downto 0);
        signal d_1_tmp : std_logic_vector(31 downto 0);
        signal d_2_tmp : std_logic_vector(31 downto 0);
        signal d_3_tmp : std_logic_vector(31 downto 0);
        signal d_4_tmp : std_logic_vector(31 downto 0);
        signal d_5_tmp : std_logic_vector(31 downto 0);
        signal d_6_tmp : std_logic_vector(31 downto 0);
        signal d_7_tmp : std_logic_vector(31 downto 0);
        signal d_8_tmp : std_logic_vector(31 downto 0);
        signal d_9_tmp : std_logic_vector(31 downto 0);
        signal d_10_tmp : std_logic_vector(31 downto 0);
        signal d_11_tmp : std_logic_vector(31 downto 0);
        signal d_12_tmp : std_logic_vector(31 downto 0);
        signal d_13_tmp : std_logic_vector(31 downto 0);
        signal d_14_tmp : std_logic_vector(31 downto 0);
        signal d_15_tmp : std_logic_vector(31 downto 0);
 
        signal q_0_tmp : std_logic_vector(31 downto 0);
        signal q_1_tmp : std_logic_vector(31 downto 0);
        signal q_2_tmp : std_logic_vector(31 downto 0);
        signal q_3_tmp : std_logic_vector(31 downto 0);
        signal q_4_tmp : std_logic_vector(31 downto 0);
        signal q_5_tmp : std_logic_vector(31 downto 0);
        signal q_6_tmp : std_logic_vector(31 downto 0);
        signal q_7_tmp : std_logic_vector(31 downto 0);
        signal q_8_tmp : std_logic_vector(31 downto 0);
        signal q_9_tmp : std_logic_vector(31 downto 0);
        signal q_10_tmp : std_logic_vector(31 downto 0);
        signal q_11_tmp : std_logic_vector(31 downto 0);
        signal q_12_tmp : std_logic_vector(31 downto 0);
        signal q_13_tmp : std_logic_vector(31 downto 0);
        signal q_14_tmp : std_logic_vector(31 downto 0);
        signal q_15_tmp : std_logic_vector(31 downto 0);
 
        signal w_j_tmp : std_logic_vector(31 downto 0);
 
begin
 
        mux_ff_0:process(rst, msg_0, w_j_tmp)
        begin
                        if rst = '1' then
                                d_0_tmp <= msg_0;
                        else
                                d_0_tmp <= w_j_tmp;
                        end if;
        end process;
 
        mux_ff_1:process(rst, msg_1, q_0_tmp)
        begin
                        if rst = '1' then
                                d_1_tmp <= msg_1;
                        else
                                d_1_tmp <= q_0_tmp;
                        end if;
        end process;
 
        mux_ff_2:process(rst, msg_2, q_1_tmp)
        begin
                        if rst = '1' then
                                d_2_tmp <= msg_2;
                        else
                                d_2_tmp <= q_1_tmp;
                        end if;
        end process;
 
        mux_ff_3:process(rst, msg_3, q_2_tmp)
        begin
                        if rst = '1' then
                                d_3_tmp <= msg_3;
                        else
                                d_3_tmp <= q_2_tmp;
                        end if;
        end process;
 
        mux_ff_4:process(rst, msg_4, q_3_tmp)
        begin
                        if rst = '1' then
                                d_4_tmp <= msg_4;
                        else
                                d_4_tmp <= q_3_tmp;
                        end if;
        end process;
 
        mux_ff_5:process(rst, msg_5, q_4_tmp)
        begin
                        if rst = '1' then
                                d_5_tmp <= msg_5;
                        else
                                d_5_tmp <= q_4_tmp;
                        end if;
        end process;
 
        mux_ff_6:process(rst, msg_6, q_5_tmp)
        begin
                        if rst = '1' then
                                d_6_tmp <= msg_6;
                        else
                                d_6_tmp <= q_5_tmp;
                        end if;
        end process;
 
        mux_ff_7:process(rst, msg_7, q_6_tmp)
        begin
                        if rst = '1' then
                                d_7_tmp <= msg_7;
                        else
                                d_7_tmp <= q_6_tmp;
                        end if;
        end process;
 
        mux_ff_8:process(rst, msg_8, q_7_tmp)
        begin
                        if rst = '1' then
                                d_8_tmp <= msg_8;
                        else
                                d_8_tmp <= q_7_tmp;
                        end if;
        end process;
 
        mux_ff_9:process(rst, msg_9, q_8_tmp)
        begin
                        if rst = '1' then
                                d_9_tmp <= msg_9;
                        else
                                d_9_tmp <= q_8_tmp;
                        end if;
        end process;
 
        mux_ff_10:process(rst, msg_10, q_9_tmp)
        begin
                        if rst = '1' then
                                d_10_tmp <= msg_10;
                        else
                                d_10_tmp <= q_9_tmp;
                        end if;
        end process;
 
        mux_ff_11:process(rst, msg_11, q_10_tmp)
        begin
                        if rst = '1' then
                                d_11_tmp <= msg_11;
                        else
                                d_11_tmp <= q_10_tmp;
                        end if;
        end process;
 
        mux_ff_12:process(rst, msg_12, q_11_tmp)
        begin
                        if rst = '1' then
                                d_12_tmp <= msg_12;
                        else
                                d_12_tmp <= q_11_tmp;
                        end if;
        end process;
 
        mux_ff_13:process(rst, msg_13, q_12_tmp)
        begin
                        if rst = '1' then
                                d_13_tmp <= msg_13;
                        else
                                d_13_tmp <= q_12_tmp;
                        end if;
        end process;
 
        mux_ff_14:process(rst, msg_14, q_13_tmp)
        begin
                        if rst = '1' then
                                d_14_tmp <= msg_14;
                        else
                                d_14_tmp <= q_13_tmp;
                        end if;
        end process;
 
        mux_ff_15:process(rst, msg_15, q_14_tmp)
        begin
                        if rst = '1' then
                                d_15_tmp <= msg_15;
                        else
                                d_15_tmp <= q_14_tmp;
                        end if;
        end process;
 
        ff_0 : ff_bank port map (clk, d_0_tmp, q_0_tmp);
        ff_1 : ff_bank port map (clk, d_1_tmp, q_1_tmp);
        ff_2 : ff_bank port map (clk, d_2_tmp, q_2_tmp);
        ff_3 : ff_bank port map (clk, d_3_tmp, q_3_tmp);
        ff_4 : ff_bank port map (clk, d_4_tmp, q_4_tmp);
        ff_5 : ff_bank port map (clk, d_5_tmp, q_5_tmp);
        ff_6 : ff_bank port map (clk, d_6_tmp, q_6_tmp);
        ff_7 : ff_bank port map (clk, d_7_tmp, q_7_tmp);
        ff_8 : ff_bank port map (clk, d_8_tmp, q_8_tmp);
        ff_9 : ff_bank port map (clk, d_9_tmp, q_9_tmp);
        ff_10 : ff_bank port map (clk, d_10_tmp, q_10_tmp);
        ff_11 : ff_bank port map (clk, d_11_tmp, q_11_tmp);
        ff_12 : ff_bank port map (clk, d_12_tmp, q_12_tmp);
        ff_13 : ff_bank port map (clk, d_13_tmp, q_13_tmp);
        ff_14 : ff_bank port map (clk, d_14_tmp, q_14_tmp);
        ff_15 : ff_bank port map (clk, d_15_tmp, q_15_tmp);
 
        w_j_tmp <= std_logic_vector(unsigned(sigma_0(q_14_tmp)) + unsigned(q_15_tmp) +
                         unsigned(sigma_1(q_1_tmp)) + unsigned(q_6_tmp));
 
        w_j <= w_j_tmp;
 
end structural;

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[/] [sha256core/] [trunk/] [rtl/] [sh_reg.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	entactogen
2
3			`-- Copyright (c) 2013 Antonio de la Piedra`
4
5			`-- This program is free software: you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation, either version 3 of the License, or`
8			`-- (at your option) any later version.`
9
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14
15			`-- You should have received a copy of the GNU General Public License`
16			`-- along with this program. If not, see <http://www.gnu.org/licenses/>.`
17
18			`library IEEE;`
19
20			`use IEEE.STD_LOGIC_1164.ALL;`
21			`use IEEE.NUMERIC_STD.ALL;`
22			`use work.sha_fun.ALL;`
23
24			`entity sh_reg is`
25			`port(clk : in std_logic;`
26			`rst : in std_logic;`
27
28			`msg_0 : in std_logic_vector(31 downto 0);`
29			`msg_1 : in std_logic_vector(31 downto 0);`
30			`msg_2 : in std_logic_vector(31 downto 0);`
31			`msg_3 : in std_logic_vector(31 downto 0);`
32			`msg_4 : in std_logic_vector(31 downto 0);`
33			`msg_5 : in std_logic_vector(31 downto 0);`
34			`msg_6 : in std_logic_vector(31 downto 0);`
35			`msg_7 : in std_logic_vector(31 downto 0);`
36			`msg_8 : in std_logic_vector(31 downto 0);`
37			`msg_9 : in std_logic_vector(31 downto 0);`
38			`msg_10 : in std_logic_vector(31 downto 0);`
39			`msg_11 : in std_logic_vector(31 downto 0);`
40			`msg_12 : in std_logic_vector(31 downto 0);`
41			`msg_13 : in std_logic_vector(31 downto 0);`
42			`msg_14 : in std_logic_vector(31 downto 0);`
43			`msg_15 : in std_logic_vector(31 downto 0);`
44
45			`w_j : out std_logic_vector(31 downto 0));`
46			`end sh_reg;`
47
48			`architecture structural of sh_reg is`
49
50			`component ff_bank is`
51			`port(clk : in std_logic;`
52			`d : in std_logic_vector(31 downto 0);`
53			`q : out std_logic_vector(31 downto 0));`
54			`end component;`
55
56			`signal d_0_tmp : std_logic_vector(31 downto 0);`
57			`signal d_1_tmp : std_logic_vector(31 downto 0);`
58			`signal d_2_tmp : std_logic_vector(31 downto 0);`
59			`signal d_3_tmp : std_logic_vector(31 downto 0);`
60			`signal d_4_tmp : std_logic_vector(31 downto 0);`
61			`signal d_5_tmp : std_logic_vector(31 downto 0);`
62			`signal d_6_tmp : std_logic_vector(31 downto 0);`
63			`signal d_7_tmp : std_logic_vector(31 downto 0);`
64			`signal d_8_tmp : std_logic_vector(31 downto 0);`
65			`signal d_9_tmp : std_logic_vector(31 downto 0);`
66			`signal d_10_tmp : std_logic_vector(31 downto 0);`
67			`signal d_11_tmp : std_logic_vector(31 downto 0);`
68			`signal d_12_tmp : std_logic_vector(31 downto 0);`
69			`signal d_13_tmp : std_logic_vector(31 downto 0);`
70			`signal d_14_tmp : std_logic_vector(31 downto 0);`
71			`signal d_15_tmp : std_logic_vector(31 downto 0);`
72
73			`signal q_0_tmp : std_logic_vector(31 downto 0);`
74			`signal q_1_tmp : std_logic_vector(31 downto 0);`
75			`signal q_2_tmp : std_logic_vector(31 downto 0);`
76			`signal q_3_tmp : std_logic_vector(31 downto 0);`
77			`signal q_4_tmp : std_logic_vector(31 downto 0);`
78			`signal q_5_tmp : std_logic_vector(31 downto 0);`
79			`signal q_6_tmp : std_logic_vector(31 downto 0);`
80			`signal q_7_tmp : std_logic_vector(31 downto 0);`
81			`signal q_8_tmp : std_logic_vector(31 downto 0);`
82			`signal q_9_tmp : std_logic_vector(31 downto 0);`
83			`signal q_10_tmp : std_logic_vector(31 downto 0);`
84			`signal q_11_tmp : std_logic_vector(31 downto 0);`
85			`signal q_12_tmp : std_logic_vector(31 downto 0);`
86			`signal q_13_tmp : std_logic_vector(31 downto 0);`
87			`signal q_14_tmp : std_logic_vector(31 downto 0);`
88			`signal q_15_tmp : std_logic_vector(31 downto 0);`
89
90			`signal w_j_tmp : std_logic_vector(31 downto 0);`
91
92			`begin`
93
94			`mux_ff_0:process(rst, msg_0, w_j_tmp)`
95			`begin`
96			`if rst = '1' then`
97			`d_0_tmp <= msg_0;`
98			`else`
99			`d_0_tmp <= w_j_tmp;`
100			`end if;`
101			`end process;`
102
103			`mux_ff_1:process(rst, msg_1, q_0_tmp)`
104			`begin`
105			`if rst = '1' then`
106			`d_1_tmp <= msg_1;`
107			`else`
108			`d_1_tmp <= q_0_tmp;`
109			`end if;`
110			`end process;`
111
112			`mux_ff_2:process(rst, msg_2, q_1_tmp)`
113			`begin`
114			`if rst = '1' then`
115			`d_2_tmp <= msg_2;`
116			`else`
117			`d_2_tmp <= q_1_tmp;`
118			`end if;`
119			`end process;`
120
121			`mux_ff_3:process(rst, msg_3, q_2_tmp)`
122			`begin`
123			`if rst = '1' then`
124			`d_3_tmp <= msg_3;`
125			`else`
126			`d_3_tmp <= q_2_tmp;`
127			`end if;`
128			`end process;`
129
130			`mux_ff_4:process(rst, msg_4, q_3_tmp)`
131			`begin`
132			`if rst = '1' then`
133			`d_4_tmp <= msg_4;`
134			`else`
135			`d_4_tmp <= q_3_tmp;`
136			`end if;`
137			`end process;`
138
139			`mux_ff_5:process(rst, msg_5, q_4_tmp)`
140			`begin`
141			`if rst = '1' then`
142			`d_5_tmp <= msg_5;`
143			`else`
144			`d_5_tmp <= q_4_tmp;`
145			`end if;`
146			`end process;`
147
148			`mux_ff_6:process(rst, msg_6, q_5_tmp)`
149			`begin`
150			`if rst = '1' then`
151			`d_6_tmp <= msg_6;`
152			`else`
153			`d_6_tmp <= q_5_tmp;`
154			`end if;`
155			`end process;`
156
157			`mux_ff_7:process(rst, msg_7, q_6_tmp)`
158			`begin`
159			`if rst = '1' then`
160			`d_7_tmp <= msg_7;`
161			`else`
162			`d_7_tmp <= q_6_tmp;`
163			`end if;`
164			`end process;`
165
166			`mux_ff_8:process(rst, msg_8, q_7_tmp)`
167			`begin`
168			`if rst = '1' then`
169			`d_8_tmp <= msg_8;`
170			`else`
171			`d_8_tmp <= q_7_tmp;`
172			`end if;`
173			`end process;`
174
175			`mux_ff_9:process(rst, msg_9, q_8_tmp)`
176			`begin`
177			`if rst = '1' then`
178			`d_9_tmp <= msg_9;`
179			`else`
180			`d_9_tmp <= q_8_tmp;`
181			`end if;`
182			`end process;`
183
184			`mux_ff_10:process(rst, msg_10, q_9_tmp)`
185			`begin`
186			`if rst = '1' then`
187			`d_10_tmp <= msg_10;`
188			`else`
189			`d_10_tmp <= q_9_tmp;`
190			`end if;`
191			`end process;`
192
193			`mux_ff_11:process(rst, msg_11, q_10_tmp)`
194			`begin`
195			`if rst = '1' then`
196			`d_11_tmp <= msg_11;`
197			`else`
198			`d_11_tmp <= q_10_tmp;`
199			`end if;`
200			`end process;`
201
202			`mux_ff_12:process(rst, msg_12, q_11_tmp)`
203			`begin`
204			`if rst = '1' then`
205			`d_12_tmp <= msg_12;`
206			`else`
207			`d_12_tmp <= q_11_tmp;`
208			`end if;`
209			`end process;`
210
211			`mux_ff_13:process(rst, msg_13, q_12_tmp)`
212			`begin`
213			`if rst = '1' then`
214			`d_13_tmp <= msg_13;`
215			`else`
216			`d_13_tmp <= q_12_tmp;`
217			`end if;`
218			`end process;`
219
220			`mux_ff_14:process(rst, msg_14, q_13_tmp)`
221			`begin`
222			`if rst = '1' then`
223			`d_14_tmp <= msg_14;`
224			`else`
225			`d_14_tmp <= q_13_tmp;`
226			`end if;`
227			`end process;`
228
229			`mux_ff_15:process(rst, msg_15, q_14_tmp)`
230			`begin`
231			`if rst = '1' then`
232			`d_15_tmp <= msg_15;`
233			`else`
234			`d_15_tmp <= q_14_tmp;`
235			`end if;`
236			`end process;`
237
238			`ff_0 : ff_bank port map (clk, d_0_tmp, q_0_tmp);`
239			`ff_1 : ff_bank port map (clk, d_1_tmp, q_1_tmp);`
240			`ff_2 : ff_bank port map (clk, d_2_tmp, q_2_tmp);`
241			`ff_3 : ff_bank port map (clk, d_3_tmp, q_3_tmp);`
242			`ff_4 : ff_bank port map (clk, d_4_tmp, q_4_tmp);`
243			`ff_5 : ff_bank port map (clk, d_5_tmp, q_5_tmp);`
244			`ff_6 : ff_bank port map (clk, d_6_tmp, q_6_tmp);`
245			`ff_7 : ff_bank port map (clk, d_7_tmp, q_7_tmp);`
246			`ff_8 : ff_bank port map (clk, d_8_tmp, q_8_tmp);`
247			`ff_9 : ff_bank port map (clk, d_9_tmp, q_9_tmp);`
248			`ff_10 : ff_bank port map (clk, d_10_tmp, q_10_tmp);`
249			`ff_11 : ff_bank port map (clk, d_11_tmp, q_11_tmp);`
250			`ff_12 : ff_bank port map (clk, d_12_tmp, q_12_tmp);`
251			`ff_13 : ff_bank port map (clk, d_13_tmp, q_13_tmp);`
252			`ff_14 : ff_bank port map (clk, d_14_tmp, q_14_tmp);`
253			`ff_15 : ff_bank port map (clk, d_15_tmp, q_15_tmp);`
254
255			`w_j_tmp <= std_logic_vector(unsigned(sigma_0(q_14_tmp)) + unsigned(q_15_tmp) +`
256			`unsigned(sigma_1(q_1_tmp)) + unsigned(q_6_tmp));`
257
258			`w_j <= w_j_tmp;`
259
260			`end structural;`