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[/] [sha256core/] [trunk/] [rtl/] [sha_256.vhd] - Blame information for rev 2

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-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity sha_256 is
        port(clk  : in std_logic;
             rst : in std_logic;
                                 gen_hash : in std_logic;
 
                                 msg_0 : in std_logic_vector(31 downto 0);
                                 msg_1 : in std_logic_vector(31 downto 0);
                                 msg_2 : in std_logic_vector(31 downto 0);
                                 msg_3 : in std_logic_vector(31 downto 0);
                                 msg_4 : in std_logic_vector(31 downto 0);
                            msg_5 : in std_logic_vector(31 downto 0);
                            msg_6 : in std_logic_vector(31 downto 0);
                                 msg_7 : in std_logic_vector(31 downto 0);
                                 msg_8 : in std_logic_vector(31 downto 0);
                                 msg_9 : in std_logic_vector(31 downto 0);
                       msg_10 : in std_logic_vector(31 downto 0);
                       msg_11 : in std_logic_vector(31 downto 0);
                       msg_12 : in std_logic_vector(31 downto 0);
                       msg_13 : in std_logic_vector(31 downto 0);
                       msg_14 : in std_logic_vector(31 downto 0);
                       msg_15 : in std_logic_vector(31 downto 0);
 
                                 a_out : out std_logic_vector(31 downto 0);
                                 b_out : out std_logic_vector(31 downto 0);
                                 c_out : out std_logic_vector(31 downto 0);
                                 d_out : out std_logic_vector(31 downto 0);
                                 e_out : out std_logic_vector(31 downto 0);
                                 f_out : out std_logic_vector(31 downto 0);
                                 g_out : out std_logic_vector(31 downto 0);
                                 h_out : out std_logic_vector(31 downto 0);
                                 block_ready : out std_logic;
                                 hash : out std_logic_vector(255 downto 0));
end sha_256;
 
architecture Behavioral of sha_256 is
 
        component msg_comp is
        port(clk  : in std_logic;
             rst : in std_logic;
 
                                 h_0 : in std_logic_vector(31 downto 0);
                                 h_1 : in std_logic_vector(31 downto 0);
                                 h_2 : in std_logic_vector(31 downto 0);
                                 h_3 : in std_logic_vector(31 downto 0);
                                 h_4 : in std_logic_vector(31 downto 0);
                            h_5 : in std_logic_vector(31 downto 0);
                            h_6 : in std_logic_vector(31 downto 0);
                                 h_7 : in std_logic_vector(31 downto 0);
 
                            w_i : in std_logic_vector(31 downto 0);
                                 k_i : in std_logic_vector(31 downto 0);
 
                                 a : out std_logic_vector(31 downto 0);
                                 b : out std_logic_vector(31 downto 0);
                                 c : out std_logic_vector(31 downto 0);
                                 d : out std_logic_vector(31 downto 0);
                                 e : out std_logic_vector(31 downto 0);
                                 f : out std_logic_vector(31 downto 0);
                                 g : out std_logic_vector(31 downto 0);
                                 h : out std_logic_vector(31 downto 0));
        end component;
 
        component sh_reg is
        port(clk  : in std_logic;
             rst : in std_logic;
 
                                 msg_0 : in std_logic_vector(31 downto 0);
                                 msg_1 : in std_logic_vector(31 downto 0);
                                 msg_2 : in std_logic_vector(31 downto 0);
                                 msg_3 : in std_logic_vector(31 downto 0);
                                 msg_4 : in std_logic_vector(31 downto 0);
                            msg_5 : in std_logic_vector(31 downto 0);
                            msg_6 : in std_logic_vector(31 downto 0);
                                 msg_7 : in std_logic_vector(31 downto 0);
                                 msg_8 : in std_logic_vector(31 downto 0);
                                 msg_9 : in std_logic_vector(31 downto 0);
                       msg_10 : in std_logic_vector(31 downto 0);
                       msg_11 : in std_logic_vector(31 downto 0);
                       msg_12 : in std_logic_vector(31 downto 0);
                       msg_13 : in std_logic_vector(31 downto 0);
                       msg_14 : in std_logic_vector(31 downto 0);
                       msg_15 : in std_logic_vector(31 downto 0);
 
                                 w_j : out std_logic_vector(31 downto 0));
        end component;
 
  component dual_mem is
  generic (ADDR_LENGTH : integer := 6;
           DATA_LENGTH : integer := 32;
           N_ADDR      : integer := 64);
  port (clk  : in std_logic;
        we   : in std_logic;
        a    : in std_logic_vector(ADDR_LENGTH - 1 downto 0);
        dpra : in std_logic_vector(ADDR_LENGTH - 1 downto 0);
        di   : in std_logic_vector(DATA_LENGTH - 1 downto 0);
        spo  : out std_logic_vector(DATA_LENGTH - 1 downto 0);
        dpo  : out std_logic_vector(DATA_LENGTH - 1 downto 0));
        end component;
 
        signal w_j_tmp : std_logic_vector(31 downto 0);
 
        signal h_0_tmp : std_logic_vector(31 downto 0);
        signal h_1_tmp : std_logic_vector(31 downto 0);
        signal h_2_tmp : std_logic_vector(31 downto 0);
        signal h_3_tmp : std_logic_vector(31 downto 0);
        signal h_4_tmp : std_logic_vector(31 downto 0);
        signal h_5_tmp : std_logic_vector(31 downto 0);
        signal h_6_tmp : std_logic_vector(31 downto 0);
        signal h_7_tmp : std_logic_vector(31 downto 0);
 
        signal k_i_tmp : std_logic_vector(31 downto 0);
 
        signal start_cnt_tmp, rst_sch_tmp, rst_comp_tmp : std_logic;
        signal cnt_s : std_logic_vector(5 downto 0);
 
        signal m_tmp : std_logic_vector(31 downto 0);
 
   type state_type is (idle, init, run, m_1, m_2, m_3, m_4, m_5, m_6, m_7,
        m_8, m_9, m_10, m_11, m_12, m_13, m_14, m_15, w_s);
   signal state, next_state: state_type ;
 
  type delay_buffer_t is array(67 downto 0) of
   std_logic;
 
  signal hash_delay : delay_buffer_t;
 
  signal a_out_tmp : std_logic_vector(31 downto 0);
  signal b_out_tmp : std_logic_vector(31 downto 0);
  signal c_out_tmp : std_logic_vector(31 downto 0);
  signal d_out_tmp : std_logic_vector(31 downto 0);
  signal e_out_tmp : std_logic_vector(31 downto 0);
  signal f_out_tmp : std_logic_vector(31 downto 0);
  signal g_out_tmp : std_logic_vector(31 downto 0);
  signal h_out_tmp : std_logic_vector(31 downto 0);
 
  signal gen_hash_tmp : std_logic;
  signal rst_cnt_s : std_logic;
 
begin
 
  process1: process (clk, rst)
  begin
    if (rst ='1') then
      state <= idle;
    elsif rising_edge(clk) then
      state <= next_state;
    end if;
  end process process1;
 
  process2 : process (state, gen_hash, m_tmp, msg_0, msg_1, w_j_tmp, hash_delay(66))
  begin
    next_state <= state;
 
         rst_sch_tmp <= '0';
         rst_comp_tmp <= '0';
         rst_cnt_s <= '0';
 
         start_cnt_tmp <= '0';
         m_tmp <= (others => '0');
 
         gen_hash_tmp <= '0';
 
         case state is
                when idle =>
                        if gen_hash = '1' then
                                gen_hash_tmp <= '1';
                                rst_cnt_s <= '1';
                                next_state <= init;
                        else
                                next_state <= idle;
                        end if;
                when init =>
                        rst_comp_tmp <= '1';
                        start_cnt_tmp <= '1';
 
                        next_state <= run;
                when run =>
                        rst_comp_tmp <= '0';
                        start_cnt_tmp <= '1';
                        m_tmp <= msg_15;
 
                        next_state <= m_1;
                when m_1 =>
                        m_tmp <= msg_14;
                        start_cnt_tmp <= '1';
                        next_state <= m_2;
                when m_2 =>
                        m_tmp <= msg_13;
                        start_cnt_tmp <= '1';
                        next_state <= m_3;
                when m_3 =>
                        m_tmp <= msg_12;
                        start_cnt_tmp <= '1';
                        next_state <= m_4;
                when m_4 =>
                        m_tmp <= msg_11;
                        start_cnt_tmp <= '1';
                        next_state <= m_5;
                when m_5 =>
                        m_tmp <= msg_10;
                        start_cnt_tmp <= '1';
                        next_state <= m_6;
                when m_6 =>
                        m_tmp <= msg_9;
                        start_cnt_tmp <= '1';
                        next_state <= m_7;
                when m_7 =>
                        m_tmp <= msg_8;
                        start_cnt_tmp <= '1';
                        next_state <= m_8;
                when m_8 =>
                        m_tmp <= msg_7;
                        start_cnt_tmp <= '1';
                        next_state <= m_9;
                when m_9 =>
                        m_tmp <= msg_6;
                        start_cnt_tmp <= '1';
                        next_state <= m_10;
                when m_10 =>
                        m_tmp <= msg_5;
                        start_cnt_tmp <= '1';
                        next_state <= m_11;
                when m_11 =>
                        m_tmp <= msg_4;
                        start_cnt_tmp <= '1';
                        next_state <= m_12;
                when m_12 =>
                        m_tmp <= msg_3;
                        start_cnt_tmp <= '1';
                        next_state <= m_13;
                when m_13 =>
                        m_tmp <= msg_2;
                        start_cnt_tmp <= '1';
 
                        next_state <= m_14;
                when m_14 =>
                        m_tmp <= msg_1;
                        start_cnt_tmp <= '1';
                        next_state <= m_15;
                when m_15 =>
                        m_tmp <= msg_0;
                        start_cnt_tmp <= '1';
                        rst_sch_tmp <= '1';
                        next_state <= w_s;
                when w_s =>
                        m_tmp <= w_j_tmp;
                        start_cnt_tmp <= '1';
 
                        if hash_delay(66) = '1' then
                                next_state <= idle;
                        else
                                next_state <= w_s;
                        end if;
         end case;
 
 end process;
 
        message_schedule: sh_reg port map (clk,
                                                                                                  rst_sch_tmp,
                                                                                                  msg_0,
                                                                                                  msg_1,
                                                                                                  msg_2,
                                                                                                  msg_3,
                                                                                                  msg_4,
                                                                                                  msg_5,
                                                                                                  msg_6,
                                                                                                  msg_7,
                                                                                                  msg_8,
                                                                                                  msg_9,
                                                                                                  msg_10,
                                                                                                  msg_11,
                                                                                                  msg_12,
                                                                                                  msg_13,
                                                                                                  msg_14,
                                                                                                  msg_15,
                                                                                                  w_j_tmp);
 
 
        message_compression: msg_comp port map (clk,
                                                                                                                 rst_comp_tmp,
                                                                                                            h_0_tmp,
                                                                                                                 h_1_tmp,
                                                                                                                 h_2_tmp,
                                                                                                                 h_3_tmp,
                                                                                                                 h_4_tmp,
                                                                                                                 h_5_tmp,
                                                                                                                 h_6_tmp,
                                                                                                                 h_7_tmp,
                                                                                                                 m_tmp,
                                                                                                                 k_i_tmp,
                                                                                                                 a_out_tmp,
                                                                                                                 b_out_tmp,
                                                                                                                 c_out_tmp,
                                                                                                                 d_out_tmp,
                                                                                                                 e_out_tmp,
                                                                                                                 f_out_tmp,
                                                                                                                 g_out_tmp,
                                                                                                                 h_out_tmp);
 
        a_out <= a_out_tmp;
        b_out <= b_out_tmp;
        c_out <= c_out_tmp;
        d_out <= d_out_tmp;
        e_out <= e_out_tmp;
        f_out <= f_out_tmp;
        g_out <= g_out_tmp;
        h_out <= h_out_tmp;
 
        k_mem: dual_mem port map(clk,
                                                                         '0',
                                                                         cnt_s, --cnt_s,
                                                                         (others => '0'),
                                                                         (others => '0'),
                                                                         k_i_tmp,
                                                                         open);
 
        cnt_k_pr: process(clk, rst_cnt_s, start_cnt_tmp)
                variable cnt_v : unsigned(5 downto 0) := (others => '0');
        begin
                if rising_edge(clk) then
                        if rst_cnt_s = '1' then
                                cnt_v := (others => '0');
                        elsif
                                start_cnt_tmp = '1' then
                                        cnt_v := cnt_v + 1;
                        end if;
                end if;
 
                cnt_s <= std_logic_vector(cnt_v);
        end process;
 
                        hash_delay(0) <= gen_hash_tmp;
 
                        delay_chain: for i in 1 to 66 generate
                                delay_ff_proc: process(clk)
                                begin
                                        if rising_edge(clk) then
                                                hash_delay(i) <= hash_delay(i-1);
                                        end if;
                                end process delay_ff_proc;
                        end generate delay_chain;
 
                        block_ready <= hash_delay(66);
 
                        final_block: process(clk, rst, gen_hash, hash_delay(65),
                                                                                a_out_tmp,
                                                                                b_out_tmp,
                                                                                c_out_tmp,
                                                                                d_out_tmp,
                                                                                e_out_tmp,
                                                                                f_out_tmp,
                                                                                g_out_tmp,
                                                                                h_out_tmp)
                                variable h_0_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
                                variable h_1_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
                                variable h_2_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
                                variable h_3_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
                                variable h_4_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
                                variable h_5_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
                                variable h_6_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
                                variable h_7_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
                        begin
                                if rising_edge(clk) then
                                        if rst = '1' then
                                                h_0_tmp_v := X"6a09e667";
                                                h_1_tmp_v := X"bb67ae85";
                                                h_2_tmp_v := X"3c6ef372";
                                                h_3_tmp_v := X"a54ff53a";
                                                h_4_tmp_v := X"510e527f";
                                                h_5_tmp_v := X"9b05688c";
                                                h_6_tmp_v := X"1f83d9ab";
                                                h_7_tmp_v := X"5be0cd19";
                                        elsif hash_delay(65) = '1' then
                                                h_0_tmp_v := std_logic_vector(unsigned(h_0_tmp_v) + unsigned(a_out_tmp));
                                                h_1_tmp_v := std_logic_vector(unsigned(h_1_tmp_v) + unsigned(b_out_tmp));
                                                h_2_tmp_v := std_logic_vector(unsigned(h_2_tmp_v) + unsigned(c_out_tmp));
                                                h_3_tmp_v := std_logic_vector(unsigned(h_3_tmp_v) + unsigned(d_out_tmp));
                                                h_4_tmp_v := std_logic_vector(unsigned(h_4_tmp_v) + unsigned(e_out_tmp));
                                                h_5_tmp_v := std_logic_vector(unsigned(h_5_tmp_v) + unsigned(f_out_tmp));
                                                h_6_tmp_v := std_logic_vector(unsigned(h_6_tmp_v) + unsigned(g_out_tmp));
                                                h_7_tmp_v := std_logic_vector(unsigned(h_7_tmp_v) + unsigned(h_out_tmp));
                                        end if;
                                end if;
 
                                h_0_tmp <= h_0_tmp_v;
                                h_1_tmp <= h_1_tmp_v;
                                h_2_tmp <= h_2_tmp_v;
                                h_3_tmp <= h_3_tmp_v;
                                h_4_tmp <= h_4_tmp_v;
                                h_5_tmp <= h_5_tmp_v;
                                h_6_tmp <= h_6_tmp_v;
                                h_7_tmp <= h_7_tmp_v;
 
                        end process;
 
                        hash <= h_0_tmp & h_1_tmp &
                                          h_2_tmp & h_3_tmp &
                                          h_4_tmp & h_5_tmp &
                                          h_6_tmp & h_7_tmp;
end Behavioral;
 

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Subversion Repositories sha256core

[/] [sha256core/] [trunk/] [rtl/] [sha_256.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	entactogen
2
3			`-- Copyright (c) 2013 Antonio de la Piedra`
4
5			`-- This program is free software: you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation, either version 3 of the License, or`
8			`-- (at your option) any later version.`
9
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14
15			`-- You should have received a copy of the GNU General Public License`
16			`-- along with this program. If not, see <http://www.gnu.org/licenses/>.`
17
18			`library IEEE;`
19			`use IEEE.STD_LOGIC_1164.ALL;`
20			`use IEEE.NUMERIC_STD.ALL;`
21
22			`entity sha_256 is`
23			`port(clk : in std_logic;`
24			`rst : in std_logic;`
25			`gen_hash : in std_logic;`
26
27			`msg_0 : in std_logic_vector(31 downto 0);`
28			`msg_1 : in std_logic_vector(31 downto 0);`
29			`msg_2 : in std_logic_vector(31 downto 0);`
30			`msg_3 : in std_logic_vector(31 downto 0);`
31			`msg_4 : in std_logic_vector(31 downto 0);`
32			`msg_5 : in std_logic_vector(31 downto 0);`
33			`msg_6 : in std_logic_vector(31 downto 0);`
34			`msg_7 : in std_logic_vector(31 downto 0);`
35			`msg_8 : in std_logic_vector(31 downto 0);`
36			`msg_9 : in std_logic_vector(31 downto 0);`
37			`msg_10 : in std_logic_vector(31 downto 0);`
38			`msg_11 : in std_logic_vector(31 downto 0);`
39			`msg_12 : in std_logic_vector(31 downto 0);`
40			`msg_13 : in std_logic_vector(31 downto 0);`
41			`msg_14 : in std_logic_vector(31 downto 0);`
42			`msg_15 : in std_logic_vector(31 downto 0);`
43
44			`a_out : out std_logic_vector(31 downto 0);`
45			`b_out : out std_logic_vector(31 downto 0);`
46			`c_out : out std_logic_vector(31 downto 0);`
47			`d_out : out std_logic_vector(31 downto 0);`
48			`e_out : out std_logic_vector(31 downto 0);`
49			`f_out : out std_logic_vector(31 downto 0);`
50			`g_out : out std_logic_vector(31 downto 0);`
51			`h_out : out std_logic_vector(31 downto 0);`
52			`block_ready : out std_logic;`
53			`hash : out std_logic_vector(255 downto 0));`
54			`end sha_256;`
55
56			`architecture Behavioral of sha_256 is`
57
58			`component msg_comp is`
59			`port(clk : in std_logic;`
60			`rst : in std_logic;`
61
62			`h_0 : in std_logic_vector(31 downto 0);`
63			`h_1 : in std_logic_vector(31 downto 0);`
64			`h_2 : in std_logic_vector(31 downto 0);`
65			`h_3 : in std_logic_vector(31 downto 0);`
66			`h_4 : in std_logic_vector(31 downto 0);`
67			`h_5 : in std_logic_vector(31 downto 0);`
68			`h_6 : in std_logic_vector(31 downto 0);`
69			`h_7 : in std_logic_vector(31 downto 0);`
70
71			`w_i : in std_logic_vector(31 downto 0);`
72			`k_i : in std_logic_vector(31 downto 0);`
73
74			`a : out std_logic_vector(31 downto 0);`
75			`b : out std_logic_vector(31 downto 0);`
76			`c : out std_logic_vector(31 downto 0);`
77			`d : out std_logic_vector(31 downto 0);`
78			`e : out std_logic_vector(31 downto 0);`
79			`f : out std_logic_vector(31 downto 0);`
80			`g : out std_logic_vector(31 downto 0);`
81			`h : out std_logic_vector(31 downto 0));`
82			`end component;`
83
84			`component sh_reg is`
85			`port(clk : in std_logic;`
86			`rst : in std_logic;`
87
88			`msg_0 : in std_logic_vector(31 downto 0);`
89			`msg_1 : in std_logic_vector(31 downto 0);`
90			`msg_2 : in std_logic_vector(31 downto 0);`
91			`msg_3 : in std_logic_vector(31 downto 0);`
92			`msg_4 : in std_logic_vector(31 downto 0);`
93			`msg_5 : in std_logic_vector(31 downto 0);`
94			`msg_6 : in std_logic_vector(31 downto 0);`
95			`msg_7 : in std_logic_vector(31 downto 0);`
96			`msg_8 : in std_logic_vector(31 downto 0);`
97			`msg_9 : in std_logic_vector(31 downto 0);`
98			`msg_10 : in std_logic_vector(31 downto 0);`
99			`msg_11 : in std_logic_vector(31 downto 0);`
100			`msg_12 : in std_logic_vector(31 downto 0);`
101			`msg_13 : in std_logic_vector(31 downto 0);`
102			`msg_14 : in std_logic_vector(31 downto 0);`
103			`msg_15 : in std_logic_vector(31 downto 0);`
104
105			`w_j : out std_logic_vector(31 downto 0));`
106			`end component;`
107
108			`component dual_mem is`
109			`generic (ADDR_LENGTH : integer := 6;`
110			`DATA_LENGTH : integer := 32;`
111			`N_ADDR : integer := 64);`
112			`port (clk : in std_logic;`
113			`we : in std_logic;`
114			`a : in std_logic_vector(ADDR_LENGTH - 1 downto 0);`
115			`dpra : in std_logic_vector(ADDR_LENGTH - 1 downto 0);`
116			`di : in std_logic_vector(DATA_LENGTH - 1 downto 0);`
117			`spo : out std_logic_vector(DATA_LENGTH - 1 downto 0);`
118			`dpo : out std_logic_vector(DATA_LENGTH - 1 downto 0));`
119			`end component;`
120
121			`signal w_j_tmp : std_logic_vector(31 downto 0);`
122
123			`signal h_0_tmp : std_logic_vector(31 downto 0);`
124			`signal h_1_tmp : std_logic_vector(31 downto 0);`
125			`signal h_2_tmp : std_logic_vector(31 downto 0);`
126			`signal h_3_tmp : std_logic_vector(31 downto 0);`
127			`signal h_4_tmp : std_logic_vector(31 downto 0);`
128			`signal h_5_tmp : std_logic_vector(31 downto 0);`
129			`signal h_6_tmp : std_logic_vector(31 downto 0);`
130			`signal h_7_tmp : std_logic_vector(31 downto 0);`
131
132			`signal k_i_tmp : std_logic_vector(31 downto 0);`
133
134			`signal start_cnt_tmp, rst_sch_tmp, rst_comp_tmp : std_logic;`
135			`signal cnt_s : std_logic_vector(5 downto 0);`
136
137			`signal m_tmp : std_logic_vector(31 downto 0);`
138
139			`type state_type is (idle, init, run, m_1, m_2, m_3, m_4, m_5, m_6, m_7,`
140			`m_8, m_9, m_10, m_11, m_12, m_13, m_14, m_15, w_s);`
141			`signal state, next_state: state_type ;`
142
143			`type delay_buffer_t is array(67 downto 0) of`
144			`std_logic;`
145
146			`signal hash_delay : delay_buffer_t;`
147
148			`signal a_out_tmp : std_logic_vector(31 downto 0);`
149			`signal b_out_tmp : std_logic_vector(31 downto 0);`
150			`signal c_out_tmp : std_logic_vector(31 downto 0);`
151			`signal d_out_tmp : std_logic_vector(31 downto 0);`
152			`signal e_out_tmp : std_logic_vector(31 downto 0);`
153			`signal f_out_tmp : std_logic_vector(31 downto 0);`
154			`signal g_out_tmp : std_logic_vector(31 downto 0);`
155			`signal h_out_tmp : std_logic_vector(31 downto 0);`
156
157			`signal gen_hash_tmp : std_logic;`
158			`signal rst_cnt_s : std_logic;`
159
160			`begin`
161
162			`process1: process (clk, rst)`
163			`begin`
164			`if (rst ='1') then`
165			`state <= idle;`
166			`elsif rising_edge(clk) then`
167			`state <= next_state;`
168			`end if;`
169			`end process process1;`
170
171			`process2 : process (state, gen_hash, m_tmp, msg_0, msg_1, w_j_tmp, hash_delay(66))`
172			`begin`
173			`next_state <= state;`
174
175			`rst_sch_tmp <= '0';`
176			`rst_comp_tmp <= '0';`
177			`rst_cnt_s <= '0';`
178
179			`start_cnt_tmp <= '0';`
180			`m_tmp <= (others => '0');`
181
182			`gen_hash_tmp <= '0';`
183
184			`case state is`
185			`when idle =>`
186			`if gen_hash = '1' then`
187			`gen_hash_tmp <= '1';`
188			`rst_cnt_s <= '1';`
189			`next_state <= init;`
190			`else`
191			`next_state <= idle;`
192			`end if;`
193			`when init =>`
194			`rst_comp_tmp <= '1';`
195			`start_cnt_tmp <= '1';`
196
197			`next_state <= run;`
198			`when run =>`
199			`rst_comp_tmp <= '0';`
200			`start_cnt_tmp <= '1';`
201			`m_tmp <= msg_15;`
202
203			`next_state <= m_1;`
204			`when m_1 =>`
205			`m_tmp <= msg_14;`
206			`start_cnt_tmp <= '1';`
207			`next_state <= m_2;`
208			`when m_2 =>`
209			`m_tmp <= msg_13;`
210			`start_cnt_tmp <= '1';`
211			`next_state <= m_3;`
212			`when m_3 =>`
213			`m_tmp <= msg_12;`
214			`start_cnt_tmp <= '1';`
215			`next_state <= m_4;`
216			`when m_4 =>`
217			`m_tmp <= msg_11;`
218			`start_cnt_tmp <= '1';`
219			`next_state <= m_5;`
220			`when m_5 =>`
221			`m_tmp <= msg_10;`
222			`start_cnt_tmp <= '1';`
223			`next_state <= m_6;`
224			`when m_6 =>`
225			`m_tmp <= msg_9;`
226			`start_cnt_tmp <= '1';`
227			`next_state <= m_7;`
228			`when m_7 =>`
229			`m_tmp <= msg_8;`
230			`start_cnt_tmp <= '1';`
231			`next_state <= m_8;`
232			`when m_8 =>`
233			`m_tmp <= msg_7;`
234			`start_cnt_tmp <= '1';`
235			`next_state <= m_9;`
236			`when m_9 =>`
237			`m_tmp <= msg_6;`
238			`start_cnt_tmp <= '1';`
239			`next_state <= m_10;`
240			`when m_10 =>`
241			`m_tmp <= msg_5;`
242			`start_cnt_tmp <= '1';`
243			`next_state <= m_11;`
244			`when m_11 =>`
245			`m_tmp <= msg_4;`
246			`start_cnt_tmp <= '1';`
247			`next_state <= m_12;`
248			`when m_12 =>`
249			`m_tmp <= msg_3;`
250			`start_cnt_tmp <= '1';`
251			`next_state <= m_13;`
252			`when m_13 =>`
253			`m_tmp <= msg_2;`
254			`start_cnt_tmp <= '1';`
255
256			`next_state <= m_14;`
257			`when m_14 =>`
258			`m_tmp <= msg_1;`
259			`start_cnt_tmp <= '1';`
260			`next_state <= m_15;`
261			`when m_15 =>`
262			`m_tmp <= msg_0;`
263			`start_cnt_tmp <= '1';`
264			`rst_sch_tmp <= '1';`
265			`next_state <= w_s;`
266			`when w_s =>`
267			`m_tmp <= w_j_tmp;`
268			`start_cnt_tmp <= '1';`
269
270			`if hash_delay(66) = '1' then`
271			`next_state <= idle;`
272			`else`
273			`next_state <= w_s;`
274			`end if;`
275			`end case;`
276
277			`end process;`
278
279			`message_schedule: sh_reg port map (clk,`
280			`rst_sch_tmp,`
281			`msg_0,`
282			`msg_1,`
283			`msg_2,`
284			`msg_3,`
285			`msg_4,`
286			`msg_5,`
287			`msg_6,`
288			`msg_7,`
289			`msg_8,`
290			`msg_9,`
291			`msg_10,`
292			`msg_11,`
293			`msg_12,`
294			`msg_13,`
295			`msg_14,`
296			`msg_15,`
297			`w_j_tmp);`
298
299
300			`message_compression: msg_comp port map (clk,`
301			`rst_comp_tmp,`
302			`h_0_tmp,`
303			`h_1_tmp,`
304			`h_2_tmp,`
305			`h_3_tmp,`
306			`h_4_tmp,`
307			`h_5_tmp,`
308			`h_6_tmp,`
309			`h_7_tmp,`
310			`m_tmp,`
311			`k_i_tmp,`
312			`a_out_tmp,`
313			`b_out_tmp,`
314			`c_out_tmp,`
315			`d_out_tmp,`
316			`e_out_tmp,`
317			`f_out_tmp,`
318			`g_out_tmp,`
319			`h_out_tmp);`
320
321			`a_out <= a_out_tmp;`
322			`b_out <= b_out_tmp;`
323			`c_out <= c_out_tmp;`
324			`d_out <= d_out_tmp;`
325			`e_out <= e_out_tmp;`
326			`f_out <= f_out_tmp;`
327			`g_out <= g_out_tmp;`
328			`h_out <= h_out_tmp;`
329
330			`k_mem: dual_mem port map(clk,`
331			`'0',`
332			`cnt_s, --cnt_s,`
333			`(others => '0'),`
334			`(others => '0'),`
335			`k_i_tmp,`
336			`open);`
337
338			`cnt_k_pr: process(clk, rst_cnt_s, start_cnt_tmp)`
339			`variable cnt_v : unsigned(5 downto 0) := (others => '0');`
340			`begin`
341			`if rising_edge(clk) then`
342			`if rst_cnt_s = '1' then`
343			`cnt_v := (others => '0');`
344			`elsif`
345			`start_cnt_tmp = '1' then`
346			`cnt_v := cnt_v + 1;`
347			`end if;`
348			`end if;`
349
350			`cnt_s <= std_logic_vector(cnt_v);`
351			`end process;`
352
353			`hash_delay(0) <= gen_hash_tmp;`
354
355			`delay_chain: for i in 1 to 66 generate`
356			`delay_ff_proc: process(clk)`
357			`begin`
358			`if rising_edge(clk) then`
359			`hash_delay(i) <= hash_delay(i-1);`
360			`end if;`
361			`end process delay_ff_proc;`
362			`end generate delay_chain;`
363
364			`block_ready <= hash_delay(66);`
365
366			`final_block: process(clk, rst, gen_hash, hash_delay(65),`
367			`a_out_tmp,`
368			`b_out_tmp,`
369			`c_out_tmp,`
370			`d_out_tmp,`
371			`e_out_tmp,`
372			`f_out_tmp,`
373			`g_out_tmp,`
374			`h_out_tmp)`
375			`variable h_0_tmp_v : std_logic_vector(31 downto 0) := (others => '0');`
376			`variable h_1_tmp_v : std_logic_vector(31 downto 0) := (others => '0');`
377			`variable h_2_tmp_v : std_logic_vector(31 downto 0) := (others => '0');`
378			`variable h_3_tmp_v : std_logic_vector(31 downto 0) := (others => '0');`
379			`variable h_4_tmp_v : std_logic_vector(31 downto 0) := (others => '0');`
380			`variable h_5_tmp_v : std_logic_vector(31 downto 0) := (others => '0');`
381			`variable h_6_tmp_v : std_logic_vector(31 downto 0) := (others => '0');`
382			`variable h_7_tmp_v : std_logic_vector(31 downto 0) := (others => '0');`
383			`begin`
384			`if rising_edge(clk) then`
385			`if rst = '1' then`
386			`h_0_tmp_v := X"6a09e667";`
387			`h_1_tmp_v := X"bb67ae85";`
388			`h_2_tmp_v := X"3c6ef372";`
389			`h_3_tmp_v := X"a54ff53a";`
390			`h_4_tmp_v := X"510e527f";`
391			`h_5_tmp_v := X"9b05688c";`
392			`h_6_tmp_v := X"1f83d9ab";`
393			`h_7_tmp_v := X"5be0cd19";`
394			`elsif hash_delay(65) = '1' then`
395			`h_0_tmp_v := std_logic_vector(unsigned(h_0_tmp_v) + unsigned(a_out_tmp));`
396			`h_1_tmp_v := std_logic_vector(unsigned(h_1_tmp_v) + unsigned(b_out_tmp));`
397			`h_2_tmp_v := std_logic_vector(unsigned(h_2_tmp_v) + unsigned(c_out_tmp));`
398			`h_3_tmp_v := std_logic_vector(unsigned(h_3_tmp_v) + unsigned(d_out_tmp));`
399			`h_4_tmp_v := std_logic_vector(unsigned(h_4_tmp_v) + unsigned(e_out_tmp));`
400			`h_5_tmp_v := std_logic_vector(unsigned(h_5_tmp_v) + unsigned(f_out_tmp));`
401			`h_6_tmp_v := std_logic_vector(unsigned(h_6_tmp_v) + unsigned(g_out_tmp));`
402			`h_7_tmp_v := std_logic_vector(unsigned(h_7_tmp_v) + unsigned(h_out_tmp));`
403			`end if;`
404			`end if;`
405
406			`h_0_tmp <= h_0_tmp_v;`
407			`h_1_tmp <= h_1_tmp_v;`
408			`h_2_tmp <= h_2_tmp_v;`
409			`h_3_tmp <= h_3_tmp_v;`
410			`h_4_tmp <= h_4_tmp_v;`
411			`h_5_tmp <= h_5_tmp_v;`
412			`h_6_tmp <= h_6_tmp_v;`
413			`h_7_tmp <= h_7_tmp_v;`
414
415			`end process;`
416
417			`hash <= h_0_tmp & h_1_tmp &`
418			`h_2_tmp & h_3_tmp &`
419			`h_4_tmp & h_5_tmp &`
420			`h_6_tmp & h_7_tmp;`
421			`end Behavioral;`
422