1 |
2 |
entactogen |
|
2 |
|
|
|
3 |
|
|
-- Copyright (c) 2013 Antonio de la Piedra
|
4 |
|
|
|
5 |
|
|
-- This program is free software: you can redistribute it and/or modify
|
6 |
|
|
-- it under the terms of the GNU General Public License as published by
|
7 |
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
8 |
|
|
-- (at your option) any later version.
|
9 |
|
|
|
10 |
|
|
-- This program is distributed in the hope that it will be useful,
|
11 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
13 |
|
|
-- GNU General Public License for more details.
|
14 |
|
|
|
15 |
|
|
-- You should have received a copy of the GNU General Public License
|
16 |
|
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
17 |
|
|
|
18 |
|
|
LIBRARY ieee;
|
19 |
|
|
USE ieee.std_logic_1164.ALL;
|
20 |
|
|
|
21 |
|
|
ENTITY tb_sha_256 IS
|
22 |
|
|
END tb_sha_256;
|
23 |
|
|
|
24 |
|
|
ARCHITECTURE behavior OF tb_sha_256 IS
|
25 |
|
|
|
26 |
|
|
-- Component Declaration for the Unit Under Test (UUT)
|
27 |
|
|
|
28 |
|
|
COMPONENT sha_256
|
29 |
|
|
PORT(
|
30 |
|
|
clk : IN std_logic;
|
31 |
|
|
rst : IN std_logic;
|
32 |
|
|
gen_hash : in std_logic;
|
33 |
|
|
msg_0 : IN std_logic_vector(31 downto 0);
|
34 |
|
|
msg_1 : IN std_logic_vector(31 downto 0);
|
35 |
|
|
msg_2 : IN std_logic_vector(31 downto 0);
|
36 |
|
|
msg_3 : IN std_logic_vector(31 downto 0);
|
37 |
|
|
msg_4 : IN std_logic_vector(31 downto 0);
|
38 |
|
|
msg_5 : IN std_logic_vector(31 downto 0);
|
39 |
|
|
msg_6 : IN std_logic_vector(31 downto 0);
|
40 |
|
|
msg_7 : IN std_logic_vector(31 downto 0);
|
41 |
|
|
msg_8 : IN std_logic_vector(31 downto 0);
|
42 |
|
|
msg_9 : IN std_logic_vector(31 downto 0);
|
43 |
|
|
msg_10 : IN std_logic_vector(31 downto 0);
|
44 |
|
|
msg_11 : IN std_logic_vector(31 downto 0);
|
45 |
|
|
msg_12 : IN std_logic_vector(31 downto 0);
|
46 |
|
|
msg_13 : IN std_logic_vector(31 downto 0);
|
47 |
|
|
msg_14 : IN std_logic_vector(31 downto 0);
|
48 |
|
|
msg_15 : IN std_logic_vector(31 downto 0);
|
49 |
|
|
a_out : OUT std_logic_vector(31 downto 0);
|
50 |
|
|
b_out : OUT std_logic_vector(31 downto 0);
|
51 |
|
|
c_out : OUT std_logic_vector(31 downto 0);
|
52 |
|
|
d_out : OUT std_logic_vector(31 downto 0);
|
53 |
|
|
e_out : OUT std_logic_vector(31 downto 0);
|
54 |
|
|
f_out : OUT std_logic_vector(31 downto 0);
|
55 |
|
|
g_out : OUT std_logic_vector(31 downto 0);
|
56 |
|
|
h_out : OUT std_logic_vector(31 downto 0);
|
57 |
|
|
block_ready : out std_logic;
|
58 |
|
|
hash : out std_logic_vector(255 downto 0));
|
59 |
|
|
END COMPONENT;
|
60 |
|
|
|
61 |
|
|
|
62 |
|
|
--Inputs
|
63 |
|
|
signal clk : std_logic := '0';
|
64 |
|
|
signal rst : std_logic := '0';
|
65 |
|
|
signal gen_hash : std_logic := '0';
|
66 |
|
|
signal msg_0 : std_logic_vector(31 downto 0) := (others => '0');
|
67 |
|
|
signal msg_1 : std_logic_vector(31 downto 0) := (others => '0');
|
68 |
|
|
signal msg_2 : std_logic_vector(31 downto 0) := (others => '0');
|
69 |
|
|
signal msg_3 : std_logic_vector(31 downto 0) := (others => '0');
|
70 |
|
|
signal msg_4 : std_logic_vector(31 downto 0) := (others => '0');
|
71 |
|
|
signal msg_5 : std_logic_vector(31 downto 0) := (others => '0');
|
72 |
|
|
signal msg_6 : std_logic_vector(31 downto 0) := (others => '0');
|
73 |
|
|
signal msg_7 : std_logic_vector(31 downto 0) := (others => '0');
|
74 |
|
|
signal msg_8 : std_logic_vector(31 downto 0) := (others => '0');
|
75 |
|
|
signal msg_9 : std_logic_vector(31 downto 0) := (others => '0');
|
76 |
|
|
signal msg_10 : std_logic_vector(31 downto 0) := (others => '0');
|
77 |
|
|
signal msg_11 : std_logic_vector(31 downto 0) := (others => '0');
|
78 |
|
|
signal msg_12 : std_logic_vector(31 downto 0) := (others => '0');
|
79 |
|
|
signal msg_13 : std_logic_vector(31 downto 0) := (others => '0');
|
80 |
|
|
signal msg_14 : std_logic_vector(31 downto 0) := (others => '0');
|
81 |
|
|
signal msg_15 : std_logic_vector(31 downto 0) := (others => '0');
|
82 |
|
|
|
83 |
|
|
--Outputs
|
84 |
|
|
signal a_out : std_logic_vector(31 downto 0);
|
85 |
|
|
signal b_out : std_logic_vector(31 downto 0);
|
86 |
|
|
signal c_out : std_logic_vector(31 downto 0);
|
87 |
|
|
signal d_out : std_logic_vector(31 downto 0);
|
88 |
|
|
signal e_out : std_logic_vector(31 downto 0);
|
89 |
|
|
signal f_out : std_logic_vector(31 downto 0);
|
90 |
|
|
signal g_out : std_logic_vector(31 downto 0);
|
91 |
|
|
signal h_out : std_logic_vector(31 downto 0);
|
92 |
|
|
signal block_ready : std_logic;
|
93 |
|
|
signal hash : std_logic_vector(255 downto 0);
|
94 |
|
|
|
95 |
|
|
-- Clock period definitions
|
96 |
|
|
constant clk_period : time := 10 ns;
|
97 |
|
|
|
98 |
|
|
BEGIN
|
99 |
|
|
|
100 |
|
|
-- Instantiate the Unit Under Test (UUT)
|
101 |
|
|
uut: sha_256 PORT MAP (
|
102 |
|
|
clk => clk,
|
103 |
|
|
rst => rst,
|
104 |
|
|
gen_hash => gen_hash,
|
105 |
|
|
msg_0 => msg_0,
|
106 |
|
|
msg_1 => msg_1,
|
107 |
|
|
msg_2 => msg_2,
|
108 |
|
|
msg_3 => msg_3,
|
109 |
|
|
msg_4 => msg_4,
|
110 |
|
|
msg_5 => msg_5,
|
111 |
|
|
msg_6 => msg_6,
|
112 |
|
|
msg_7 => msg_7,
|
113 |
|
|
msg_8 => msg_8,
|
114 |
|
|
msg_9 => msg_9,
|
115 |
|
|
msg_10 => msg_10,
|
116 |
|
|
msg_11 => msg_11,
|
117 |
|
|
msg_12 => msg_12,
|
118 |
|
|
msg_13 => msg_13,
|
119 |
|
|
msg_14 => msg_14,
|
120 |
|
|
msg_15 => msg_15,
|
121 |
|
|
a_out => a_out,
|
122 |
|
|
b_out => b_out,
|
123 |
|
|
c_out => c_out,
|
124 |
|
|
d_out => d_out,
|
125 |
|
|
e_out => e_out,
|
126 |
|
|
f_out => f_out,
|
127 |
|
|
g_out => g_out,
|
128 |
|
|
h_out => h_out,
|
129 |
|
|
block_ready => block_ready,
|
130 |
|
|
hash => hash
|
131 |
|
|
);
|
132 |
|
|
|
133 |
|
|
-- Clock process definitions
|
134 |
|
|
clk_process :process
|
135 |
|
|
begin
|
136 |
|
|
clk <= '0';
|
137 |
|
|
wait for clk_period/2;
|
138 |
|
|
clk <= '1';
|
139 |
|
|
wait for clk_period/2;
|
140 |
|
|
end process;
|
141 |
|
|
|
142 |
|
|
|
143 |
|
|
-- Stimulus process
|
144 |
|
|
stim_proc: process
|
145 |
|
|
begin
|
146 |
|
|
wait for clk_period/2 + clk_period;
|
147 |
|
|
|
148 |
|
|
-- Example from "APPENDIX B: SHA-256 EXAMPLES",
|
149 |
|
|
-- B.1 SHA-256 Example (One-Block Message)
|
150 |
|
|
-- FIPS 180-26
|
151 |
|
|
|
152 |
|
|
msg_0 <= X"00000018";
|
153 |
|
|
msg_1 <= X"00000000";
|
154 |
|
|
msg_2 <= X"00000000";
|
155 |
|
|
msg_3 <= X"00000000";
|
156 |
|
|
msg_4 <= X"00000000";
|
157 |
|
|
msg_5 <= X"00000000";
|
158 |
|
|
msg_6 <= X"00000000";
|
159 |
|
|
msg_7 <= X"00000000";
|
160 |
|
|
msg_8 <= X"00000000";
|
161 |
|
|
msg_9 <= X"00000000";
|
162 |
|
|
msg_10 <= X"00000000";
|
163 |
|
|
msg_11 <= X"00000000";
|
164 |
|
|
msg_12 <= X"00000000";
|
165 |
|
|
msg_13 <= X"00000000";
|
166 |
|
|
msg_14 <= X"00000000";
|
167 |
|
|
msg_15 <= X"61626380";
|
168 |
|
|
|
169 |
|
|
rst <= '1';
|
170 |
|
|
wait for clk_period;
|
171 |
|
|
rst <= '0';
|
172 |
|
|
gen_hash <= '1';
|
173 |
|
|
|
174 |
|
|
wait for 0.66 us + clk_period;
|
175 |
|
|
|
176 |
|
|
assert hash = X"ba7816bf8f01cfea414140de5dae2223b00361a396177a9cb410ff61f20015ad"
|
177 |
|
|
report "B.1 Hash output ERROR" severity FAILURE;
|
178 |
|
|
|
179 |
|
|
-- Example from "APPENDIX B: SHA-256 EXAMPLES",
|
180 |
|
|
-- B.1 SHA-256 Example (One-Block Message)
|
181 |
|
|
-- FIPS 180-26
|
182 |
|
|
|
183 |
|
|
gen_hash <= '0';
|
184 |
|
|
wait for clk_period;
|
185 |
|
|
|
186 |
|
|
rst <= '1';
|
187 |
|
|
wait for clk_period;
|
188 |
|
|
rst <= '0';
|
189 |
|
|
|
190 |
|
|
msg_15 <= X"61626364";
|
191 |
|
|
msg_14 <= X"62636465";
|
192 |
|
|
msg_13 <= X"63646566";
|
193 |
|
|
msg_12 <= X"64656667";
|
194 |
|
|
msg_11 <= X"65666768";
|
195 |
|
|
msg_10 <= X"66676869";
|
196 |
|
|
msg_9 <= X"6768696A";
|
197 |
|
|
msg_8 <= X"68696A6B";
|
198 |
|
|
msg_7 <= X"696A6B6C";
|
199 |
|
|
msg_6 <= X"6A6B6C6D";
|
200 |
|
|
msg_5 <= X"6B6C6D6E";
|
201 |
|
|
msg_4 <= X"6C6D6E6F";
|
202 |
|
|
msg_3 <= X"6D6E6F70";
|
203 |
|
|
msg_2 <= X"6E6F7071";
|
204 |
|
|
msg_1 <= X"80000000";
|
205 |
|
|
msg_0 <= X"00000000";
|
206 |
|
|
|
207 |
|
|
gen_hash <= '1';
|
208 |
|
|
|
209 |
|
|
wait for 0.66 us + clk_period;
|
210 |
|
|
|
211 |
|
|
assert hash = X"85e655d6417a17953363376a624cde5c76e09589cac5f811cc4b32c1f20e533a"
|
212 |
|
|
report "B.2 (Part 1) Hash output ERROR" severity FAILURE;
|
213 |
|
|
|
214 |
|
|
gen_hash <= '0';
|
215 |
|
|
wait for clk_period;
|
216 |
|
|
|
217 |
|
|
msg_15 <= X"00000000";
|
218 |
|
|
msg_14 <= X"00000000";
|
219 |
|
|
msg_13 <= X"00000000";
|
220 |
|
|
msg_12 <= X"00000000";
|
221 |
|
|
msg_11 <= X"00000000";
|
222 |
|
|
msg_10 <= X"00000000";
|
223 |
|
|
msg_9 <= X"00000000";
|
224 |
|
|
msg_8 <= X"00000000";
|
225 |
|
|
msg_7 <= X"00000000";
|
226 |
|
|
msg_6 <= X"00000000";
|
227 |
|
|
msg_5 <= X"00000000";
|
228 |
|
|
msg_4 <= X"00000000";
|
229 |
|
|
msg_3 <= X"00000000";
|
230 |
|
|
msg_2 <= X"00000000";
|
231 |
|
|
msg_1 <= X"00000000";
|
232 |
|
|
msg_0 <= X"000001c0";
|
233 |
|
|
|
234 |
|
|
gen_hash <= '1';
|
235 |
|
|
|
236 |
|
|
wait for 0.66 us + clk_period;
|
237 |
|
|
|
238 |
|
|
assert hash = X"248d6a61d20638b8e5c026930c3e6039a33ce45964ff2167f6ecedd419db06c1"
|
239 |
|
|
report "B.2 (Part 2) Hash output ERROR" severity FAILURE;
|
240 |
|
|
|
241 |
|
|
gen_hash <= '0';
|
242 |
|
|
|
243 |
|
|
wait;
|
244 |
|
|
end process;
|
245 |
|
|
|
246 |
|
|
END;
|