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[/] [signed_integer_divider/] [trunk/] [shifter_tb.v] - Blame information for rev 3

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1 3 m99 
module  shifter_tb();
2 
reg     clk=0,rst=0;
3 
always #1 clk=~clk;
4 
initial #100 rst=1;
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6 
// driver
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reg     signed[31:0]data=0,data_1=0;
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reg     state=0;
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reg     [4:0]ct=0;
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always@(posedge clk)begin
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        if(rst)begin
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                case(state)
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                        0:begin
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                                data<=$random;
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                                state<=1;
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                        end
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                        1:begin
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                                if(ct==31)begin
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                                        state<=0;
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                                        ct<=0;
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                                end
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                                else begin
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                                        ct<=ct+1;
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                                        data<=data>>>1;
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                                end
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                        end
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                endcase
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        end
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end
31 
 
32 
// score board
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reg     signd=0;
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reg     [31:0]data_tb=0;
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reg     [4:0]shifted_tb=0;
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always@* begin
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        if(data[31]==0)begin
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                data_1=~data;
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                signd=1;
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        end
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        else begin
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                signd=0;
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                data_1=data;
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        end
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        casex(data_1)
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                32'b10??????????????????????????????:begin
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                        data_tb=data_1[31:0];
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                        shifted_tb=0;
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                end
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                32'b110?????????????????????????????:begin
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                        data_tb={data_1[30:0],{1{signd}}};
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                        shifted_tb=1;
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                end
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                32'b1110????????????????????????????:begin
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                        data_tb={data_1[29:0],{2{signd}}};
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                        shifted_tb=2;
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                end
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                32'b11110???????????????????????????:begin
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                        data_tb={data_1[28:0],{3{signd}}};
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                        shifted_tb=3;
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                end
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                32'b111110??????????????????????????:begin
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                        data_tb={data_1[27:0],{4{signd}}};
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                        shifted_tb=4;
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                end
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                32'b1111110?????????????????????????:begin
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                        data_tb={data_1[26:0],{5{signd}}};
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                        shifted_tb=5;
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                end
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                32'b11111110????????????????????????:begin
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                        data_tb={data_1[25:0],{6{signd}}};
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                        shifted_tb=6;
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                end
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                32'b111111110???????????????????????:begin
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                        data_tb={data_1[24:0],{7{signd}}};
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                        shifted_tb=7;
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                end
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                32'b1111111110??????????????????????:begin
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                        data_tb={data_1[23:0],{8{signd}}};
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                        shifted_tb=8;
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                end
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                32'b11111111110?????????????????????:begin
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                        data_tb={data_1[22:0],{9{signd}}};
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                        shifted_tb=9;
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                end
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                32'b111111111110????????????????????:begin
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                        data_tb={data_1[21:0],{10{signd}}};
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                        shifted_tb=10;
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                end
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                32'b1111111111110???????????????????:begin
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                        data_tb={data_1[20:0],{11{signd}}};
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                        shifted_tb=11;
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                end
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                32'b11111111111110??????????????????:begin
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                        data_tb={data_1[19:0],{12{signd}}};
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                        shifted_tb=12;
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                end
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                32'b111111111111110?????????????????:begin
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                        data_tb={data_1[18:0],{13{signd}}};
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                        shifted_tb=13;
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                end
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                32'b1111111111111110????????????????:begin
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                        data_tb={data_1[17:0],{14{signd}}};
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                        shifted_tb=14;
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                end
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                32'b11111111111111110???????????????:begin
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                        data_tb={data_1[16:0],{15{signd}}};
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                        shifted_tb=15;
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                end
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                32'b111111111111111110??????????????:begin
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                        data_tb={data_1[15:0],{16{signd}}};
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                        shifted_tb=16;
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                end
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                32'b1111111111111111110?????????????:begin
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                        data_tb={data_1[14:0],{17{signd}}};
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                        shifted_tb=17;
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                end
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                32'b11111111111111111110????????????:begin
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                        data_tb={data_1[13:0],{18{signd}}};
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                        shifted_tb=18;
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                end
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                32'b111111111111111111110???????????:begin
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                        data_tb={data_1[12:0],{19{signd}}};
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                        shifted_tb=19;
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                end
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                32'b1111111111111111111110??????????:begin
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                        data_tb={data_1[11:0],{20{signd}}};
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                        shifted_tb=20;
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                end
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                32'b11111111111111111111110?????????:begin
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                        data_tb={data_1[10:0],{21{signd}}};
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                        shifted_tb=21;
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                end
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                32'b111111111111111111111110????????:begin
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                        data_tb={data_1[9:0],{22{signd}}};
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                        shifted_tb=22;
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                end
138 
                32'b1111111111111111111111110???????:begin
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                        data_tb={data_1[8:0],{23{signd}}};
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                        shifted_tb=23;
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                end
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                32'b11111111111111111111111110??????:begin
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                        data_tb={data_1[7:0],{24{signd}}};
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                        shifted_tb=24;
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                end
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                32'b111111111111111111111111110?????:begin
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                        data_tb={data_1[6:0],{25{signd}}};
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                        shifted_tb=25;
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                end
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                32'b1111111111111111111111111110????:begin
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                        data_tb={data_1[5:0],{26{signd}}};
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                        shifted_tb=26;
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                end
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                32'b11111111111111111111111111110???:begin
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                        data_tb={data_1[4:0],{27{signd}}};
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                        shifted_tb=27;
157 
                end
158 
                32'b111111111111111111111111111110??:begin
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                        data_tb={data_1[3:0],{28{signd}}};
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                        shifted_tb=28;
161 
                end
162 
                32'b1111111111111111111111111111110?:begin
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                        data_tb={data_1[2:0],{29{signd}}};
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                        shifted_tb=29;
165 
                end
166 
                32'b11111111111111111111111111111110:begin
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                        data_tb={data_1[1:0],{30{signd}}};
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                        shifted_tb=30;
169 
                end
170 
                32'b11111111111111111111111111111111:begin
171 
                        data_tb={data_1[31],{31{signd}}};
172 
                        shifted_tb=31;
173 
                end
174 
        endcase
175 
        if(signd)data_tb=~data_tb;
176 
end
177 
 
178 
// checker
179 
wire    [31:0]data_o;
180 
wire    [4:0]shifted_o;
181 
always@(negedge clk)
182 
        if(rst)begin
183 
                if(data_o==data_tb)$display("%6d        correct data_o=%h",$time,data_o);
184 
                else $display("%6d      error   data_o=%h       data_tb=%h",$time,data_o,data_tb);
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                if(shifted_o==shifted_tb)$display("%6d  correct shifted_o=%d",$time,shifted_o);
186 
                else $display("%6d      error   shifted_o=%d    shifted_tb=%d",$time,shifted_o,shifted_tb);
187 
        end
188 
 
189 
 
190 
shifter shifter_0(
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data,
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data_o,
193 
shifted_o
194 
);
195 
endmodule

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