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[/] [simple_uart_for_fpga/] [trunk/] [example/] [uart_loopback_tb.vhd] - Blame information for rev 2

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--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- MODULE:  TESTBANCH OF UART LOOPBACK EXAMPLE TOP MODULE
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
-- lICENSE: The MIT License (MIT)
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity UART_LOOPBACK_TB is
end UART_LOOPBACK_TB;
 
architecture FULL of UART_LOOPBACK_TB is
 
        signal CLK           : std_logic := '0';
        signal RST_N         : std_logic := '0';
        signal tx_uart       : std_logic;
        signal rx_uart       : std_logic := '1';
    signal busy          : std_logic;
    signal frame_error   : std_logic;
 
        constant clk_period  : time := 20 ns;
        constant uart_period : time := 8680.56 ns;
        constant data_value  : std_logic_vector(7 downto 0) := "10100111";
        constant data_value2 : std_logic_vector(7 downto 0) := "00110110";
 
begin
 
        utt: entity work.UART_LOOPBACK
    generic map (
        CLK_FREQ    => 50e6,
        BAUD_RATE   => 115200,
        PARITY_BIT  => "none"
    )
    port map (
        CLK         => CLK,
        RST_N       => RST_N,
        -- UART INTERFACE
        UART_TXD    => tx_uart,
        UART_RXD    => rx_uart,
        -- DEBUG INTERFACE
        BUSY        => busy,
        FRAME_ERR   => frame_error
    );
 
        clk_process : process
        begin
                CLK <= '0';
                wait for clk_period/2;
                CLK <= '1';
                wait for clk_period/2;
        end process;
 
        test_rx_uart : process
        begin
                rx_uart <= '1';
                RST_N <= '0';
                wait for 100 ns;
        RST_N <= '1';
 
                wait for uart_period;
 
                rx_uart <= '0'; -- start bit
                wait for uart_period;
 
                for i in 0 to (data_value'LENGTH-1) loop
                    rx_uart <= data_value(i); -- data bits
                    wait for uart_period;
                end loop;
 
                rx_uart <= '1'; -- stop bit
                wait for uart_period;
 
                rx_uart <= '0'; -- start bit
                wait for uart_period;
 
                for i in 0 to (data_value2'LENGTH-1) loop
                        rx_uart <= data_value2(i); -- data bits
                wait for uart_period;
                end loop;
 
                rx_uart <= '1'; -- stop bit
                wait for uart_period;
 
                rx_uart <= '0'; -- start bit
                wait for uart_period;
 
                for i in 0 to (data_value'LENGTH-1) loop
                        rx_uart <= data_value(i); -- data bits
                        wait for uart_period;
                end loop;
 
                rx_uart <= '1'; -- stop bit
                wait for uart_period;
 
                rx_uart <= '0'; -- start bit
                wait for uart_period;
 
                for i in 0 to (data_value2'LENGTH-1) loop
                        rx_uart <= data_value2(i); -- data bits
                        wait for uart_period;
                end loop;
 
                rx_uart <= '1'; -- stop bit
                wait for uart_period;
 
                wait;
 
        end process;
 
end FULL;

Line No.	Rev	Author	Line
1	2	jakubcabal	`--------------------------------------------------------------------------------`
2			`-- PROJECT: SIMPLE UART FOR FPGA`
3			`--------------------------------------------------------------------------------`
4			`-- MODULE: TESTBANCH OF UART LOOPBACK EXAMPLE TOP MODULE`
5			`-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>`
6			`-- lICENSE: The MIT License (MIT)`
7			`-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga`
8			`--------------------------------------------------------------------------------`
9
10			`library IEEE;`
11			`use IEEE.STD_LOGIC_1164.ALL;`
12			`use IEEE.NUMERIC_STD.ALL;`
13
14			`entity UART_LOOPBACK_TB is`
15			`end UART_LOOPBACK_TB;`
16
17			`architecture FULL of UART_LOOPBACK_TB is`
18
19			`signal CLK : std_logic := '0';`
20			`signal RST_N : std_logic := '0';`
21			`signal tx_uart : std_logic;`
22			`signal rx_uart : std_logic := '1';`
23			`signal busy : std_logic;`
24			`signal frame_error : std_logic;`
25
26			`constant clk_period : time := 20 ns;`
27			`constant uart_period : time := 8680.56 ns;`
28			`constant data_value : std_logic_vector(7 downto 0) := "10100111";`
29			`constant data_value2 : std_logic_vector(7 downto 0) := "00110110";`
30
31			`begin`
32
33			`utt: entity work.UART_LOOPBACK`
34			`generic map (`
35			`CLK_FREQ => 50e6,`
36			`BAUD_RATE => 115200,`
37			`PARITY_BIT => "none"`
38			`)`
39			`port map (`
40			`CLK => CLK,`
41			`RST_N => RST_N,`
42			`-- UART INTERFACE`
43			`UART_TXD => tx_uart,`
44			`UART_RXD => rx_uart,`
45			`-- DEBUG INTERFACE`
46			`BUSY => busy,`
47			`FRAME_ERR => frame_error`
48			`);`
49
50			`clk_process : process`
51			`begin`
52			`CLK <= '0';`
53			`wait for clk_period/2;`
54			`CLK <= '1';`
55			`wait for clk_period/2;`
56			`end process;`
57
58			`test_rx_uart : process`
59			`begin`
60			`rx_uart <= '1';`
61			`RST_N <= '0';`
62			`wait for 100 ns;`
63			`RST_N <= '1';`
64
65			`wait for uart_period;`
66
67			`rx_uart <= '0'; -- start bit`
68			`wait for uart_period;`
69
70			`for i in 0 to (data_value'LENGTH-1) loop`
71			`rx_uart <= data_value(i); -- data bits`
72			`wait for uart_period;`
73			`end loop;`
74
75			`rx_uart <= '1'; -- stop bit`
76			`wait for uart_period;`
77
78			`rx_uart <= '0'; -- start bit`
79			`wait for uart_period;`
80
81			`for i in 0 to (data_value2'LENGTH-1) loop`
82			`rx_uart <= data_value2(i); -- data bits`
83			`wait for uart_period;`
84			`end loop;`
85
86			`rx_uart <= '1'; -- stop bit`
87			`wait for uart_period;`
88
89			`rx_uart <= '0'; -- start bit`
90			`wait for uart_period;`
91
92			`for i in 0 to (data_value'LENGTH-1) loop`
93			`rx_uart <= data_value(i); -- data bits`
94			`wait for uart_period;`
95			`end loop;`
96
97			`rx_uart <= '1'; -- stop bit`
98			`wait for uart_period;`
99
100			`rx_uart <= '0'; -- start bit`
101			`wait for uart_period;`
102
103			`for i in 0 to (data_value2'LENGTH-1) loop`
104			`rx_uart <= data_value2(i); -- data bits`
105			`wait for uart_period;`
106			`end loop;`
107
108			`rx_uart <= '1'; -- stop bit`
109			`wait for uart_period;`
110
111			`wait;`
112
113			`end process;`
114
115			`end FULL;`

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[/] [simple_uart_for_fpga/] [trunk/] [example/] [uart_loopback_tb.vhd] - Blame information for rev 2