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[/] [smii/] [trunk/] [rtl/] [verilog/] [generic_buffers.v] - Blame information for rev 3

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1 3 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  SMII                                                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Low pin count serial MII ethernet interface                 ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB          michael.unneback@orsoc.se           ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module obufdff
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  (
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   input d,
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   output reg pad,
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   input clk,
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   input rst
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   );
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   always @ (posedge clk or posedge rst)
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     if (rst)
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       pad <= #1 1'b0;
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     else
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       pad <= #1 d;
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endmodule // obufdff
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module ibufdff
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  (
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   input pad,
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   output reg q,
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   input clk,
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   input rst
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   );
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   always @ (posedge clk or posedge rst)
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     if (rst)
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       q <= #1 1'b0;
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     else
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       q <= #1 pad;
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endmodule // ibufdff
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module iobuftri
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  (
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   input i,
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   input oe,
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   output o,
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   inout pad
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   );
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   assign #1 pad = oe ? i : 1'bz;
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   assign #1 i = pad;
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endmodule // iobuftri
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module obuf
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  (
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   input i,
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   inout pad
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   );
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   assign #1 pad = i;
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endmodule // iobuftri

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