OpenCores
URL https://opencores.org/ocsvn/soc_auto_vbus/soc_auto_vbus/trunk

Subversion Repositories soc_auto_vbus

[/] [soc_auto_vbus/] [trunk/] [src/] [vBUS1_tb.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 pozniak 
library ieee;
2 
use ieee.std_logic_1164.all;
3 
use ieee.std_logic_unsigned.all;
4 
 
5 
entity vBUS_TEST_B_TB is
6 
  generic (
7 
    ADDR_WIDTH                  :integer := 4;
8 
    DATA_WIDTH                  :integer := 4
9 
  );
10 
end entity vBUS_TEST_B_TB;
11 
 
12 
architecture behaviour of vBUS_TEST_B_TB is
13 
 
14 
  signal resN                   :std_logic;
15 
  signal enaN                   :std_logic;
16 
  signal strN                   :std_logic;
17 
  signal rdN                    :std_logic := '1';
18 
  signal addr                   :std_logic_vector(ADDR_WIDTH-1 downto 0);
19 
  signal data_wr                :std_logic_vector(DATA_WIDTH-1 downto 0);
20 
  signal data_rd                :std_logic_vector(DATA_WIDTH-1 downto 0);
21 
 
22 
begin
23 
 
24 
 process is
25 
 begin
26 
   resN <= '0';
27 
   wait for 10ns;
28 
   resN <= '1';
29 
   wait;
30 
 end process;
31 
 
32 
 process is
33 
 begin
34 
   enaN    <= '1';
35 
   strN    <= '1';
36 
   addr    <= (others => '0');
37 
   data_wr <= (others => '0');
38 
   wait for 20 ns;
39 
   for i in 0 to 9 loop
40 
     data_wr <= data_wr + 10;
41 
     wait for 5 ns;
42 
     enaN    <= '0';
43 
     wait for 5 ns;
44 
     strN    <= '0';
45 
     wait for 10 ns;
46 
     strN    <= '1';
47 
     wait for 5 ns;
48 
     enaN    <= '1';
49 
     wait for 5 ns;
50 
     addr <= addr + 1;
51 
   end loop;
52 
   rdN <= not(rdN);
53 
 end process;
54 
 
55 
 inst: entity work.vBUS_TEST_B generic map (ADDR_WIDTH, DATA_WIDTH) port map (resN, enaN, strN, rdN, addr, data_wr, data_rd);
56 
 
57 
end behaviour;
58 
 
59 
-------------------------------------------------------------------------------------------------
60 
 
61 
library ieee;
62 
use ieee.std_logic_1164.all;
63 
use ieee.std_logic_unsigned.all;
64 
use work.vBUS.all;
65 
 
66 
entity vBUS_TEST_A_TB is
67 
  generic (
68 
    ADDR_WIDTH                  :integer := 3;
69 
    DATA_WIDTH                  :integer := 4;
70 
    ITEM_MODE                   :TvBUSnodeMode := WREG
71 
  );
72 
end entity vBUS_TEST_A_TB;
73 
 
74 
architecture behaviour of vBUS_TEST_A_TB is
75 
 
76 
  signal resN                   :std_logic;
77 
  signal enaN                   :std_logic;
78 
  signal strN                   :std_logic;
79 
  signal rdN                    :std_logic := '1';
80 
  signal addr                   :std_logic_vector(ADDR_WIDTH-1 downto 0);
81 
  signal data_wr                :std_logic_vector(DATA_WIDTH-1 downto 0);
82 
  signal data_rd                :std_logic_vector(DATA_WIDTH-1 downto 0);
83 
  signal sdata_wr               :std_logic_vector(DATA_WIDTH/2-1 downto 0);
84 
  signal sena_wr                :std_logic_vector(DATA_WIDTH/2-1 downto 0);
85 
  signal ldata_wr               :std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0);
86 
  signal lena_wr                :std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0);
87 
  signal sdata_rd               :std_logic_vector(DATA_WIDTH/2-1 downto 0);
88 
  signal sena_rd                :std_logic_vector(DATA_WIDTH/2-1 downto 0);
89 
  signal ldata_rd               :std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0);
90 
  signal lena_rd                :std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0);
91 
 
92 
begin
93 
 
94 
 process is
95 
 begin
96 
   resN <= '0';
97 
   wait for 10ns;
98 
   resN <= '1';
99 
   wait;
100 
 end process;
101 
 
102 
 process is
103 
 begin
104 
   enaN     <= '1';
105 
   strN     <= '1';
106 
   addr     <= (others => '0');
107 
   data_wr  <= (others => '0');
108 
   sdata_rd <= (others => '0');
109 
   ldata_rd <= (others => '0');
110 
   wait for 0 ns;
111 
   data_wr  <= data_wr+18;
112 
   sdata_rd <= sdata_rd+16#1#;
113 
   ldata_rd <= ldata_rd+16#23456#;
114 
   wait for 20 ns;
115 
   for i in 0 to 2**ADDR_WIDTH-1 loop
116 
     data_wr  <= data_wr + 17;
117 
     sdata_rd <= sdata_rd+16#1#;
118 
     ldata_rd <= ldata_rd+16#11111#;
119 
     wait for 5 ns;
120 
     enaN    <= '0';
121 
     wait for 5 ns;
122 
     strN    <= '0';
123 
     wait for 10 ns;
124 
     strN    <= '1';
125 
     wait for 5 ns;
126 
     enaN    <= '1';
127 
     wait for 5 ns;
128 
     addr <= addr + 1;
129 
   end loop;
130 
   rdN <= not(rdN);
131 
 end process;
132 
 
133 
 inst: entity work.vBUS_TEST_A
134 
   generic map (ADDR_WIDTH, DATA_WIDTH, ITEM_MODE)
135 
   port map (resN, enaN, strN, rdN, addr, data_wr, data_rd,
136 
             sdata_wr, sena_wr, ldata_wr, lena_wr, sdata_rd, sena_rd, ldata_rd, lena_rd);
137 
 
138 
end behaviour;
139 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.