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[/] [soc_maker/] [trunk/] [spec/] [test_soc_lib/] [cores/] [core_B_rel1/] [core_b.yaml] - Blame information for rev 10

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SOCM_CORE
name: Core B
description: B test IP-core
id: core_B,rel1
date: 1.1.2014
license: LGPL
licensefile:
author: Christian Hättich
authormail: feddischson@gmx.com
repocmd:
toplevel: core_b
interfaces:
  :myifc: SOCM_IFC
    name: core_AB_ifc
    dir: 1
    id: core_AB_ifc,1
    ports:
      :mysig_con1a: SOCM_PORT
         defn: sig_a
         len: 8
      :mysig_con1b: SOCM_PORT
         defn: sig_b
         len: 32
      :mysig_con1c: SOCM_PORT
         defn: sig_c
         len: 1
 
hdlfiles:
  :core_b.vhd: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: ./core_b.vhd
 
 

Line No.	Rev	Author	Line
1	3	feddischso	`SOCM_CORE`
2	10	feddischso	`name: Core B`
3	3	feddischso	`description: B test IP-core`
4	10	feddischso	`id: core_B,rel1`
5	3	feddischso	`date: 1.1.2014`
6			`license: LGPL`
7			`licensefile:`
8			`author: Christian Hättich`
9			`authormail: feddischson@gmx.com`
10			`repocmd:`
11			`toplevel: core_b`
12			`interfaces:`
13			`:myifc: SOCM_IFC`
14			`name: core_AB_ifc`
15			`dir: 1`
16	10	feddischso	`id: core_AB_ifc,1`
17	3	feddischso	`ports:`
18			`:mysig_con1a: SOCM_PORT`
19			`defn: sig_a`
20			`len: 8`
21			`:mysig_con1b: SOCM_PORT`
22			`defn: sig_b`
23			`len: 32`
24			`:mysig_con1c: SOCM_PORT`
25			`defn: sig_c`
26			`len: 1`
27
28			`hdlfiles:`
29			`:core_b.vhd: SOCM_HDL_FILE`
30			`use_syn: true`
31			`use_sys_sim: true`
32			`use_mod_sim: true`
33			`type: vhdl`
34			`path: ./core_b.vhd`
35
36

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[/] [soc_maker/] [trunk/] [spec/] [test_soc_lib/] [cores/] [core_B_rel1/] [core_b.yaml] - Blame information for rev 10