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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [jtag/] [rtl/] [verilog/] [syn/] [jtag_tap.v] - Blame information for rev 135

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/**********************************************************************/
/*                                                                    */
/*             -------                                                */
/*            /   SOC  \                                              */
/*           /    GEN   \                                             */
/*          /    TARGET  \                                            */
/*          ==============                                            */
/*          |            |                                            */
/*          |____________|                                            */
/*                                                                    */
/*  Jtag tap controller for xilinx spartan 3e fpga                    */
/*                                                                    */
/*                                                                    */
/*  Author(s):                                                        */
/*      - John Eaton, jt_eaton@opencores.org                          */
/*                                                                    */
/**********************************************************************/
/*                                                                    */
/*    Copyright (C) <2010>  <Ouabache Design Works>                   */
/*                                                                    */
/*  This source file may be used and distributed without              */
/*  restriction provided that this copyright statement is not         */
/*  removed from the file and that any derivative work contains       */
/*  the original copyright notice and the associated disclaimer.      */
/*                                                                    */
/*  This source file is free software; you can redistribute it        */
/*  and/or modify it under the terms of the GNU Lesser General        */
/*  Public License as published by the Free Software Foundation;      */
/*  either version 2.1 of the License, or (at your option) any        */
/*  later version.                                                    */
/*                                                                    */
/*  This source is distributed in the hope that it will be            */
/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
/*  PURPOSE.  See the GNU Lesser General Public License for more      */
/*  details.                                                          */
/*                                                                    */
/*  You should have received a copy of the GNU Lesser General         */
/*  Public License along with this source; if not, download it        */
/*  from http://www.opencores.org/lgpl.shtml                          */
/*                                                                    */
/**********************************************************************/
 
//////////////////////////////////////////////////////////////////////
//                                                                  //
// This file is a wrapper for the various Xilinx internal BSCAN     //
// TAP devices.  It is designed to take the place of a separate TAP //
// controller in Xilinx systems, to allow a user to access a CPU    //
// debug module (such as that of the OR1200) through the FPGA's     //
// dedicated JTAG / configuration port.                             //
//                                                                  //
//////////////////////////////////////////////////////////////////////
//
 
// Note that the SPARTAN BSCAN controllers have more than one channel.
// This implementation always uses channel 1, this is not configurable.
// If you want to use another channel, then it is probably because you
// want to attach multiple devices to the BSCAN device, which means
// you'll be making changes to this file anyway.
 
 
module cde_jtag_tap
#(parameter  CHIP_ID_VAL=32'h00000000 )
(
 
 input wire  tdo_i,
 
 
 input wire  tclk_pad_in,
 input wire  tms_pad_in,
 input wire  tdi_pad_in,
 input wire  trst_n_pad_in,
 output wire tdo_pad_out,
 
 
 
 
 output wire shiftcapture_dr_clk_o,
 output wire tdi_o,
 output wire test_logic_reset_o,
 output wire shift_dr_o,
 output wire capture_dr_o,
 output wire update_dr_clk_o,
 output wire select_o,
 
 
 input wire  aux_tdo_i,
 output wire aux_shiftcapture_dr_clk_o,
 output wire aux_tdi_o,
 output wire aux_test_logic_reset_o,
 output wire aux_shift_dr_o,
 output wire aux_capture_dr_o,
 output wire aux_update_dr_clk_o,
 output wire aux_select_o
 
);
 
wire       update_dr_i;
 
 
BSCAN_SPARTAN3
BSCAN_SPARTAN3_inst (
   .CAPTURE (capture_dr_o),         // CAPTURE output from TAP controller
   .DRCK1   (user1_clk_i),          // shiftcapture clk for USER1 functions
   .DRCK2   (user2_clk_i),          // shiftcapture clk for USER2 functions
   .RESET   (test_logic_reset_o),   // Reset output from TAP controller
   .SEL1    (select_o),             // USER1 active output
   .SEL2    (aux_select_o),         // USER2 active output
   .SHIFT   (shift_dr_o),           // SHIFT output from TAP controller
   .TDI     (tdi_o),                // TDI output from TAP controller
   .UPDATE  (update_dr_i),          // UPDATE output from TAP controller
   .TDO1    (tdo_i),                // Data input for USER1 function
   .TDO2    (aux_tdo_i)             // Data input for USER2 function
);
 
// Since we don't generate a update_clk we make one from the update state decode
BUFG
update_buf (
   .O       (update_dr_clk_o),        // Clock buffer output
   .I       (update_dr_i)             // Clock buffer input
            );
 
 
BUFG
aux_update_buf (
   .O       (aux_update_dr_clk_o),        // Clock buffer output
   .I       (update_dr_i)             // Clock buffer input
            );
 
 
 
 
 
BUFG
user1_clk_buf (
   .O       (shiftcapture_dr_clk_o),              // Clock buffer output
   .I       (user1_clk_i && user2_clk_i )             // Clock buffer input
            );
 
 
 BUFG
user2_clk_buf (
   .O       (aux_shiftcapture_dr_clk_o),              // Clock buffer output
   .I       (user1_clk_i && user2_clk_i )             // Clock buffer input
            );
 
 
 
assign     aux_tdi_o               = tdi_o;
assign     aux_test_logic_reset_o  = test_logic_reset_o ;
assign     aux_shift_dr_o          = shift_dr_o ;
assign     aux_capture_dr_o        = capture_dr_o;
 
 
 
endmodule

Line No.	Rev	Author	Line
1	131	jt_eaton	`/**********************************************************************/`
2			`/* */`
3			`/* ------- */`
4			`/* / SOC \ */`
5			`/* / GEN \ */`
6			`/* / TARGET \ */`
7			`/* ============== */`
8			`/* \| \| */`
9			`/* \|____________\| */`
10			`/* */`
11			`/* Jtag tap controller for xilinx spartan 3e fpga */`
12			`/* */`
13			`/* */`
14			`/* Author(s): */`
15			`/* - John Eaton, jt_eaton@opencores.org */`
16			`/* */`
17			`/**********************************************************************/`
18			`/* */`
19			`/* Copyright (C) <2010> <Ouabache Design Works> */`
20			`/* */`
21			`/* This source file may be used and distributed without */`
22			`/* restriction provided that this copyright statement is not */`
23			`/* removed from the file and that any derivative work contains */`
24			`/* the original copyright notice and the associated disclaimer. */`
25			`/* */`
26			`/* This source file is free software; you can redistribute it */`
27			`/* and/or modify it under the terms of the GNU Lesser General */`
28			`/* Public License as published by the Free Software Foundation; */`
29			`/* either version 2.1 of the License, or (at your option) any */`
30			`/* later version. */`
31			`/* */`
32			`/* This source is distributed in the hope that it will be */`
33			`/* useful, but WITHOUT ANY WARRANTY; without even the implied */`
34			`/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */`
35			`/* PURPOSE. See the GNU Lesser General Public License for more */`
36			`/* details. */`
37			`/* */`
38			`/* You should have received a copy of the GNU Lesser General */`
39			`/* Public License along with this source; if not, download it */`
40			`/* from http://www.opencores.org/lgpl.shtml */`
41			`/* */`
42			`/**********************************************************************/`
43
44			`//////////////////////////////////////////////////////////////////////`
45			`// //`
46			`// This file is a wrapper for the various Xilinx internal BSCAN //`
47			`// TAP devices. It is designed to take the place of a separate TAP //`
48			`// controller in Xilinx systems, to allow a user to access a CPU //`
49			`// debug module (such as that of the OR1200) through the FPGA's //`
50			`// dedicated JTAG / configuration port. //`
51			`// //`
52			`//////////////////////////////////////////////////////////////////////`
53			`//`
54
55			`// Note that the SPARTAN BSCAN controllers have more than one channel.`
56			`// This implementation always uses channel 1, this is not configurable.`
57			`// If you want to use another channel, then it is probably because you`
58			`// want to attach multiple devices to the BSCAN device, which means`
59			`// you'll be making changes to this file anyway.`
60
61
62			`module cde_jtag_tap`
63	133	jt_eaton	`#(parameter CHIP_ID_VAL=32'h00000000 )`
64	131	jt_eaton	`(`
65
66	135	jt_eaton	`input wire tdo_i,`
67	133	jt_eaton
68
69	135	jt_eaton	`input wire tclk_pad_in,`
70			`input wire tms_pad_in,`
71			`input wire tdi_pad_in,`
72			`input wire trst_n_pad_in,`
73			`output wire tdo_pad_out,`
74
75
76
77
78			`output wire shiftcapture_dr_clk_o,`
79			`output wire tdi_o,`
80			`output wire test_logic_reset_o,`
81			`output wire shift_dr_o,`
82			`output wire capture_dr_o,`
83			`output wire update_dr_clk_o,`
84			`output wire select_o,`
85
86
87			`input wire aux_tdo_i,`
88			`output wire aux_shiftcapture_dr_clk_o,`
89			`output wire aux_tdi_o,`
90			`output wire aux_test_logic_reset_o,`
91			`output wire aux_shift_dr_o,`
92			`output wire aux_capture_dr_o,`
93			`output wire aux_update_dr_clk_o,`
94			`output wire aux_select_o`
95	133	jt_eaton
96	131	jt_eaton	`);`
97
98			`wire update_dr_i;`
99
100
101			`BSCAN_SPARTAN3`
102			`BSCAN_SPARTAN3_inst (`
103			`.CAPTURE (capture_dr_o), // CAPTURE output from TAP controller`
104			`.DRCK1 (user1_clk_i), // shiftcapture clk for USER1 functions`
105			`.DRCK2 (user2_clk_i), // shiftcapture clk for USER2 functions`
106			`.RESET (test_logic_reset_o), // Reset output from TAP controller`
107	133	jt_eaton	`.SEL1 (select_o), // USER1 active output`
108			`.SEL2 (aux_select_o), // USER2 active output`
109	131	jt_eaton	`.SHIFT (shift_dr_o), // SHIFT output from TAP controller`
110			`.TDI (tdi_o), // TDI output from TAP controller`
111			`.UPDATE (update_dr_i), // UPDATE output from TAP controller`
112	133	jt_eaton	`.TDO1 (tdo_i), // Data input for USER1 function`
113			`.TDO2 (aux_tdo_i) // Data input for USER2 function`
114	131	jt_eaton	`);`
115
116			`// Since we don't generate a update_clk we make one from the update state decode`
117			`BUFG`
118			`update_buf (`
119			`.O (update_dr_clk_o), // Clock buffer output`
120			`.I (update_dr_i) // Clock buffer input`
121			`);`
122
123
124			`BUFG`
125	133	jt_eaton	`aux_update_buf (`
126			`.O (aux_update_dr_clk_o), // Clock buffer output`
127			`.I (update_dr_i) // Clock buffer input`
128			`);`
129
130
131
132
133
134			`BUFG`
135	131	jt_eaton	`user1_clk_buf (`
136			`.O (shiftcapture_dr_clk_o), // Clock buffer output`
137			`.I (user1_clk_i && user2_clk_i ) // Clock buffer input`
138			`);`
139
140
141	133	jt_eaton	`BUFG`
142			`user2_clk_buf (`
143			`.O (aux_shiftcapture_dr_clk_o), // Clock buffer output`
144			`.I (user1_clk_i && user2_clk_i ) // Clock buffer input`
145			`);`
146	131	jt_eaton
147
148
149	133	jt_eaton	`assign aux_tdi_o = tdi_o;`
150			`assign aux_test_logic_reset_o = test_logic_reset_o ;`
151			`assign aux_shift_dr_o = shift_dr_o ;`
152			`assign aux_capture_dr_o = capture_dr_o;`
153	131	jt_eaton
154	133	jt_eaton
155	131	jt_eaton
156	133	jt_eaton	`endmodule`

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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [jtag/] [rtl/] [verilog/] [syn/] [jtag_tap.v] - Blame information for rev 135