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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_be.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://digilentinc.com"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
digilentinc.com
Nexys2
sram
be
 
 
 

 
 
 
 
 
 

 
 

 
 
 
   
      fs-sim
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
   
      fs-lint
 
 
      
        dest_dir../verilog/lint/
        verilogSourcelibraryDir
      
 
   
 
 
 

 
 
 
 
 
 

 
                
                        
                                verilog
                                verilog
                                cde_sram_be
                                
                                        
                                                ADDR
                                                8
                                        
                                        
                                                WIDTH
                                                8
                                        
                                        
                                                WORDS
                                                256
                                        
                                        
                                                WRITETHRU
                                                1
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
 
  
 
 
        
        rtl
        verilog:Kactus2:
        verilog
        
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lint:*Lint:*
 
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
 
 
      
 
 
 

ADDR10
WIDTH8
WORDS1024
WRITETHRU0

 

 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
be
wire
in

 
 
 
 
addr
wire
in
ADDR-10

 
 
wdata
wire
in
WIDTH-10

 
rdata
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_be.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://digilentinc.com"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`digilentinc.com`
13			`Nexys2`
14			`sram`
15			`be`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21
22
23
24
25
26	135	jt_eaton
27	131	jt_eaton
28
29	135	jt_eaton
30	131	jt_eaton
31
32
33	135	jt_eaton
34			`fs-sim`
35	131	jt_eaton
36	135	jt_eaton
37			`dest_dir../verilog/`
38			`verilogSourcelibraryDir`
39
40	131	jt_eaton
41	135	jt_eaton
42	131	jt_eaton
43
44	135	jt_eaton
45			`fs-syn`
46	131	jt_eaton
47	135	jt_eaton
48			`dest_dir../verilog/`
49			`verilogSourcelibraryDir`
50
51	131	jt_eaton
52
53
54	135	jt_eaton
55	131	jt_eaton
56
57	135	jt_eaton
58			`fs-lint`
59	131	jt_eaton
60
61	135	jt_eaton
62			`dest_dir../verilog/lint/`
63			`verilogSourcelibraryDir`
64
65	131	jt_eaton
66	135	jt_eaton
67	131	jt_eaton
68
69
70	135	jt_eaton
71	131	jt_eaton
72
73
74
75
76
77	135	jt_eaton
78	131	jt_eaton
79	135	jt_eaton
80
81			`verilog`
82			`verilog`
83			`cde_sram_be`
84
85
86			`ADDR`
87			`8`
88
89
90			`WIDTH`
91			`8`
92
93
94			`WORDS`
95			`256`
96
97
98			`WRITETHRU`
99			`1`
100
101
102
103			`fs-sim`
104
105
106
107	131	jt_eaton
108	135	jt_eaton
109
110
111
112
113
114
115			`rtl`
116			`verilog:Kactus2:`
117			`verilog`
118
119
120
121			`sim:Simulation:`
122	131	jt_eaton
123	135	jt_eaton	`Verilog`
124
125
126			`fs-sim`
127
128
129	131	jt_eaton
130	135	jt_eaton
131			`syn:Synthesis:`
132	131	jt_eaton
133	135	jt_eaton	`Verilog`
134
135
136			`fs-syn`
137
138
139	131	jt_eaton
140
141	135	jt_eaton
142			`lint:Lint:`
143	131	jt_eaton
144	135	jt_eaton	`Verilog`
145
146
147			`fs-lint`
148
149
150	131	jt_eaton
151
152
153
154
155
156	135	jt_eaton
157	131	jt_eaton
158
159
160	135	jt_eaton
161			`ADDR10`
162			`WIDTH8`
163			`WORDS1024`
164			`WRITETHRU0`
165
166	131	jt_eaton
167	135	jt_eaton
168	131	jt_eaton
169	135	jt_eaton	`clk`
170			`wire`
171			`in`
172
173	131	jt_eaton
174	135	jt_eaton	`cs`
175			`wire`
176			`in`
177
178	131	jt_eaton
179	135	jt_eaton	`wr`
180			`wire`
181			`in`
182
183	131	jt_eaton
184	135	jt_eaton	`rd`
185			`wire`
186			`in`
187
188	131	jt_eaton
189	135	jt_eaton	`be`
190			`wire`
191			`in`
192
193	131	jt_eaton
194
195
196
197	135	jt_eaton	`addr`
198			`wire`
199			`in`
200			`ADDR-10`
201
202	131	jt_eaton
203
204	135	jt_eaton	`wdata`
205			`wire`
206			`in`
207			`WIDTH-10`
208
209	131	jt_eaton
210	135	jt_eaton	`rdata`
211			`reg`
212			`out`
213			`WIDTH-10`
214
215	131	jt_eaton
216
217
218	135	jt_eaton
219	131	jt_eaton
220	135	jt_eaton
221	131	jt_eaton
222
223
224
225
226
227
228
229
230
231
232	135	jt_eaton