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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [sim/] [testbenches/] [xml/] [fpgas_iceskate_default_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
digilentinc.com
nexys2
iceskate
default_tb
 
 
 
 
 

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      iceskate_default_tb
    
  

 
 
 

 
 
 
 
 

 
 
 
 
  
 
 
 
   
     Dut
     
   
 
 
   
     BFM
     
   
 
 
 
 
  
 
 
 
 
 
 
 
 
       
 
 
 
              
              Dut
              :*Simulation:*
              Dut
              
 
              
              BFM
              :*Simulation:*
              BFM
              
 
 
 
 
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
    JTAG_MODEL_DIVCNT     4'h4
    JTAG_MODEL_SIZE       4

 
 
 
 
 
 
 

 
 
 
  
 
 
 
    
      fs-common
 
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
 
    
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/iceskate_default_tb
        verilogSourcemodule
      
 
    
 
 
 
 
 
 
 
  
 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [sim/] [testbenches/] [xml/] [fpgas_iceskate_default_tb.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
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31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36			`digilentinc.com`
37			`nexys2`
38			`iceskate`
39			`default_tb`
40
41
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48			`gen_verilog`
49			`104.0`
50			`none`
51			`:common:`
52			`tools/verilog/gen_verilog`
53
54
55			`destination`
56			`iceskate_default_tb`
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79			`Dut`
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85			`BFM`
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106			`Dut`
107			`:Simulation:`
108			`Dut`
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112			`BFM`
113			`:Simulation:`
114			`BFM`
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124			`icarus`
125
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127			`ipxact:library="Testbench"`
128			`ipxact:name="toolflow"`
129			`ipxact:version="icarus"/>`
130
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137			`common:common:`
138			`Verilog`
139
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141			`fs-common`
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147			`sim:Simulation:`
148			`Verilog`
149
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151			`fs-sim`
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156			`lint:Lint:`
157			`Verilog`
158
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160			`fs-lint`
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168			`JTAG_MODEL_DIVCNT 4'h4`
169			`JTAG_MODEL_SIZE 4`
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187			`fs-common`
188
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192			`../verilog/tb.ext`
193			`verilogSourcefragment`
194
195
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204			`fs-sim`
205
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208			`../verilog/common/iceskate_default_tb`
209			`verilogSourcemodule`
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