OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [lattice.com/] [fpgas/] [ip/] [iceskate/] [rtl/] [xml/] [fpgas_iceskate_core.xml] - Blame information for rev 135

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 135 jt_eaton
2
30
31
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
32
xmlns:socgen="http://opencores.org"
33
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
34
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
35
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
36
 
37
lattice.com
38
fpgas
39
iceskate
40
core
41
 
42
43
 
44
45
  gen_verilog
46
  104.0
47
  none
48
  :*common:*
49
  tools/verilog/gen_verilog
50
  
51
    
52
      destination
53
      iceskate_core
54
    
55
  
56
57
 
58
59
 
60
 
61
 
62
 
63
 
64
 
65
66
 
67
 
68
 
69
 
70
 
71
 
72
 
73
  
74
 
75
 
76
              
77
              padring:*Simulation:*
78
              
79
              
80
                                   ipxact:library="fpgas"
81
                                   ipxact:name="iceskate"
82
                                   ipxact:version="CORE"/>
83
              
84
              
85
 
86
 
87
 
88
 
89
 
90
 
91
              
92
              verilog:*Simulation:*
93
              
94
              
95
                                   ipxact:library="Testbench"
96
                                   ipxact:name="toolflow"
97
                                   ipxact:version="verilog"/>
98
              
99
              
100
 
101
              
102
              common:*common:*
103
              Verilog
104
              
105
                     
106
                            fs-common
107
                     
108
              
109
 
110
              
111
              sim:*Simulation:*
112
              Verilog
113
              
114
                     
115
                            fs-sim
116
                     
117
              
118
 
119
 
120
              
121
              syn:*Synthesis:*
122
              Verilog
123
              
124
                     
125
                            fs-sim
126
                     
127
              
128
 
129
      
130
 
131
132
 
133
 
134
 
135
 
136
137
 
138
   
139
      fs-common
140
 
141
 
142
 
143
 
144
      
145
        
146
        ../verilog/top
147
        verilogSourcefragment
148
      
149
 
150
 
151
 
152
 
153
      
154
        ../verilog
155
        verilogSourcelibraryDir
156
      
157
 
158
 
159
 
160
   
161
 
162
 
163
   
164
      fs-sim
165
 
166
      
167
        
168
        ../verilog/copyright
169
        verilogSourceinclude
170
      
171
 
172
      
173
        
174
        ../verilog/common/iceskate_core
175
        verilogSourcemodule
176
      
177
 
178
 
179
 
180
 
181
 
182
 
183
   
184
 
185
 
186
 
187
 
188
 
189
190
 
191
 
192
 
193
 
194
 
195
196
 
197
 
198
 
199
 
200
 
201
 
202
 
203
 
204
 
205
 
206
 
207
 
208
 
209
 
210
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.